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25402f5d HL |
1 | /** @file\r |
2 | *\r | |
3 | * Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r | |
4 | *\r | |
4059386c | 5 | * SPDX-License-Identifier: BSD-2-Clause-Patent\r |
25402f5d HL |
6 | *\r |
7 | **/\r | |
8 | \r | |
9 | #ifndef __AARCH64_MMU_H_\r | |
10 | #define __AARCH64_MMU_H_\r | |
11 | \r | |
12 | //\r | |
13 | // Memory Attribute Indirection register Definitions\r | |
14 | //\r | |
15 | #define MAIR_ATTR_DEVICE_MEMORY 0x0ULL\r | |
16 | #define MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE 0x44ULL\r | |
17 | #define MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH 0xBBULL\r | |
18 | #define MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK 0xFFULL\r | |
19 | \r | |
20 | #define MAIR_ATTR(n,value) ((value) << (((n) >> 2)*8))\r | |
21 | \r | |
22 | //\r | |
23 | // Long-descriptor Translation Table format\r | |
24 | //\r | |
25 | \r | |
26 | // Return the smallest offset from the table level.\r | |
27 | // The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0\r | |
28 | #define TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel) (12 + ((3 - (TableLevel)) * 9))\r | |
29 | \r | |
88333703 | 30 | #define TT_BLOCK_ENTRY_SIZE_AT_LEVEL(Level) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(Level))\r |
25402f5d HL |
31 | \r |
32 | // Get the associated entry in the given Translation Table\r | |
33 | #define TT_GET_ENTRY_FOR_ADDRESS(TranslationTable, Level, Address) \\r | |
88333703 | 34 | ((UINTN)(TranslationTable) + ((((UINTN)(Address) >> TT_ADDRESS_OFFSET_AT_LEVEL(Level)) & (BIT9-1)) * sizeof(UINT64)))\r |
25402f5d HL |
35 | \r |
36 | // Return the smallest address granularity from the table level.\r | |
37 | // The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0\r | |
88333703 | 38 | #define TT_ADDRESS_AT_LEVEL(TableLevel) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel))\r |
25402f5d | 39 | \r |
d9680b94 OM |
40 | #define TT_LAST_BLOCK_ADDRESS(TranslationTable, EntryCount) \\r |
41 | ((UINT64*)((EFI_PHYSICAL_ADDRESS)(TranslationTable) + (((EntryCount) - 1) * sizeof(UINT64))))\r | |
42 | \r | |
25402f5d HL |
43 | // There are 512 entries per table when 4K Granularity\r |
44 | #define TT_ENTRY_COUNT 512\r | |
45 | #define TT_ALIGNMENT_BLOCK_ENTRY BIT12\r | |
46 | #define TT_ALIGNMENT_DESCRIPTION_TABLE BIT12\r | |
47 | \r | |
829ea9b2 HG |
48 | #define TT_ADDRESS_MASK_BLOCK_ENTRY (0xFFFFFFFFFULL << 12)\r |
49 | #define TT_ADDRESS_MASK_DESCRIPTION_TABLE (0xFFFFFFFFFULL << 12)\r | |
25402f5d HL |
50 | \r |
51 | #define TT_TYPE_MASK 0x3\r | |
52 | #define TT_TYPE_TABLE_ENTRY 0x3\r | |
53 | #define TT_TYPE_BLOCK_ENTRY 0x1\r | |
54 | #define TT_TYPE_BLOCK_ENTRY_LEVEL3 0x3\r | |
55 | \r | |
56 | #define TT_ATTR_INDX_MASK (0x7 << 2)\r | |
57 | #define TT_ATTR_INDX_DEVICE_MEMORY (0x0 << 2)\r | |
58 | #define TT_ATTR_INDX_MEMORY_NON_CACHEABLE (0x1 << 2)\r | |
59 | #define TT_ATTR_INDX_MEMORY_WRITE_THROUGH (0x2 << 2)\r | |
60 | #define TT_ATTR_INDX_MEMORY_WRITE_BACK (0x3 << 2)\r | |
61 | \r | |
62 | #define TT_AP_MASK (0x3UL << 6)\r | |
63 | #define TT_AP_NO_RW (0x0UL << 6)\r | |
64 | #define TT_AP_RW_RW (0x1UL << 6)\r | |
65 | #define TT_AP_NO_RO (0x2UL << 6)\r | |
66 | #define TT_AP_RO_RO (0x3UL << 6)\r | |
67 | \r | |
68 | #define TT_NS BIT5\r | |
69 | #define TT_AF BIT10\r | |
70 | \r | |
0c9a522f AB |
71 | #define TT_SH_NON_SHAREABLE (0x0 << 8)\r |
72 | #define TT_SH_OUTER_SHAREABLE (0x2 << 8)\r | |
73 | #define TT_SH_INNER_SHAREABLE (0x3 << 8)\r | |
74 | #define TT_SH_MASK (0x3 << 8)\r | |
75 | \r | |
25402f5d | 76 | #define TT_PXN_MASK BIT53\r |
2afeabd1 AB |
77 | #define TT_UXN_MASK BIT54 // EL1&0\r |
78 | #define TT_XN_MASK BIT54 // EL2 / EL3\r | |
25402f5d HL |
79 | \r |
80 | #define TT_ATTRIBUTES_MASK ((0xFFFULL << 52) | (0x3FFULL << 2))\r | |
81 | \r | |
82 | #define TT_TABLE_PXN BIT59\r | |
2afeabd1 AB |
83 | #define TT_TABLE_UXN BIT60 // EL1&0\r |
84 | #define TT_TABLE_XN BIT60 // EL2 / EL3\r | |
25402f5d HL |
85 | #define TT_TABLE_NS BIT63\r |
86 | \r | |
87 | #define TT_TABLE_AP_MASK (BIT62 | BIT61)\r | |
88 | #define TT_TABLE_AP_NO_PERMISSION (0x0ULL << 61)\r | |
89 | #define TT_TABLE_AP_EL0_NO_ACCESS (0x1ULL << 61)\r | |
90 | #define TT_TABLE_AP_NO_WRITE_ACCESS (0x2ULL << 61)\r | |
91 | \r | |
92 | //\r | |
93 | // Translation Control Register\r | |
94 | //\r | |
31441f29 | 95 | #define TCR_T0SZ_MASK 0x3FUL\r |
25402f5d | 96 | \r |
31441f29 AB |
97 | #define TCR_PS_4GB (0UL << 16)\r |
98 | #define TCR_PS_64GB (1UL << 16)\r | |
99 | #define TCR_PS_1TB (2UL << 16)\r | |
100 | #define TCR_PS_4TB (3UL << 16)\r | |
101 | #define TCR_PS_16TB (4UL << 16)\r | |
102 | #define TCR_PS_256TB (5UL << 16)\r | |
25402f5d | 103 | \r |
31441f29 AB |
104 | #define TCR_TG0_4KB (0UL << 14)\r |
105 | #define TCR_TG1_4KB (2UL << 30)\r | |
25402f5d | 106 | \r |
62436c21 OM |
107 | #define TCR_IPS_4GB (0ULL << 32)\r |
108 | #define TCR_IPS_64GB (1ULL << 32)\r | |
109 | #define TCR_IPS_1TB (2ULL << 32)\r | |
110 | #define TCR_IPS_4TB (3ULL << 32)\r | |
111 | #define TCR_IPS_16TB (4ULL << 32)\r | |
112 | #define TCR_IPS_256TB (5ULL << 32)\r | |
25402f5d | 113 | \r |
31441f29 | 114 | #define TCR_EPD1 (1UL << 23)\r |
25402f5d HL |
115 | \r |
116 | #define TTBR_ASID_FIELD (48)\r | |
117 | #define TTBR_ASID_MASK (0xFF << TTBR_ASID_FIELD)\r | |
118 | #define TTBR_BADDR_MASK (0xFFFFFFFFFFFF ) // The width of this field depends on the values in TxSZ. Addr occupies bottom 48bits\r | |
119 | \r | |
120 | #define TCR_EL1_T0SZ_FIELD (0)\r | |
121 | #define TCR_EL1_EPD0_FIELD (7)\r | |
122 | #define TCR_EL1_IRGN0_FIELD (8)\r | |
123 | #define TCR_EL1_ORGN0_FIELD (10)\r | |
124 | #define TCR_EL1_SH0_FIELD (12)\r | |
125 | #define TCR_EL1_TG0_FIELD (14)\r | |
126 | #define TCR_EL1_T1SZ_FIELD (16)\r | |
127 | #define TCR_EL1_A1_FIELD (22)\r | |
128 | #define TCR_EL1_EPD1_FIELD (23)\r | |
129 | #define TCR_EL1_IRGN1_FIELD (24)\r | |
130 | #define TCR_EL1_ORGN1_FIELD (26)\r | |
131 | #define TCR_EL1_SH1_FIELD (28)\r | |
132 | #define TCR_EL1_TG1_FIELD (30)\r | |
133 | #define TCR_EL1_IPS_FIELD (32)\r | |
134 | #define TCR_EL1_AS_FIELD (36)\r | |
135 | #define TCR_EL1_TBI0_FIELD (37)\r | |
136 | #define TCR_EL1_TBI1_FIELD (38)\r | |
31441f29 AB |
137 | #define TCR_EL1_T0SZ_MASK (0x1FUL << TCR_EL1_T0SZ_FIELD)\r |
138 | #define TCR_EL1_EPD0_MASK (0x01UL << TCR_EL1_EPD0_FIELD)\r | |
139 | #define TCR_EL1_IRGN0_MASK (0x03UL << TCR_EL1_IRGN0_FIELD)\r | |
140 | #define TCR_EL1_ORGN0_MASK (0x03UL << TCR_EL1_ORGN0_FIELD)\r | |
141 | #define TCR_EL1_SH0_MASK (0x03UL << TCR_EL1_SH0_FIELD)\r | |
142 | #define TCR_EL1_TG0_MASK (0x01UL << TCR_EL1_TG0_FIELD)\r | |
143 | #define TCR_EL1_T1SZ_MASK (0x1FUL << TCR_EL1_T1SZ_FIELD)\r | |
144 | #define TCR_EL1_A1_MASK (0x01UL << TCR_EL1_A1_FIELD)\r | |
145 | #define TCR_EL1_EPD1_MASK (0x01UL << TCR_EL1_EPD1_FIELD)\r | |
146 | #define TCR_EL1_IRGN1_MASK (0x03UL << TCR_EL1_IRGN1_FIELD)\r | |
147 | #define TCR_EL1_ORGN1_MASK (0x03UL << TCR_EL1_ORGN1_FIELD)\r | |
148 | #define TCR_EL1_SH1_MASK (0x03UL << TCR_EL1_SH1_FIELD)\r | |
149 | #define TCR_EL1_TG1_MASK (0x01UL << TCR_EL1_TG1_FIELD)\r | |
150 | #define TCR_EL1_IPS_MASK (0x07UL << TCR_EL1_IPS_FIELD)\r | |
151 | #define TCR_EL1_AS_MASK (0x01UL << TCR_EL1_AS_FIELD)\r | |
152 | #define TCR_EL1_TBI0_MASK (0x01UL << TCR_EL1_TBI0_FIELD)\r | |
153 | #define TCR_EL1_TBI1_MASK (0x01UL << TCR_EL1_TBI1_FIELD)\r | |
154 | \r | |
155 | \r | |
156 | #define TCR_EL23_T0SZ_FIELD (0)\r | |
157 | #define TCR_EL23_IRGN0_FIELD (8)\r | |
158 | #define TCR_EL23_ORGN0_FIELD (10)\r | |
159 | #define TCR_EL23_SH0_FIELD (12)\r | |
25402f5d | 160 | #define TCR_EL23_TG0_FIELD (14)\r |
31441f29 AB |
161 | #define TCR_EL23_PS_FIELD (16)\r |
162 | #define TCR_EL23_T0SZ_MASK (0x1FUL << TCR_EL23_T0SZ_FIELD)\r | |
163 | #define TCR_EL23_IRGN0_MASK (0x03UL << TCR_EL23_IRGN0_FIELD)\r | |
164 | #define TCR_EL23_ORGN0_MASK (0x03UL << TCR_EL23_ORGN0_FIELD)\r | |
165 | #define TCR_EL23_SH0_MASK (0x03UL << TCR_EL23_SH0_FIELD)\r | |
166 | #define TCR_EL23_TG0_MASK (0x01UL << TCR_EL23_TG0_FIELD)\r | |
167 | #define TCR_EL23_PS_MASK (0x07UL << TCR_EL23_PS_FIELD)\r | |
168 | \r | |
169 | \r | |
170 | #define TCR_RGN_OUTER_NON_CACHEABLE (0x0UL << 10)\r | |
171 | #define TCR_RGN_OUTER_WRITE_BACK_ALLOC (0x1UL << 10)\r | |
172 | #define TCR_RGN_OUTER_WRITE_THROUGH (0x2UL << 10)\r | |
173 | #define TCR_RGN_OUTER_WRITE_BACK_NO_ALLOC (0x3UL << 10)\r | |
174 | \r | |
175 | #define TCR_RGN_INNER_NON_CACHEABLE (0x0UL << 8)\r | |
176 | #define TCR_RGN_INNER_WRITE_BACK_ALLOC (0x1UL << 8)\r | |
177 | #define TCR_RGN_INNER_WRITE_THROUGH (0x2UL << 8)\r | |
178 | #define TCR_RGN_INNER_WRITE_BACK_NO_ALLOC (0x3UL << 8)\r | |
179 | \r | |
180 | #define TCR_SH_NON_SHAREABLE (0x0UL << 12)\r | |
181 | #define TCR_SH_OUTER_SHAREABLE (0x2UL << 12)\r | |
182 | #define TCR_SH_INNER_SHAREABLE (0x3UL << 12)\r | |
183 | \r | |
184 | #define TCR_PASZ_32BITS_4GB (0x0UL)\r | |
185 | #define TCR_PASZ_36BITS_64GB (0x1UL)\r | |
186 | #define TCR_PASZ_40BITS_1TB (0x2UL)\r | |
187 | #define TCR_PASZ_42BITS_4TB (0x3UL)\r | |
188 | #define TCR_PASZ_44BITS_16TB (0x4UL)\r | |
189 | #define TCR_PASZ_48BITS_256TB (0x5UL)\r | |
25402f5d HL |
190 | \r |
191 | // The value written to the T*SZ fields are defined as 2^(64-T*SZ). So a 39Bit\r | |
192 | // Virtual address range for 512GB of virtual space sets T*SZ to 25\r | |
193 | #define INPUT_ADDRESS_SIZE_TO_TxSZ(a) (64 - a)\r | |
194 | \r | |
195 | // Uses LPAE Page Table format\r | |
196 | \r | |
197 | #endif // __AARCH64_MMU_H_\r | |
198 | \r |