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3127615b | 1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2011, ARM Limited. All rights reserved.\r | |
4 | \r | |
5 | This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #ifndef __ARM_CORTEX_A9_H__\r | |
16 | #define __ARM_CORTEX_A9_H__\r | |
17 | \r | |
18 | #include <Chipset/ArmV7.h>\r | |
19 | \r | |
20 | //\r | |
21 | // Cortex A9 feature bit definitions\r | |
22 | //\r | |
23 | #define A9_FEATURE_PARITY (1<<9)\r | |
24 | #define A9_FEATURE_AOW (1<<8)\r | |
25 | #define A9_FEATURE_EXCL (1<<7)\r | |
26 | #define A9_FEATURE_SMP (1<<6)\r | |
27 | #define A9_FEATURE_FOZ (1<<3)\r | |
28 | #define A9_FEATURE_DPREF (1<<2)\r | |
29 | #define A9_FEATURE_HINT (1<<1)\r | |
30 | #define A9_FEATURE_FWD (1<<0)\r | |
31 | \r | |
32 | //\r | |
33 | // Cortex A9 Watchdog\r | |
34 | //\r | |
35 | #define ARM_A9_WATCHDOG_REGION 0x600\r | |
36 | \r | |
37 | #define ARM_A9_WATCHDOG_LOAD_REGISTER 0x20\r | |
38 | #define ARM_A9_WATCHDOG_CONTROL_REGISTER 0x28\r | |
39 | \r | |
40 | #define ARM_A9_WATCHDOG_WATCHDOG_MODE (1 << 3)\r | |
41 | #define ARM_A9_WATCHDOG_TIMER_MODE (0 << 3)\r | |
42 | #define ARM_A9_WATCHDOG_SINGLE_SHOT (0 << 1)\r | |
43 | #define ARM_A9_WATCHDOG_AUTORELOAD (1 << 1)\r | |
44 | #define ARM_A9_WATCHDOG_ENABLE 1\r | |
45 | \r | |
46 | //\r | |
47 | // SCU register offsets & masks\r | |
48 | //\r | |
49 | #define A9_SCU_CONTROL_OFFSET 0x0\r | |
50 | #define A9_SCU_CONFIG_OFFSET 0x4\r | |
51 | #define A9_SCU_INVALL_OFFSET 0xC\r | |
52 | #define A9_SCU_FILT_START_OFFSET 0x40\r | |
53 | #define A9_SCU_FILT_END_OFFSET 0x44\r | |
54 | #define A9_SCU_SACR_OFFSET 0x50\r | |
55 | #define A9_SCU_SSACR_OFFSET 0x54\r | |
56 | \r | |
57 | \r | |
58 | UINTN\r | |
59 | EFIAPI\r | |
60 | ArmGetScuBaseAddress (\r | |
61 | VOID\r | |
62 | );\r | |
63 | \r | |
64 | #endif\r | |
65 | \r |