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11c20f4e | 1 | #/** @file\r |
2 | #\r | |
1bc83266 | 3 | # Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r |
11c20f4e | 4 | # \r |
5 | # This program and the accompanying materials \r | |
6 | # are licensed and made available under the terms and conditions of the BSD License \r | |
7 | # which accompanies this distribution. The full text of the license may be found at \r | |
8 | # http://opensource.org/licenses/bsd-license.php \r | |
9 | #\r | |
10 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
11 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
12 | #\r | |
13 | #**/\r | |
14 | \r | |
15 | [Defines]\r | |
16 | DEC_SPECIFICATION = 0x00010005\r | |
17 | PACKAGE_NAME = ArmPlatformPkg\r | |
18 | PACKAGE_GUID = 3308e0a0-1d94-11e0-915c-0002a5d5c51b \r | |
19 | PACKAGE_VERSION = 0.1\r | |
20 | \r | |
21 | ################################################################################\r | |
22 | #\r | |
23 | # Include Section - list of Include Paths that are provided by this package.\r | |
24 | # Comments are used for Keywords and Module Types.\r | |
25 | #\r | |
26 | # Supported Module Types:\r | |
27 | # BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r | |
28 | #\r | |
29 | ################################################################################\r | |
30 | [Includes.common]\r | |
31 | Include # Root include for the package\r | |
32 | \r | |
33 | [Guids.common]\r | |
34 | gArmPlatformTokenSpaceGuid = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }\r | |
35 | #\r | |
36 | # Following Guid must match FILE_GUID in MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r | |
37 | #\r | |
38 | gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } }\r | |
39 | \r | |
8fc38a3f | 40 | ## Include/Guid/ArmGlobalVariableHob.h\r |
41 | gArmGlobalVariableGuid = { 0xc3253c90, 0xa24f, 0x4599, { 0xa6, 0x64, 0x1f, 0x88, 0x13, 0x77, 0x8f, 0xc9} }\r | |
42 | \r | |
43 | [Ppis]\r | |
44 | ## Include/Ppi/ArmGlobalVariable.h\r | |
45 | gArmGlobalVariablePpiGuid = { 0xab1c1816, 0xd542, 0x4e6f, {0x9b, 0x1e, 0x8e, 0xcd, 0x92, 0x53, 0xe2, 0xe7} }\r | |
46 | \r | |
11c20f4e | 47 | [PcdsFeatureFlag.common]\r |
48 | # Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0.\r | |
49 | gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012\r | |
50 | \r | |
51 | gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE|BOOLEAN|0x00000001\r | |
52 | gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|FALSE|BOOLEAN|0x00000002\r | |
53 | gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004\r | |
54 | \r | |
68dda854 | 55 | gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked|FALSE|BOOLEAN|0x0000003C\r |
d8c4bb9a OM |
56 | \r |
57 | # Disable the GOP controller on ExitBootServices(). By default the value is FALSE,\r | |
58 | # we assume the OS will handle the FrameBuffer from the UEFI GOP information.\r | |
59 | gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D\r | |
60 | \r | |
11c20f4e | 61 | [PcdsFixedAtBuild.common]\r |
695df8ba | 62 | gArmPlatformTokenSpaceGuid.PcdCoreCount|1|UINT32|0x00000039\r |
2dbcb8f0 | 63 | gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038\r |
64 | \r | |
11c20f4e | 65 | # Stack for CPU Cores in Secure Mode\r |
66 | gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT32|0x00000005\r | |
2dbcb8f0 | 67 | gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000|UINT32|0x00000036\r |
68 | gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006\r | |
11c20f4e | 69 | \r |
11c20f4e | 70 | # Stack for CPU Cores in Non Secure Mode\r |
2dbcb8f0 | 71 | gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT32|0x00000009\r |
72 | gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037\r | |
73 | gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A\r | |
11c20f4e | 74 | \r |
75 | # Size of the region used by UEFI in permanent memory (Reserved 128MB by default)\r | |
76 | gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015\r | |
77 | \r | |
78 | # Size to reserve in the primary core stack for PEI Global Variables\r | |
79 | # = sizeof(UINTN) /* PcdPeiServicePtr or HobListPtr */\r | |
80 | gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize|0x4|UINT32|0x00000016\r | |
81 | # PeiServicePtr and HobListPtr shares the same location in the PEI Global Variable list\r | |
82 | # PeiServicePtr is only valid with PEI Core and HobListPtr only when the PEI Core is skipped. \r | |
83 | gArmPlatformTokenSpaceGuid.PcdPeiServicePtrGlobalOffset|0x0|UINT32|0x00000017\r | |
84 | gArmPlatformTokenSpaceGuid.PcdHobListPtrGlobalOffset|0x0|UINT32|0x00000018\r | |
85 | \r | |
8fc38a3f | 86 | # Size to reserve in the primary core stack for SEC Global Variables\r |
87 | gArmPlatformTokenSpaceGuid.PcdSecGlobalVariableSize|0x0|UINT32|0x00000031\r | |
88 | \r | |
11c20f4e | 89 | #\r |
90 | # ARM Primecells\r | |
91 | #\r | |
92 | \r | |
93 | ## SP804 DualTimer\r | |
94 | gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|1|UINT32|0x0000001D\r | |
95 | gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|0|UINT32|0x0000001E\r | |
96 | gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0|UINT32|0x0000002A\r | |
97 | gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0|UINT32|0x0000002B\r | |
98 | gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0|UINT32|0x0000002C\r | |
99 | \r | |
100 | ## SP805 Watchdog\r | |
101 | gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0|UINT32|0x00000023\r | |
102 | gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021\r | |
103 | \r | |
104 | ## PL011 UART\r | |
051e63bb | 105 | gArmPlatformTokenSpaceGuid.PL011UartClkInHz|24000000|UINT32|0x0000001F\r |
106 | gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020\r | |
107 | gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D\r | |
11c20f4e | 108 | \r |
109 | ## PL031 RealTimeClock\r | |
110 | gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024\r | |
111 | gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022\r | |
112 | \r | |
113 | ## PL061 GPIO\r | |
114 | gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025\r | |
115 | \r | |
98622390 | 116 | ## PL111 Lcd & HdLcd\r |
11c20f4e | 117 | gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026\r |
118 | gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027\r | |
119 | \r | |
120 | ## PL180 MCI\r | |
121 | gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028\r | |
122 | gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029\r | |
123 | \r | |
124 | #\r | |
125 | # BDS - Boot Manager\r | |
126 | #\r | |
127 | gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Platform"|VOID*|0x00000019\r | |
128 | gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Default Boot Device"|VOID*|0x0000000C\r | |
129 | gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L""|VOID*|0x0000000D\r | |
130 | gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L""|VOID*|0x0000000E\r | |
131 | gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|""|VOID*|0x000000F\r | |
132 | # PcdDefaultBootType define the type of the binary pointed by PcdDefaultBootDevicePath: \r | |
133 | # - 0 = an EFI application\r | |
134 | # - 1 = a Linux kernel with ATAG support\r | |
135 | # - 2 = a Linux kernel with FDT support\r | |
136 | gArmPlatformTokenSpaceGuid.PcdDefaultBootType|0|UINT32|0x00000010\r | |
137 | gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L""|VOID*|0x00000011\r | |
138 | \r | |
139 | ## Timeout value for displaying progressing bar in before boot OS.\r | |
140 | # According to UEFI 2.0 spec, the default TimeOut should be 0xffff.\r | |
141 | gArmPlatformTokenSpaceGuid.PcdPlatformBootTimeOut|0xffff|UINT16|0x0000001A\r | |
142 | \r | |
143 | gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B\r | |
144 | gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C\r | |
1bc83266 HL |
145 | \r |
146 | [PcdsFixedAtBuild.ARM]\r | |
147 | # Stack for CPU Cores in Secure Monitor Mode\r | |
148 | gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007\r | |
149 | gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008\r | |
150 | \r | |
151 | [PcdsFixedAtBuild.AARCH64]\r | |
152 | # The Secure World is only running in EL3. Only one set of stacks is needed for AArch64.\r | |
153 | # The Secure stacks are described by PcdCPUCoresSecStackBase, PcdCPUCoreSecPrimaryStackSize\r | |
154 | # and PcdCPUCoreSecSecondaryStackSize\r | |
155 | gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007\r | |
156 | gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x0|UINT32|0x00000008\r | |
157 | \r |