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1d5d0ae9 | 1 | /** @file |
2 | * | |
3 | * Copyright (c) 2011, ARM Limited. All rights reserved. | |
4 | * | |
5 | * This program and the accompanying materials | |
6 | * are licensed and made available under the terms and conditions of the BSD License | |
7 | * which accompanies this distribution. The full text of the license may be found at | |
8 | * http://opensource.org/licenses/bsd-license.php | |
9 | * | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
12 | * | |
13 | **/ | |
14 | ||
15 | #ifndef __PL011_UART_H__ | |
16 | #define __PL011_UART_H__ | |
17 | ||
18 | #define SERIAL_PORT_MAX_TIMEOUT 100000000 // 100 seconds | |
19 | ||
20 | // PL011 Registers | |
21 | #define UARTDR 0x000 | |
22 | #define UARTRSR 0x004 | |
23 | #define UARTECR 0x004 | |
24 | #define UARTFR 0x018 | |
25 | #define UARTILPR 0x020 | |
26 | #define UARTIBRD 0x024 | |
27 | #define UARTFBRD 0x028 | |
28 | #define UARTLCR_H 0x02C | |
29 | #define UARTCR 0x030 | |
30 | #define UARTIFLS 0x034 | |
31 | #define UARTIMSC 0x038 | |
32 | #define UARTRIS 0x03C | |
33 | #define UARTMIS 0x040 | |
34 | #define UARTICR 0x044 | |
35 | #define UARTDMACR 0x048 | |
36 | ||
37 | #define UART_115200_IDIV 13 // Integer Part | |
38 | #define UART_115200_FDIV 1 // Fractional Part | |
39 | #define UART_38400_IDIV 39 | |
40 | #define UART_38400_FDIV 5 | |
41 | #define UART_19200_IDIV 12 | |
42 | #define UART_19200_FDIV 37 | |
43 | ||
44 | // data status bits | |
45 | #define UART_DATA_ERROR_MASK 0x0F00 | |
46 | ||
47 | // status reg bits | |
48 | #define UART_STATUS_ERROR_MASK 0x0F | |
49 | ||
50 | // flag reg bits | |
51 | #define UART_TX_EMPTY_FLAG_MASK 0x80 | |
52 | #define UART_RX_FULL_FLAG_MASK 0x40 | |
53 | #define UART_TX_FULL_FLAG_MASK 0x20 | |
54 | #define UART_RX_EMPTY_FLAG_MASK 0x10 | |
55 | #define UART_BUSY_FLAG_MASK 0x08 | |
56 | ||
57 | // control reg bits | |
58 | #define UART_CTSEN_CONTROL_MASK 0x8000 | |
59 | #define UART_RTSEN_CONTROL_MASK 0x4000 | |
60 | #define UART_RTS_CONTROL_MASK 0x0800 | |
61 | #define UART_DTR_CONTROL_MASK 0x0400 | |
62 | ||
63 | #endif |