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1d5d0ae9 | 1 | /** @file\r |
2 | * Main file supporting the transition to PEI Core in Normal World for Versatile Express\r | |
3 | *\r | |
6dafb303 | 4 | * Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r |
1d5d0ae9 | 5 | *\r |
6dafb303 OM |
6 | * This program and the accompanying materials\r |
7 | * are licensed and made available under the terms and conditions of the BSD License\r | |
8 | * which accompanies this distribution. The full text of the license may be found at\r | |
9 | * http://opensource.org/licenses/bsd-license.php\r | |
10 | *\r | |
11 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
1d5d0ae9 | 13 | *\r |
14 | **/\r | |
15 | \r | |
1d5d0ae9 | 16 | #include <Library/BaseLib.h>\r |
a6caee65 | 17 | #include <Library/DebugAgentLib.h>\r |
1d5d0ae9 | 18 | #include <Library/ArmLib.h>\r |
8fc38a3f | 19 | \r |
20 | #include <Ppi/ArmGlobalVariable.h>\r | |
1d5d0ae9 | 21 | \r |
f598bf12 | 22 | #include "PrePeiCore.h"\r |
1d5d0ae9 | 23 | \r |
93d451c6 | 24 | EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi = { PrePeiCoreTemporaryRamSupport };\r |
8fc38a3f | 25 | ARM_GLOBAL_VARIABLE_PPI mGlobalVariablePpi = { PrePeiCoreGetGlobalVariableMemory };\r |
1d5d0ae9 | 26 | \r |
8fc38a3f | 27 | EFI_PEI_PPI_DESCRIPTOR gCommonPpiTable[] = {\r |
1d5d0ae9 | 28 | {\r |
8fc38a3f | 29 | EFI_PEI_PPI_DESCRIPTOR_PPI,\r |
1d5d0ae9 | 30 | &gEfiTemporaryRamSupportPpiGuid,\r |
93d451c6 | 31 | &mTemporaryRamSupportPpi\r |
8fc38a3f | 32 | },\r |
33 | {\r | |
77de7e53 | 34 | EFI_PEI_PPI_DESCRIPTOR_PPI,\r |
8fc38a3f | 35 | &gArmGlobalVariablePpiGuid,\r |
36 | &mGlobalVariablePpi\r | |
1d5d0ae9 | 37 | }\r |
38 | };\r | |
39 | \r | |
77de7e53 | 40 | VOID\r |
41 | CreatePpiList (\r | |
42 | OUT UINTN *PpiListSize,\r | |
43 | OUT EFI_PEI_PPI_DESCRIPTOR **PpiList\r | |
44 | )\r | |
45 | {\r | |
46 | EFI_PEI_PPI_DESCRIPTOR *PlatformPpiList;\r | |
47 | UINTN PlatformPpiListSize;\r | |
48 | UINTN ListBase;\r | |
49 | EFI_PEI_PPI_DESCRIPTOR *LastPpi;\r | |
50 | \r | |
51 | // Get the Platform PPIs\r | |
52 | PlatformPpiListSize = 0;\r | |
53 | ArmPlatformGetPlatformPpiList (&PlatformPpiListSize, &PlatformPpiList);\r | |
54 | \r | |
55 | // Copy the Common and Platform PPis in Temporrary Memory\r | |
56 | ListBase = PcdGet32 (PcdCPUCoresStackBase);\r | |
57 | CopyMem ((VOID*)ListBase, gCommonPpiTable, sizeof(gCommonPpiTable));\r | |
58 | CopyMem ((VOID*)(ListBase + sizeof(gCommonPpiTable)), PlatformPpiList, PlatformPpiListSize);\r | |
59 | \r | |
60 | // Set the Terminate flag on the last PPI entry\r | |
61 | LastPpi = (EFI_PEI_PPI_DESCRIPTOR*)ListBase + ((sizeof(gCommonPpiTable) + PlatformPpiListSize) / sizeof(EFI_PEI_PPI_DESCRIPTOR)) - 1;\r | |
62 | LastPpi->Flags |= EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;\r | |
63 | \r | |
64 | *PpiList = (EFI_PEI_PPI_DESCRIPTOR*)ListBase;\r | |
65 | *PpiListSize = sizeof(gCommonPpiTable) + PlatformPpiListSize;\r | |
66 | }\r | |
67 | \r | |
1d5d0ae9 | 68 | VOID\r |
69 | CEntryPoint (\r | |
0787bc61 | 70 | IN UINTN MpId,\r |
1d5d0ae9 | 71 | IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint\r |
72 | )\r | |
73 | {\r | |
6dafb303 OM |
74 | // Data Cache enabled on Primary core when MMU is enabled.\r |
75 | ArmDisableDataCache ();\r | |
76 | // Invalidate Data cache\r | |
77 | ArmInvalidateDataCache ();\r | |
78 | // Invalidate instruction cache\r | |
a9d7090f | 79 | ArmInvalidateInstructionCache ();\r |
6dafb303 | 80 | // Enable Instruction Caches on all cores.\r |
f598bf12 | 81 | ArmEnableInstructionCache ();\r |
1d5d0ae9 | 82 | \r |
83 | //\r | |
84 | // Note: Doesn't have to Enable CPU interface in non-secure world,\r | |
85 | // as Non-secure interface is already enabled in Secure world.\r | |
86 | //\r | |
87 | \r | |
a9d7090f | 88 | // Write VBAR - The Exception Vector table must be aligned to its requirement\r |
1bc83266 HL |
89 | //TODO: Fix baseTools to ensure the Exception Vector Table is correctly aligned in AArch64\r |
90 | //ASSERT(((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);\r | |
a9d7090f | 91 | ArmWriteVBar ((UINTN)PeiVectorTable);\r |
1d5d0ae9 | 92 | \r |
93 | //Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.\r | |
94 | \r | |
77de7e53 | 95 | // If not primary Jump to Secondary Main\r |
bebda7ce | 96 | if (ArmPlatformIsPrimaryCore (MpId)) {\r |
a6caee65 | 97 | // Initialize the Debug Agent for Source Level Debugging\r |
98 | InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);\r | |
99 | SaveAndSetDebugTimerInterrupt (TRUE);\r | |
100 | \r | |
f437141a | 101 | // Initialize the platform specific controllers\r |
102 | ArmPlatformInitialize (MpId);\r | |
103 | \r | |
a6caee65 | 104 | // Goto primary Main.\r |
f598bf12 | 105 | PrimaryMain (PeiCoreEntryPoint);\r |
1d5d0ae9 | 106 | } else {\r |
0787bc61 | 107 | SecondaryMain (MpId);\r |
1d5d0ae9 | 108 | }\r |
109 | \r | |
110 | // PEI Core should always load and never return\r | |
111 | ASSERT (FALSE);\r | |
112 | }\r | |
113 | \r | |
114 | EFI_STATUS\r | |
115 | EFIAPI\r | |
93d451c6 | 116 | PrePeiCoreTemporaryRamSupport (\r |
1d5d0ae9 | 117 | IN CONST EFI_PEI_SERVICES **PeiServices,\r |
118 | IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,\r | |
119 | IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,\r | |
120 | IN UINTN CopySize\r | |
121 | )\r | |
122 | {\r | |
93d451c6 | 123 | VOID *OldHeap;\r |
124 | VOID *NewHeap;\r | |
125 | VOID *OldStack;\r | |
126 | VOID *NewStack;\r | |
127 | \r | |
128 | OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;\r | |
129 | NewHeap = (VOID*)((UINTN)PermanentMemoryBase + (CopySize >> 1));\r | |
130 | \r | |
131 | OldStack = (VOID*)((UINTN)TemporaryMemoryBase + (CopySize >> 1));\r | |
132 | NewStack = (VOID*)(UINTN)PermanentMemoryBase;\r | |
133 | \r | |
134 | //\r | |
135 | // Migrate the temporary memory stack to permanent memory stack.\r | |
1d5d0ae9 | 136 | //\r |
93d451c6 | 137 | CopyMem (NewStack, OldStack, CopySize >> 1);\r |
138 | \r | |
139 | //\r | |
140 | // Migrate the temporary memory heap to permanent memory heap.\r | |
f598bf12 | 141 | //\r |
93d451c6 | 142 | CopyMem (NewHeap, OldHeap, CopySize >> 1);\r |
143 | \r | |
144 | SecSwitchStack ((UINTN)NewStack - (UINTN)OldStack);\r | |
1d5d0ae9 | 145 | \r |
93d451c6 | 146 | return EFI_SUCCESS;\r |
147 | }\r | |
1d5d0ae9 | 148 | \r |
8fc38a3f | 149 | EFI_STATUS\r |
150 | PrePeiCoreGetGlobalVariableMemory (\r | |
151 | OUT EFI_PHYSICAL_ADDRESS *GlobalVariableBase\r | |
152 | )\r | |
153 | {\r | |
154 | ASSERT (GlobalVariableBase != NULL);\r | |
155 | \r | |
156 | *GlobalVariableBase = (UINTN)PcdGet32 (PcdCPUCoresStackBase) +\r | |
157 | (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) -\r | |
158 | (UINTN)PcdGet32 (PcdPeiGlobalVariableSize);\r | |
159 | \r | |
1d5d0ae9 | 160 | return EFI_SUCCESS;\r |
161 | }\r | |
162 | \r |