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1d5d0ae9 | 1 | /** @file\r |
2 | * Main file supporting the transition to PEI Core in Normal World for Versatile Express\r | |
3 | *\r | |
6d0ca257 | 4 | * Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r |
1d5d0ae9 | 5 | *\r |
f4dfad05 | 6 | * SPDX-License-Identifier: BSD-2-Clause-Patent\r |
1d5d0ae9 | 7 | *\r |
8 | **/\r | |
9 | \r | |
1d5d0ae9 | 10 | #include <Library/BaseLib.h>\r |
a6caee65 | 11 | #include <Library/DebugAgentLib.h>\r |
1d5d0ae9 | 12 | #include <Library/ArmLib.h>\r |
8fc38a3f | 13 | \r |
f598bf12 | 14 | #include "PrePeiCore.h"\r |
1d5d0ae9 | 15 | \r |
0c7cc4fb | 16 | CONST EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi = { PrePeiCoreTemporaryRamSupport };\r |
1d5d0ae9 | 17 | \r |
0c7cc4fb | 18 | CONST EFI_PEI_PPI_DESCRIPTOR gCommonPpiTable[] = {\r |
1d5d0ae9 | 19 | {\r |
8fc38a3f | 20 | EFI_PEI_PPI_DESCRIPTOR_PPI,\r |
1d5d0ae9 | 21 | &gEfiTemporaryRamSupportPpiGuid,\r |
0c7cc4fb | 22 | (VOID *) &mTemporaryRamSupportPpi\r |
1d5d0ae9 | 23 | }\r |
24 | };\r | |
25 | \r | |
77de7e53 | 26 | VOID\r |
27 | CreatePpiList (\r | |
28 | OUT UINTN *PpiListSize,\r | |
29 | OUT EFI_PEI_PPI_DESCRIPTOR **PpiList\r | |
30 | )\r | |
31 | {\r | |
32 | EFI_PEI_PPI_DESCRIPTOR *PlatformPpiList;\r | |
33 | UINTN PlatformPpiListSize;\r | |
34 | UINTN ListBase;\r | |
35 | EFI_PEI_PPI_DESCRIPTOR *LastPpi;\r | |
36 | \r | |
37 | // Get the Platform PPIs\r | |
38 | PlatformPpiListSize = 0;\r | |
39 | ArmPlatformGetPlatformPpiList (&PlatformPpiListSize, &PlatformPpiList);\r | |
40 | \r | |
16f3544d | 41 | // Copy the Common and Platform PPis in Temporary Memory\r |
bb5420bb | 42 | ListBase = PcdGet64 (PcdCPUCoresStackBase);\r |
77de7e53 | 43 | CopyMem ((VOID*)ListBase, gCommonPpiTable, sizeof(gCommonPpiTable));\r |
44 | CopyMem ((VOID*)(ListBase + sizeof(gCommonPpiTable)), PlatformPpiList, PlatformPpiListSize);\r | |
45 | \r | |
46 | // Set the Terminate flag on the last PPI entry\r | |
47 | LastPpi = (EFI_PEI_PPI_DESCRIPTOR*)ListBase + ((sizeof(gCommonPpiTable) + PlatformPpiListSize) / sizeof(EFI_PEI_PPI_DESCRIPTOR)) - 1;\r | |
48 | LastPpi->Flags |= EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;\r | |
49 | \r | |
50 | *PpiList = (EFI_PEI_PPI_DESCRIPTOR*)ListBase;\r | |
51 | *PpiListSize = sizeof(gCommonPpiTable) + PlatformPpiListSize;\r | |
52 | }\r | |
53 | \r | |
1d5d0ae9 | 54 | VOID\r |
55 | CEntryPoint (\r | |
0787bc61 | 56 | IN UINTN MpId,\r |
1d5d0ae9 | 57 | IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint\r |
58 | )\r | |
59 | {\r | |
6dafb303 OM |
60 | // Data Cache enabled on Primary core when MMU is enabled.\r |
61 | ArmDisableDataCache ();\r | |
62 | // Invalidate Data cache\r | |
63 | ArmInvalidateDataCache ();\r | |
64 | // Invalidate instruction cache\r | |
a9d7090f | 65 | ArmInvalidateInstructionCache ();\r |
6dafb303 | 66 | // Enable Instruction Caches on all cores.\r |
f598bf12 | 67 | ArmEnableInstructionCache ();\r |
1d5d0ae9 | 68 | \r |
69 | //\r | |
70 | // Note: Doesn't have to Enable CPU interface in non-secure world,\r | |
71 | // as Non-secure interface is already enabled in Secure world.\r | |
72 | //\r | |
73 | \r | |
a9d7090f | 74 | // Write VBAR - The Exception Vector table must be aligned to its requirement\r |
6d0ca257 OM |
75 | // Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure\r |
76 | // 'Align=4K' is defined into your FDF for this module.\r | |
77 | ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);\r | |
a9d7090f | 78 | ArmWriteVBar ((UINTN)PeiVectorTable);\r |
1d5d0ae9 | 79 | \r |
a6a835bd AB |
80 | // Enable Floating Point\r |
81 | if (FixedPcdGet32 (PcdVFPEnabled)) {\r | |
82 | ArmEnableVFP ();\r | |
83 | }\r | |
84 | \r | |
1d5d0ae9 | 85 | //Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.\r |
86 | \r | |
77de7e53 | 87 | // If not primary Jump to Secondary Main\r |
bebda7ce | 88 | if (ArmPlatformIsPrimaryCore (MpId)) {\r |
a6caee65 | 89 | // Initialize the Debug Agent for Source Level Debugging\r |
90 | InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);\r | |
91 | SaveAndSetDebugTimerInterrupt (TRUE);\r | |
92 | \r | |
f437141a | 93 | // Initialize the platform specific controllers\r |
94 | ArmPlatformInitialize (MpId);\r | |
95 | \r | |
a6caee65 | 96 | // Goto primary Main.\r |
f598bf12 | 97 | PrimaryMain (PeiCoreEntryPoint);\r |
1d5d0ae9 | 98 | } else {\r |
0787bc61 | 99 | SecondaryMain (MpId);\r |
1d5d0ae9 | 100 | }\r |
101 | \r | |
102 | // PEI Core should always load and never return\r | |
103 | ASSERT (FALSE);\r | |
104 | }\r | |
105 | \r | |
106 | EFI_STATUS\r | |
107 | EFIAPI\r | |
93d451c6 | 108 | PrePeiCoreTemporaryRamSupport (\r |
1d5d0ae9 | 109 | IN CONST EFI_PEI_SERVICES **PeiServices,\r |
110 | IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,\r | |
111 | IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,\r | |
112 | IN UINTN CopySize\r | |
113 | )\r | |
114 | {\r | |
93d451c6 | 115 | VOID *OldHeap;\r |
116 | VOID *NewHeap;\r | |
117 | VOID *OldStack;\r | |
118 | VOID *NewStack;\r | |
4960d8e0 HG |
119 | UINTN HeapSize;\r |
120 | \r | |
121 | HeapSize = ALIGN_VALUE (CopySize / 2, CPU_STACK_ALIGNMENT);\r | |
93d451c6 | 122 | \r |
123 | OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;\r | |
4960d8e0 | 124 | NewHeap = (VOID*)((UINTN)PermanentMemoryBase + (CopySize - HeapSize));\r |
93d451c6 | 125 | \r |
4960d8e0 | 126 | OldStack = (VOID*)((UINTN)TemporaryMemoryBase + HeapSize);\r |
93d451c6 | 127 | NewStack = (VOID*)(UINTN)PermanentMemoryBase;\r |
128 | \r | |
129 | //\r | |
130 | // Migrate the temporary memory stack to permanent memory stack.\r | |
1d5d0ae9 | 131 | //\r |
4960d8e0 | 132 | CopyMem (NewStack, OldStack, CopySize - HeapSize);\r |
93d451c6 | 133 | \r |
134 | //\r | |
135 | // Migrate the temporary memory heap to permanent memory heap.\r | |
f598bf12 | 136 | //\r |
4960d8e0 | 137 | CopyMem (NewHeap, OldHeap, HeapSize);\r |
3402aac7 | 138 | \r |
93d451c6 | 139 | SecSwitchStack ((UINTN)NewStack - (UINTN)OldStack);\r |
1d5d0ae9 | 140 | \r |
93d451c6 | 141 | return EFI_SUCCESS;\r |
142 | }\r |