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cd872e40 | 1 | /** @file\r |
2 | *\r | |
a63be426 | 3 | * Copyright (c) 2011-2017, ARM Limited. All rights reserved.\r |
cd872e40 | 4 | *\r |
f4dfad05 | 5 | * SPDX-License-Identifier: BSD-2-Clause-Patent\r |
cd872e40 | 6 | *\r |
7 | **/\r | |
8 | \r | |
9 | #include <PiPei.h>\r | |
10 | \r | |
11 | #include <Library/DebugAgentLib.h>\r | |
12 | #include <Library/PrePiLib.h>\r | |
cd872e40 | 13 | #include <Library/PrintLib.h>\r |
37573927 | 14 | #include <Library/PrePiHobListPointerLib.h>\r |
cd872e40 | 15 | #include <Library/TimerLib.h>\r |
16 | #include <Library/PerformanceLib.h>\r | |
17 | \r | |
18 | #include <Ppi/GuidedSectionExtraction.h>\r | |
0dbbacdf | 19 | #include <Ppi/ArmMpCoreInfo.h>\r |
a63be426 | 20 | #include <Ppi/SecPerformance.h>\r |
cd872e40 | 21 | \r |
22 | #include "PrePi.h"\r | |
cd872e40 | 23 | \r |
91673dfd LD |
24 | #define IS_XIP() (((UINT64)FixedPcdGet64 (PcdFdBaseAddress) > mSystemMemoryEnd) || \\r |
25 | ((FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) < FixedPcdGet64 (PcdSystemMemoryBase)))\r | |
8fc38a3f | 26 | \r |
4aae7419 AB |
27 | UINT64 mSystemMemoryEnd = FixedPcdGet64(PcdSystemMemoryBase) +\r |
28 | FixedPcdGet64(PcdSystemMemorySize) - 1;\r | |
29 | \r | |
0dbbacdf | 30 | EFI_STATUS\r |
31 | GetPlatformPpi (\r | |
32 | IN EFI_GUID *PpiGuid,\r | |
33 | OUT VOID **Ppi\r | |
34 | )\r | |
35 | {\r | |
36 | UINTN PpiListSize;\r | |
37 | UINTN PpiListCount;\r | |
38 | EFI_PEI_PPI_DESCRIPTOR *PpiList;\r | |
39 | UINTN Index;\r | |
40 | \r | |
41 | PpiListSize = 0;\r | |
42 | ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);\r | |
43 | PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);\r | |
44 | for (Index = 0; Index < PpiListCount; Index++, PpiList++) {\r | |
45 | if (CompareGuid (PpiList->Guid, PpiGuid) == TRUE) {\r | |
46 | *Ppi = PpiList->Ppi;\r | |
47 | return EFI_SUCCESS;\r | |
48 | }\r | |
49 | }\r | |
50 | \r | |
51 | return EFI_NOT_FOUND;\r | |
52 | }\r | |
53 | \r | |
cd872e40 | 54 | VOID\r |
55 | PrePiMain (\r | |
56 | IN UINTN UefiMemoryBase,\r | |
c524ffbb | 57 | IN UINTN StacksBase,\r |
cd872e40 | 58 | IN UINT64 StartTimeStamp\r |
59 | )\r | |
60 | {\r | |
37573927 | 61 | EFI_HOB_HANDOFF_INFO_TABLE* HobList;\r |
0dbbacdf | 62 | ARM_MP_CORE_INFO_PPI* ArmMpCoreInfoPpi;\r |
63 | UINTN ArmCoreCount;\r | |
64 | ARM_CORE_INFO* ArmCoreInfoTable;\r | |
cd872e40 | 65 | EFI_STATUS Status;\r |
66 | CHAR8 Buffer[100];\r | |
67 | UINTN CharCount;\r | |
d269095b | 68 | UINTN StacksSize;\r |
a63be426 | 69 | FIRMWARE_SEC_PERFORMANCE Performance;\r |
cd872e40 | 70 | \r |
8fc38a3f | 71 | // If ensure the FD is either part of the System Memory or totally outside of the System Memory (XIP)\r |
3402aac7 | 72 | ASSERT (IS_XIP() ||\r |
91673dfd LD |
73 | ((FixedPcdGet64 (PcdFdBaseAddress) >= FixedPcdGet64 (PcdSystemMemoryBase)) &&\r |
74 | ((UINT64)(FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= (UINT64)mSystemMemoryEnd)));\r | |
8fc38a3f | 75 | \r |
1bc83266 HL |
76 | // Initialize the architecture specific bits\r |
77 | ArchInitialize ();\r | |
cd872e40 | 78 | \r |
79 | // Initialize the Serial Port\r | |
80 | SerialPortInitialize ();\r | |
37363dff | 81 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"UEFI firmware (version %s built at %a on %a)\n\r",\r |
82 | (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);\r | |
cd872e40 | 83 | SerialPortWrite ((UINT8 *) Buffer, CharCount);\r |
84 | \r | |
85 | // Initialize the Debug Agent for Source Level Debugging\r | |
86 | InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);\r | |
87 | SaveAndSetDebugTimerInterrupt (TRUE);\r | |
3402aac7 | 88 | \r |
d269095b | 89 | // Declare the PI/UEFI memory region\r |
37573927 | 90 | HobList = HobConstructor (\r |
cd872e40 | 91 | (VOID*)UefiMemoryBase,\r |
92 | FixedPcdGet32 (PcdSystemMemoryUefiRegionSize),\r | |
93 | (VOID*)UefiMemoryBase,\r | |
d269095b | 94 | (VOID*)StacksBase // The top of the UEFI Memory is reserved for the stacks\r |
95 | );\r | |
37573927 | 96 | PrePeiSetHobList (HobList);\r |
cd872e40 | 97 | \r |
98 | // Initialize MMU and Memory HOBs (Resource Descriptor HOBs)\r | |
99 | Status = MemoryPeim (UefiMemoryBase, FixedPcdGet32 (PcdSystemMemoryUefiRegionSize));\r | |
100 | ASSERT_EFI_ERROR (Status);\r | |
101 | \r | |
d269095b | 102 | // Create the Stacks HOB (reserve the memory for all stacks)\r |
99565b88 | 103 | if (ArmIsMpCore ()) {\r |
81514a8a OM |
104 | StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize) +\r |
105 | ((FixedPcdGet32 (PcdCoreCount) - 1) * FixedPcdGet32 (PcdCPUCoreSecondaryStackSize));\r | |
99565b88 | 106 | } else {\r |
107 | StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize);\r | |
108 | }\r | |
d269095b | 109 | BuildStackHob (StacksBase, StacksSize);\r |
cd872e40 | 110 | \r |
44788bae | 111 | //TODO: Call CpuPei as a library\r |
e0ec9a12 | 112 | BuildCpuHob (ArmGetPhysicalAddressBits (), PcdGet8 (PcdPrePiCpuIoSize));\r |
44788bae | 113 | \r |
0dbbacdf | 114 | if (ArmIsMpCore ()) {\r |
115 | // Only MP Core platform need to produce gArmMpCoreInfoPpiGuid\r | |
116 | Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID**)&ArmMpCoreInfoPpi);\r | |
117 | \r | |
118 | // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)\r | |
119 | ASSERT_EFI_ERROR (Status);\r | |
120 | \r | |
121 | // Build the MP Core Info Table\r | |
122 | ArmCoreCount = 0;\r | |
123 | Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);\r | |
124 | if (!EFI_ERROR(Status) && (ArmCoreCount > 0)) {\r | |
125 | // Build MPCore Info HOB\r | |
126 | BuildGuidDataHob (&gArmMpCoreInfoGuid, ArmCoreInfoTable, sizeof (ARM_CORE_INFO) * ArmCoreCount);\r | |
127 | }\r | |
128 | }\r | |
129 | \r | |
a63be426 AF |
130 | // Store timer value logged at the beginning of firmware image execution\r |
131 | Performance.ResetEnd = GetTimeInNanoSecond (StartTimeStamp);\r | |
132 | \r | |
133 | // Build SEC Performance Data Hob\r | |
134 | BuildGuidDataHob (&gEfiFirmwarePerformanceGuid, &Performance, sizeof (Performance));\r | |
135 | \r | |
cd872e40 | 136 | // Set the Boot Mode\r |
137 | SetBootMode (ArmPlatformGetBootMode ());\r | |
138 | \r | |
139 | // Initialize Platform HOBs (CpuHob and FvHob)\r | |
140 | Status = PlatformPeim ();\r | |
141 | ASSERT_EFI_ERROR (Status);\r | |
142 | \r | |
cd872e40 | 143 | // Now, the HOB List has been initialized, we can register performance information\r |
144 | PERF_START (NULL, "PEI", NULL, StartTimeStamp);\r | |
145 | \r | |
146 | // SEC phase needs to run library constructors by hand.\r | |
6efd58aa | 147 | ProcessLibraryConstructorList ();\r |
cd872e40 | 148 | \r |
cd872e40 | 149 | // Assume the FV that contains the SEC (our code) also contains a compressed FV.\r |
150 | Status = DecompressFirstFv ();\r | |
151 | ASSERT_EFI_ERROR (Status);\r | |
152 | \r | |
153 | // Load the DXE Core and transfer control to it\r | |
154 | Status = LoadDxeCoreFromFv (NULL, 0);\r | |
155 | ASSERT_EFI_ERROR (Status);\r | |
156 | }\r | |
157 | \r | |
158 | VOID\r | |
159 | CEntryPoint (\r | |
0787bc61 | 160 | IN UINTN MpId,\r |
c524ffbb | 161 | IN UINTN UefiMemoryBase,\r |
f2e17a07 | 162 | IN UINTN StacksBase\r |
cd872e40 | 163 | )\r |
164 | {\r | |
165 | UINT64 StartTimeStamp;\r | |
3402aac7 | 166 | \r |
f437141a | 167 | // Initialize the platform specific controllers\r |
168 | ArmPlatformInitialize (MpId);\r | |
169 | \r | |
bebda7ce | 170 | if (ArmPlatformIsPrimaryCore (MpId) && PerformanceMeasurementEnabled ()) {\r |
cd872e40 | 171 | // Initialize the Timer Library to setup the Timer HW controller\r |
172 | TimerConstructor ();\r | |
173 | // We cannot call yet the PerformanceLib because the HOB List has not been initialized\r | |
174 | StartTimeStamp = GetPerformanceCounter ();\r | |
2ee85366 | 175 | } else {\r |
176 | StartTimeStamp = 0;\r | |
cd872e40 | 177 | }\r |
178 | \r | |
6dafb303 OM |
179 | // Data Cache enabled on Primary core when MMU is enabled.\r |
180 | ArmDisableDataCache ();\r | |
181 | // Invalidate Data cache\r | |
182 | ArmInvalidateDataCache ();\r | |
d269095b | 183 | // Invalidate instruction cache\r |
184 | ArmInvalidateInstructionCache ();\r | |
6dafb303 | 185 | // Enable Instruction Caches on all cores.\r |
d269095b | 186 | ArmEnableInstructionCache ();\r |
cd872e40 | 187 | \r |
99565b88 | 188 | // Define the Global Variable region when we are not running in XIP\r |
189 | if (!IS_XIP()) {\r | |
bebda7ce | 190 | if (ArmPlatformIsPrimaryCore (MpId)) {\r |
1aa9860e | 191 | if (ArmIsMpCore()) {\r |
b1d41be7 | 192 | // Signal the Global Variable Region is defined (event: ARM_CPU_EVENT_DEFAULT)\r |
193 | ArmCallSEV ();\r | |
1aa9860e | 194 | }\r |
99565b88 | 195 | } else {\r |
16f3544d | 196 | // Wait the Primary core has defined the address of the Global Variable region (event: ARM_CPU_EVENT_DEFAULT)\r |
b1d41be7 | 197 | ArmCallWFE ();\r |
99565b88 | 198 | }\r |
199 | }\r | |
3402aac7 | 200 | \r |
d269095b | 201 | // If not primary Jump to Secondary Main\r |
bebda7ce | 202 | if (ArmPlatformIsPrimaryCore (MpId)) {\r |
cd872e40 | 203 | // Goto primary Main.\r |
f2e17a07 | 204 | PrimaryMain (UefiMemoryBase, StacksBase, StartTimeStamp);\r |
cd872e40 | 205 | } else {\r |
0787bc61 | 206 | SecondaryMain (MpId);\r |
cd872e40 | 207 | }\r |
208 | \r | |
209 | // DXE Core should always load and never return\r | |
210 | ASSERT (FALSE);\r | |
211 | }\r | |
212 | \r |