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1d5d0ae9 | 1 | //\r |
8cc852f7 | 2 | // Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r |
1d5d0ae9 | 3 | // \r |
4 | // This program and the accompanying materials \r | |
5 | // are licensed and made available under the terms and conditions of the BSD License \r | |
6 | // which accompanies this distribution. The full text of the license may be found at \r | |
7 | // http://opensource.org/licenses/bsd-license.php \r | |
8 | //\r | |
9 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
10 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
11 | //\r | |
12 | //\r | |
13 | \r | |
1d5d0ae9 | 14 | EXPORT return_from_exception\r |
15 | EXPORT enter_monitor_mode\r | |
16 | EXPORT copy_cpsr_into_spsr\r | |
513aa349 | 17 | EXPORT set_non_secure_mode\r |
1d5d0ae9 | 18 | \r |
19 | AREA Helper, CODE, READONLY\r | |
20 | \r | |
a8530889 | 21 | // r0: Monitor World EntryPoint\r |
22 | // r1: MpId\r | |
23 | // r2: Secure Monitor mode stack\r | |
1d5d0ae9 | 24 | enter_monitor_mode\r |
a8530889 | 25 | mrs r4, cpsr // Save current mode (SVC) in r1\r |
26 | bic r3, r4, #0x1f // Clear all mode bits\r | |
1d5d0ae9 | 27 | orr r3, r3, #0x16 // Set bits for Monitor mode\r |
28 | msr cpsr_cxsf, r3 // We are now in Monitor Mode\r | |
29 | \r | |
a8530889 | 30 | cmp r2, #0 // If a Secure Monitor stack base has been passed, used it\r |
31 | movne sp, r2 // Use the passed sp\r | |
32 | \r | |
33 | mov lr, r0 // Use the pass entrypoint as lr\r | |
1d5d0ae9 | 34 | \r |
a8530889 | 35 | msr spsr_cxsf, r4 // Use saved mode for the MOVS jump to the kernel\r |
36 | \r | |
37 | mov r4, r0 // Swap EntryPoint and MpId registers\r | |
38 | mov r0, r1\r | |
39 | \r | |
40 | bx r4\r | |
1d5d0ae9 | 41 | \r |
42 | // We cannot use the instruction 'movs pc, lr' because the caller can be written either in ARM or Thumb2 assembler.\r | |
43 | // When we will jump into this function, we will set the CPSR flag to ARM assembler. By copying directly 'lr' into\r | |
44 | // 'pc'; we will not change the CPSR flag and it will crash.\r | |
45 | // The way to fix this limitation is to do the movs into the ARM assmbler code and then do a 'bx'.\r | |
46 | return_from_exception\r | |
47 | adr lr, returned_exception\r | |
48 | movs pc, lr\r | |
49 | returned_exception // We are now in non-secure state\r | |
50 | bx r0\r | |
51 | \r | |
52 | // Save the current Program Status Register (PSR) into the Saved PSR\r | |
53 | copy_cpsr_into_spsr\r | |
54 | mrs r0, cpsr\r | |
55 | msr spsr_cxsf, r0\r | |
56 | bx lr\r | |
57 | \r | |
513aa349 | 58 | // Set the Non Secure Mode\r |
59 | set_non_secure_mode\r | |
60 | push { r1 }\r | |
c20d62b5 | 61 | and r0, r0, #0x1f // Keep only the mode bits\r |
513aa349 | 62 | mrs r1, spsr // Read the spsr\r |
63 | bic r1, r1, #0x1f // Clear all mode bits\r | |
64 | orr r1, r1, r0\r | |
65 | msr spsr_cxsf, r1 // write back spsr (may have caused a mode switch)\r | |
66 | isb\r | |
67 | pop { r1 }\r | |
68 | bx lr // return (hopefully thumb-safe!)\r | |
69 | \r | |
1d5d0ae9 | 70 | dead\r |
71 | B dead\r | |
72 | \r | |
73 | END\r |