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1fde2f61 | 1 | /** @file\r |
2 | \r | |
cf748a1a | 3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r |
1fde2f61 | 4 | \r |
cf748a1a | 5 | This program and the accompanying materials\r |
1fde2f61 | 6 | are licensed and made available under the terms and conditions of the BSD License\r |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #include <PiPei.h>\r | |
16 | \r | |
17 | #include <Library/ArmLib.h>\r | |
18 | #include <Library/PrePiLib.h>\r | |
19 | #include <Library/PcdLib.h>\r | |
20 | \r | |
21 | // DDR attributes\r | |
22 | #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r | |
23 | #define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r | |
24 | \r | |
25 | // SoC registers. L3 interconnects\r | |
26 | #define SOC_REGISTERS_L3_PHYSICAL_BASE 0x68000000\r | |
27 | #define SOC_REGISTERS_L3_PHYSICAL_LENGTH 0x08000000\r | |
28 | #define SOC_REGISTERS_L3_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE\r | |
29 | \r | |
30 | // SoC registers. L4 interconnects\r | |
31 | #define SOC_REGISTERS_L4_PHYSICAL_BASE 0x48000000\r | |
32 | #define SOC_REGISTERS_L4_PHYSICAL_LENGTH 0x08000000\r | |
33 | #define SOC_REGISTERS_L4_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE\r | |
34 | \r | |
35 | VOID\r | |
36 | InitCache (\r | |
37 | IN UINT32 MemoryBase,\r | |
38 | IN UINT32 MemoryLength\r | |
39 | )\r | |
40 | {\r | |
41 | UINT32 CacheAttributes;\r | |
42 | ARM_MEMORY_REGION_DESCRIPTOR MemoryTable[5];\r | |
43 | VOID *TranslationTableBase;\r | |
44 | UINTN TranslationTableSize;\r | |
45 | \r | |
46 | if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r | |
47 | CacheAttributes = DDR_ATTRIBUTES_CACHED;\r | |
48 | } else {\r | |
49 | CacheAttributes = DDR_ATTRIBUTES_UNCACHED;\r | |
50 | }\r | |
51 | \r | |
52 | // DDR\r | |
53 | MemoryTable[0].PhysicalBase = MemoryBase;\r | |
54 | MemoryTable[0].VirtualBase = MemoryBase;\r | |
55 | MemoryTable[0].Length = MemoryLength;\r | |
56 | MemoryTable[0].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r | |
57 | \r | |
58 | // SOC Registers. L3 interconnects\r | |
59 | MemoryTable[1].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE;\r | |
60 | MemoryTable[1].VirtualBase = SOC_REGISTERS_L3_PHYSICAL_BASE;\r | |
61 | MemoryTable[1].Length = SOC_REGISTERS_L3_PHYSICAL_LENGTH;\r | |
62 | MemoryTable[1].Attributes = SOC_REGISTERS_L3_ATTRIBUTES;\r | |
63 | \r | |
64 | // SOC Registers. L4 interconnects\r | |
65 | MemoryTable[2].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE;\r | |
66 | MemoryTable[2].VirtualBase = SOC_REGISTERS_L4_PHYSICAL_BASE;\r | |
67 | MemoryTable[2].Length = SOC_REGISTERS_L4_PHYSICAL_LENGTH;\r | |
68 | MemoryTable[2].Attributes = SOC_REGISTERS_L4_ATTRIBUTES;\r | |
69 | \r | |
70 | // End of Table\r | |
71 | MemoryTable[3].PhysicalBase = 0;\r | |
72 | MemoryTable[3].VirtualBase = 0;\r | |
73 | MemoryTable[3].Length = 0;\r | |
74 | MemoryTable[3].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r | |
75 | \r | |
76 | ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);\r | |
77 | \r | |
78 | BuildMemoryAllocationHob ((EFI_PHYSICAL_ADDRESS)(UINTN)TranslationTableBase, TranslationTableSize, EfiBootServicesData);\r | |
79 | }\r |