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1 | Device Tree Clock bindings for arch-at91 |
2 | ||
3 | This binding uses the common clock binding[1]. | |
4 | ||
5 | [1] Documentation/devicetree/bindings/clock/clock-bindings.txt | |
6 | ||
7 | Required properties: | |
8 | - compatible : shall be one of the following: | |
4b13b645 AB |
9 | "atmel,at91sam9x5-sckc" or |
10 | "atmel,sama5d4-sckc": | |
4d735e54 BB |
11 | at91 SCKC (Slow Clock Controller) |
12 | This node contains the slow clock definitions. | |
13 | ||
14 | "atmel,at91sam9x5-clk-slow-osc": | |
15 | at91 slow oscillator | |
16 | ||
17 | "atmel,at91sam9x5-clk-slow-rc-osc": | |
18 | at91 internal slow RC oscillator | |
19 | ||
32f955c6 BB |
20 | "atmel,at91rm9200-pmc" or |
21 | "atmel,at91sam9g45-pmc" or | |
22 | "atmel,at91sam9n12-pmc" or | |
23 | "atmel,at91sam9x5-pmc" or | |
24 | "atmel,sama5d3-pmc": | |
25 | at91 PMC (Power Management Controller) | |
26 | All at91 specific clocks (clocks defined below) must be child | |
27 | node of the PMC node. | |
28 | ||
4d735e54 BB |
29 | "atmel,at91sam9x5-clk-slow" (under sckc node) |
30 | or | |
31 | "atmel,at91sam9260-clk-slow" (under pmc node): | |
32 | at91 slow clk | |
33 | ||
f9e1716f BB |
34 | "atmel,at91rm9200-clk-main-osc" |
35 | "atmel,at91sam9x5-clk-main-rc-osc" | |
36 | at91 main clk sources | |
37 | ||
38 | "atmel,at91sam9x5-clk-main" | |
32f955c6 | 39 | "atmel,at91rm9200-clk-main": |
f9e1716f | 40 | at91 main clock |
32f955c6 BB |
41 | |
42 | "atmel,at91rm9200-clk-master" or | |
43 | "atmel,at91sam9x5-clk-master": | |
44 | at91 master clock | |
45 | ||
46 | "atmel,at91sam9x5-clk-peripheral" or | |
47 | "atmel,at91rm9200-clk-peripheral": | |
48 | at91 peripheral clocks | |
49 | ||
50 | "atmel,at91rm9200-clk-pll" or | |
51 | "atmel,at91sam9g45-clk-pll" or | |
52 | "atmel,at91sam9g20-clk-pllb" or | |
53 | "atmel,sama5d3-clk-pll": | |
54 | at91 pll clocks | |
55 | ||
56 | "atmel,at91sam9x5-clk-plldiv": | |
57 | at91 plla divisor | |
58 | ||
59 | "atmel,at91rm9200-clk-programmable" or | |
60 | "atmel,at91sam9g45-clk-programmable" or | |
61 | "atmel,at91sam9x5-clk-programmable": | |
62 | at91 programmable clocks | |
63 | ||
64 | "atmel,at91sam9x5-clk-smd": | |
65 | at91 SMD (Soft Modem) clock | |
66 | ||
67 | "atmel,at91rm9200-clk-system": | |
68 | at91 system clocks | |
69 | ||
70 | "atmel,at91rm9200-clk-usb" or | |
71 | "atmel,at91sam9x5-clk-usb" or | |
72 | "atmel,at91sam9n12-clk-usb": | |
73 | at91 usb clock | |
74 | ||
75 | "atmel,at91sam9x5-clk-utmi": | |
76 | at91 utmi clock | |
77 | ||
bcc5fd49 AB |
78 | "atmel,sama5d4-clk-h32mx": |
79 | at91 h32mx clock | |
80 | ||
df70aeef NF |
81 | "atmel,sama5d2-clk-generated": |
82 | at91 generated clock | |
83 | ||
4d735e54 BB |
84 | Required properties for SCKC node: |
85 | - reg : defines the IO memory reserved for the SCKC. | |
86 | - #size-cells : shall be 0 (reg is used to encode clk id). | |
87 | - #address-cells : shall be 1 (reg is used to encode clk id). | |
88 | ||
89 | ||
90 | For example: | |
91 | sckc: sckc@fffffe50 { | |
92 | compatible = "atmel,sama5d3-pmc"; | |
93 | reg = <0xfffffe50 0x4> | |
94 | #size-cells = <0>; | |
95 | #address-cells = <1>; | |
96 | ||
97 | /* put at91 slow clocks here */ | |
98 | }; | |
99 | ||
100 | ||
101 | Required properties for internal slow RC oscillator: | |
102 | - #clock-cells : from common clock binding; shall be set to 0. | |
103 | - clock-frequency : define the internal RC oscillator frequency. | |
104 | ||
105 | Optional properties: | |
106 | - clock-accuracy : define the internal RC oscillator accuracy. | |
107 | ||
108 | For example: | |
109 | slow_rc_osc: slow_rc_osc { | |
110 | compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; | |
111 | clock-frequency = <32768>; | |
112 | clock-accuracy = <50000000>; | |
113 | }; | |
114 | ||
115 | Required properties for slow oscillator: | |
116 | - #clock-cells : from common clock binding; shall be set to 0. | |
117 | - clocks : shall encode the main osc source clk sources (see atmel datasheet). | |
118 | ||
119 | Optional properties: | |
120 | - atmel,osc-bypass : boolean property. Set this when a clock signal is directly | |
121 | provided on XIN. | |
122 | ||
123 | For example: | |
124 | slow_osc: slow_osc { | |
125 | compatible = "atmel,at91rm9200-clk-slow-osc"; | |
126 | #clock-cells = <0>; | |
127 | clocks = <&slow_xtal>; | |
128 | }; | |
129 | ||
130 | Required properties for slow clock: | |
131 | - #clock-cells : from common clock binding; shall be set to 0. | |
132 | - clocks : shall encode the slow clk sources (see atmel datasheet). | |
133 | ||
134 | For example: | |
135 | clk32k: slck { | |
136 | compatible = "atmel,at91sam9x5-clk-slow"; | |
137 | #clock-cells = <0>; | |
138 | clocks = <&slow_rc_osc &slow_osc>; | |
139 | }; | |
140 | ||
32f955c6 BB |
141 | Required properties for PMC node: |
142 | - reg : defines the IO memory reserved for the PMC. | |
143 | - #size-cells : shall be 0 (reg is used to encode clk id). | |
144 | - #address-cells : shall be 1 (reg is used to encode clk id). | |
145 | - interrupts : shall be set to PMC interrupt line. | |
146 | - interrupt-controller : tell that the PMC is an interrupt controller. | |
147 | - #interrupt-cells : must be set to 1. The first cell encodes the interrupt id, | |
148 | and reflect the bit position in the PMC_ER/DR/SR registers. | |
35d35aae | 149 | You can use the dt macros defined in dt-bindings/clock/at91.h. |
32f955c6 BB |
150 | 0 (AT91_PMC_MOSCS) -> main oscillator ready |
151 | 1 (AT91_PMC_LOCKA) -> PLL A ready | |
152 | 2 (AT91_PMC_LOCKB) -> PLL B ready | |
153 | 3 (AT91_PMC_MCKRDY) -> master clock ready | |
154 | 6 (AT91_PMC_LOCKU) -> UTMI PLL clock ready | |
155 | 8 .. 15 (AT91_PMC_PCKRDY(id)) -> programmable clock ready | |
156 | 16 (AT91_PMC_MOSCSELS) -> main oscillator selected | |
157 | 17 (AT91_PMC_MOSCRCS) -> RC main oscillator stabilized | |
158 | 18 (AT91_PMC_CFDEV) -> clock failure detected | |
159 | ||
160 | For example: | |
161 | pmc: pmc@fffffc00 { | |
162 | compatible = "atmel,sama5d3-pmc"; | |
163 | interrupts = <1 4 7>; | |
164 | interrupt-controller; | |
165 | #interrupt-cells = <2>; | |
166 | #size-cells = <0>; | |
167 | #address-cells = <1>; | |
168 | ||
169 | /* put at91 clocks here */ | |
170 | }; | |
171 | ||
f9e1716f BB |
172 | Required properties for main clock internal RC oscillator: |
173 | - interrupt-parent : must reference the PMC node. | |
174 | - interrupts : shall be set to "<0>". | |
175 | - clock-frequency : define the internal RC oscillator frequency. | |
176 | ||
177 | Optional properties: | |
178 | - clock-accuracy : define the internal RC oscillator accuracy. | |
179 | ||
180 | For example: | |
181 | main_rc_osc: main_rc_osc { | |
182 | compatible = "atmel,at91sam9x5-clk-main-rc-osc"; | |
183 | interrupt-parent = <&pmc>; | |
184 | interrupts = <0>; | |
185 | clock-frequency = <12000000>; | |
186 | clock-accuracy = <50000000>; | |
187 | }; | |
188 | ||
189 | Required properties for main clock oscillator: | |
190 | - interrupt-parent : must reference the PMC node. | |
191 | - interrupts : shall be set to "<0>". | |
192 | - #clock-cells : from common clock binding; shall be set to 0. | |
193 | - clocks : shall encode the main osc source clk sources (see atmel datasheet). | |
194 | ||
195 | Optional properties: | |
196 | - atmel,osc-bypass : boolean property. Specified if a clock signal is provided | |
197 | on XIN. | |
198 | ||
199 | clock signal is directly provided on XIN pin. | |
200 | ||
201 | For example: | |
202 | main_osc: main_osc { | |
203 | compatible = "atmel,at91rm9200-clk-main-osc"; | |
204 | interrupt-parent = <&pmc>; | |
205 | interrupts = <0>; | |
206 | #clock-cells = <0>; | |
207 | clocks = <&main_xtal>; | |
208 | }; | |
209 | ||
32f955c6 BB |
210 | Required properties for main clock: |
211 | - interrupt-parent : must reference the PMC node. | |
212 | - interrupts : shall be set to "<0>". | |
213 | - #clock-cells : from common clock binding; shall be set to 0. | |
f9e1716f | 214 | - clocks : shall encode the main clk sources (see atmel datasheet). |
32f955c6 BB |
215 | |
216 | For example: | |
217 | main: mainck { | |
f9e1716f | 218 | compatible = "atmel,at91sam9x5-clk-main"; |
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219 | interrupt-parent = <&pmc>; |
220 | interrupts = <0>; | |
221 | #clock-cells = <0>; | |
f9e1716f | 222 | clocks = <&main_rc_osc &main_osc>; |
32f955c6 BB |
223 | }; |
224 | ||
225 | Required properties for master clock: | |
226 | - interrupt-parent : must reference the PMC node. | |
227 | - interrupts : shall be set to "<3>". | |
228 | - #clock-cells : from common clock binding; shall be set to 0. | |
229 | - clocks : shall be the master clock sources (see atmel datasheet) phandles. | |
230 | e.g. "<&ck32k>, <&main>, <&plla>, <&pllb>". | |
231 | - atmel,clk-output-range : minimum and maximum clock frequency (two u32 | |
232 | fields). | |
233 | e.g. output = <0 133000000>; <=> 0 to 133MHz. | |
234 | - atmel,clk-divisors : master clock divisors table (four u32 fields). | |
235 | 0 <=> reserved value. | |
236 | e.g. divisors = <1 2 4 6>; | |
237 | - atmel,master-clk-have-div3-pres : some SoC use the reserved value 7 in the | |
238 | PRES field as CLOCK_DIV3 (e.g sam9x5). | |
239 | ||
240 | For example: | |
241 | mck: mck { | |
242 | compatible = "atmel,at91rm9200-clk-master"; | |
243 | interrupt-parent = <&pmc>; | |
244 | interrupts = <3>; | |
245 | #clock-cells = <0>; | |
246 | atmel,clk-output-range = <0 133000000>; | |
247 | atmel,clk-divisors = <1 2 4 0>; | |
248 | }; | |
249 | ||
250 | Required properties for peripheral clocks: | |
251 | - #size-cells : shall be 0 (reg is used to encode clk id). | |
252 | - #address-cells : shall be 1 (reg is used to encode clk id). | |
253 | - clocks : shall be the master clock phandle. | |
254 | e.g. clocks = <&mck>; | |
c49bb94c | 255 | - name: device tree node describing a specific peripheral clock. |
32f955c6 BB |
256 | * #clock-cells : from common clock binding; shall be set to 0. |
257 | * reg: peripheral id. See Atmel's datasheets to get a full | |
258 | list of peripheral ids. | |
259 | * atmel,clk-output-range : minimum and maximum clock frequency | |
260 | (two u32 fields). Only valid on at91sam9x5-clk-peripheral | |
261 | compatible IPs. | |
262 | ||
263 | For example: | |
264 | periph: periphck { | |
265 | compatible = "atmel,at91sam9x5-clk-peripheral"; | |
266 | #size-cells = <0>; | |
267 | #address-cells = <1>; | |
268 | clocks = <&mck>; | |
269 | ||
270 | ssc0_clk { | |
271 | #clock-cells = <0>; | |
272 | reg = <2>; | |
273 | atmel,clk-output-range = <0 133000000>; | |
274 | }; | |
275 | ||
276 | usart0_clk { | |
277 | #clock-cells = <0>; | |
278 | reg = <3>; | |
279 | atmel,clk-output-range = <0 66000000>; | |
280 | }; | |
281 | }; | |
282 | ||
283 | ||
284 | Required properties for pll clocks: | |
285 | - interrupt-parent : must reference the PMC node. | |
286 | - interrupts : shall be set to "<1>". | |
287 | - #clock-cells : from common clock binding; shall be set to 0. | |
288 | - clocks : shall be the main clock phandle. | |
289 | - reg : pll id. | |
290 | 0 -> PLL A | |
291 | 1 -> PLL B | |
292 | - atmel,clk-input-range : minimum and maximum source clock frequency (two u32 | |
293 | fields). | |
294 | e.g. input = <1 32000000>; <=> 1 to 32MHz. | |
295 | - #atmel,pll-clk-output-range-cells : number of cells reserved for pll output | |
296 | range description. Sould be set to 2, 3 | |
297 | or 4. | |
298 | * 1st and 2nd cells represent the frequency range (min-max). | |
299 | * 3rd cell is optional and represents the OUT field value for the given | |
300 | range. | |
301 | * 4th cell is optional and represents the ICPLL field (PLLICPR | |
302 | register) | |
303 | - atmel,pll-clk-output-ranges : pll output frequency ranges + optional parameter | |
304 | depending on #atmel,pll-output-range-cells | |
305 | property value. | |
306 | ||
307 | For example: | |
308 | plla: pllack { | |
309 | compatible = "atmel,at91sam9g45-clk-pll"; | |
310 | interrupt-parent = <&pmc>; | |
311 | interrupts = <1>; | |
312 | #clock-cells = <0>; | |
313 | clocks = <&main>; | |
314 | reg = <0>; | |
315 | atmel,clk-input-range = <2000000 32000000>; | |
316 | #atmel,pll-clk-output-range-cells = <4>; | |
317 | atmel,pll-clk-output-ranges = <74500000 800000000 0 0 | |
318 | 69500000 750000000 1 0 | |
319 | 64500000 700000000 2 0 | |
320 | 59500000 650000000 3 0 | |
321 | 54500000 600000000 0 1 | |
322 | 49500000 550000000 1 1 | |
323 | 44500000 500000000 2 1 | |
324 | 40000000 450000000 3 1>; | |
325 | }; | |
326 | ||
327 | Required properties for plldiv clocks (plldiv = pll / 2): | |
328 | - #clock-cells : from common clock binding; shall be set to 0. | |
329 | - clocks : shall be the plla clock phandle. | |
330 | ||
331 | The pll divisor is equal to 2 and cannot be changed. | |
332 | ||
333 | For example: | |
334 | plladiv: plladivck { | |
335 | compatible = "atmel,at91sam9x5-clk-plldiv"; | |
336 | #clock-cells = <0>; | |
337 | clocks = <&plla>; | |
338 | }; | |
339 | ||
340 | Required properties for programmable clocks: | |
341 | - interrupt-parent : must reference the PMC node. | |
342 | - #size-cells : shall be 0 (reg is used to encode clk id). | |
343 | - #address-cells : shall be 1 (reg is used to encode clk id). | |
344 | - clocks : shall be the programmable clock source phandles. | |
345 | e.g. clocks = <&clk32k>, <&main>, <&plla>, <&pllb>; | |
346 | - name: device tree node describing a specific prog clock. | |
347 | * #clock-cells : from common clock binding; shall be set to 0. | |
348 | * reg : programmable clock id (register offset from PCKx | |
349 | register). | |
350 | * interrupts : shall be set to "<(8 + id)>". | |
351 | ||
352 | For example: | |
353 | prog: progck { | |
354 | compatible = "atmel,at91sam9g45-clk-programmable"; | |
355 | #size-cells = <0>; | |
356 | #address-cells = <1>; | |
357 | interrupt-parent = <&pmc>; | |
358 | clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; | |
359 | ||
360 | prog0 { | |
361 | #clock-cells = <0>; | |
362 | reg = <0>; | |
363 | interrupts = <8>; | |
364 | }; | |
365 | ||
366 | prog1 { | |
367 | #clock-cells = <0>; | |
368 | reg = <1>; | |
369 | interrupts = <9>; | |
370 | }; | |
371 | }; | |
372 | ||
373 | ||
374 | Required properties for smd clock: | |
375 | - #clock-cells : from common clock binding; shall be set to 0. | |
376 | - clocks : shall be the smd clock source phandles. | |
377 | e.g. clocks = <&plladiv>, <&utmi>; | |
378 | ||
379 | For example: | |
380 | smd: smdck { | |
381 | compatible = "atmel,at91sam9x5-clk-smd"; | |
382 | #clock-cells = <0>; | |
383 | clocks = <&plladiv>, <&utmi>; | |
384 | }; | |
385 | ||
386 | Required properties for system clocks: | |
387 | - #size-cells : shall be 0 (reg is used to encode clk id). | |
388 | - #address-cells : shall be 1 (reg is used to encode clk id). | |
389 | - name: device tree node describing a specific system clock. | |
390 | * #clock-cells : from common clock binding; shall be set to 0. | |
391 | * reg: system clock id (bit position in SCER/SCDR/SCSR registers). | |
392 | See Atmel's datasheet to get a full list of system clock ids. | |
393 | ||
394 | For example: | |
395 | system: systemck { | |
396 | compatible = "atmel,at91rm9200-clk-system"; | |
397 | #address-cells = <1>; | |
398 | #size-cells = <0>; | |
399 | ||
400 | ddrck { | |
401 | #clock-cells = <0>; | |
402 | reg = <2>; | |
403 | clocks = <&mck>; | |
404 | }; | |
405 | ||
406 | uhpck { | |
407 | #clock-cells = <0>; | |
408 | reg = <6>; | |
409 | clocks = <&usb>; | |
410 | }; | |
411 | ||
412 | udpck { | |
413 | #clock-cells = <0>; | |
414 | reg = <7>; | |
415 | clocks = <&usb>; | |
416 | }; | |
417 | }; | |
418 | ||
419 | ||
420 | Required properties for usb clock: | |
421 | - #clock-cells : from common clock binding; shall be set to 0. | |
422 | - clocks : shall be the smd clock source phandles. | |
423 | e.g. clocks = <&pllb>; | |
424 | - atmel,clk-divisors (only available for "atmel,at91rm9200-clk-usb"): | |
425 | usb clock divisor table. | |
426 | e.g. divisors = <1 2 4 0>; | |
427 | ||
428 | For example: | |
429 | usb: usbck { | |
430 | compatible = "atmel,at91sam9x5-clk-usb"; | |
431 | #clock-cells = <0>; | |
432 | clocks = <&plladiv>, <&utmi>; | |
433 | }; | |
434 | ||
435 | usb: usbck { | |
436 | compatible = "atmel,at91rm9200-clk-usb"; | |
437 | #clock-cells = <0>; | |
438 | clocks = <&pllb>; | |
439 | atmel,clk-divisors = <1 2 4 0>; | |
440 | }; | |
441 | ||
442 | ||
443 | Required properties for utmi clock: | |
444 | - interrupt-parent : must reference the PMC node. | |
445 | - interrupts : shall be set to "<AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>". | |
446 | - #clock-cells : from common clock binding; shall be set to 0. | |
447 | - clocks : shall be the main clock source phandle. | |
448 | ||
449 | For example: | |
450 | utmi: utmick { | |
451 | compatible = "atmel,at91sam9x5-clk-utmi"; | |
452 | interrupt-parent = <&pmc>; | |
453 | interrupts = <AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>; | |
454 | #clock-cells = <0>; | |
455 | clocks = <&main>; | |
456 | }; | |
bcc5fd49 AB |
457 | |
458 | Required properties for 32 bits bus Matrix clock (h32mx clock): | |
459 | - #clock-cells : from common clock binding; shall be set to 0. | |
460 | - clocks : shall be the master clock source phandle. | |
461 | ||
462 | For example: | |
463 | h32ck: h32mxck { | |
464 | #clock-cells = <0>; | |
465 | compatible = "atmel,sama5d4-clk-h32mx"; | |
466 | clocks = <&mck>; | |
467 | }; | |
df70aeef NF |
468 | |
469 | Required properties for generated clocks: | |
470 | - #size-cells : shall be 0 (reg is used to encode clk id). | |
471 | - #address-cells : shall be 1 (reg is used to encode clk id). | |
472 | - clocks : shall be the generated clock source phandles. | |
473 | e.g. clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>; | |
474 | - name: device tree node describing a specific generated clock. | |
475 | * #clock-cells : from common clock binding; shall be set to 0. | |
476 | * reg: peripheral id. See Atmel's datasheets to get a full | |
477 | list of peripheral ids. | |
478 | * atmel,clk-output-range : minimum and maximum clock frequency | |
479 | (two u32 fields). | |
480 | ||
481 | For example: | |
482 | gck { | |
483 | compatible = "atmel,sama5d2-clk-generated"; | |
484 | #address-cells = <1>; | |
485 | #size-cells = <0>; | |
486 | clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>; | |
487 | ||
488 | tcb0_gclk: tcb0_gclk { | |
489 | #clock-cells = <0>; | |
490 | reg = <35>; | |
491 | atmel,clk-output-range = <0 83000000>; | |
492 | }; | |
493 | ||
494 | pwm_gclk: pwm_gclk { | |
495 | #clock-cells = <0>; | |
496 | reg = <38>; | |
497 | atmel,clk-output-range = <0 83000000>; | |
498 | }; | |
499 | }; |