]>
Commit | Line | Data |
---|---|---|
7b5bb891 YS |
1 | * Renesas H8/300 divider clock |
2 | ||
3 | Required Properties: | |
4 | ||
c4eb32b1 | 5 | - compatible: Must be "renesas,h8300-div-clock" |
7b5bb891 YS |
6 | |
7 | - clocks: Reference to the parent clocks ("extal1" and "extal2") | |
8 | ||
9 | - #clock-cells: Must be 1 | |
10 | ||
11 | - reg: Base address and length of the divide rate selector | |
12 | ||
13 | - renesas,width: bit width of selector | |
14 | ||
15 | Example | |
16 | ------- | |
17 | ||
18 | cclk: cclk { | |
19 | compatible = "renesas,h8300-div-clock"; | |
20 | clocks = <&xclk>; | |
21 | #clock-cells = <0>; | |
22 | reg = <0xfee01b 2>; | |
23 | renesas,width = <2>; | |
24 | }; |