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Commit | Line | Data |
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9abd5f05 SH |
1 | Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator. |
2 | ||
3 | Reference | |
4 | [1] Si5351A/B/C Data Sheet | |
5 | http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf | |
6 | ||
f884ab15 | 7 | The Si5351a/b/c are programmable i2c clock generators with up to 8 output |
9abd5f05 SH |
8 | clocks. Si5351a also has a reduced pin-count package (MSOP10) where only |
9 | 3 output clocks are accessible. The internal structure of the clock | |
10 | generators can be found in [1]. | |
11 | ||
12 | ==I2C device node== | |
13 | ||
14 | Required properties: | |
15 | - compatible: shall be one of "silabs,si5351{a,a-msop,b,c}". | |
16 | - reg: i2c device address, shall be 0x60 or 0x61. | |
17 | - #clock-cells: from common clock binding; shall be set to 1. | |
18 | - clocks: from common clock binding; list of parent clock | |
19 | handles, shall be xtal reference clock or xtal and clkin for | |
f94029d8 SH |
20 | si5351c only. Corresponding clock input names are "xtal" and |
21 | "clkin" respectively. | |
9abd5f05 SH |
22 | - #address-cells: shall be set to 1. |
23 | - #size-cells: shall be set to 0. | |
24 | ||
25 | Optional properties: | |
26 | - silabs,pll-source: pair of (number, source) for each pll. Allows | |
27 | to overwrite clock source of pll A (number=0) or B (number=1). | |
28 | ||
29 | ==Child nodes== | |
30 | ||
31 | Each of the clock outputs can be overwritten individually by | |
32 | using a child node to the I2C device node. If a child node for a clock | |
33 | output is not set, the eeprom configuration is not overwritten. | |
34 | ||
35 | Required child node properties: | |
36 | - reg: number of clock output. | |
37 | ||
38 | Optional child node properties: | |
39 | - silabs,clock-source: source clock of the output divider stage N, shall be | |
40 | 0 = multisynth N | |
41 | 1 = multisynth 0 for output clocks 0-3, else multisynth4 | |
42 | 2 = xtal | |
43 | 3 = clkin (si5351c only) | |
44 | - silabs,drive-strength: output drive strength in mA, shall be one of {2,4,6,8}. | |
45 | - silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth | |
46 | divider. | |
47 | - silabs,pll-master: boolean, multisynth can change pll frequency. | |
1a0483d2 SH |
48 | - silabs,disable-state : clock output disable state, shall be |
49 | 0 = clock output is driven LOW when disabled | |
50 | 1 = clock output is driven HIGH when disabled | |
51 | 2 = clock output is FLOATING (HIGH-Z) when disabled | |
52 | 3 = clock output is NEVER disabled | |
9abd5f05 SH |
53 | |
54 | ==Example== | |
55 | ||
56 | /* 25MHz reference crystal */ | |
57 | ref25: ref25M { | |
58 | compatible = "fixed-clock"; | |
59 | #clock-cells = <0>; | |
60 | clock-frequency = <25000000>; | |
61 | }; | |
62 | ||
63 | i2c-master-node { | |
64 | ||
65 | /* Si5351a msop10 i2c clock generator */ | |
66 | si5351a: clock-generator@60 { | |
67 | compatible = "silabs,si5351a-msop"; | |
68 | reg = <0x60>; | |
69 | #address-cells = <1>; | |
70 | #size-cells = <0>; | |
71 | #clock-cells = <1>; | |
72 | ||
73 | /* connect xtal input to 25MHz reference */ | |
74 | clocks = <&ref25>; | |
f94029d8 | 75 | clock-names = "xtal"; |
9abd5f05 SH |
76 | |
77 | /* connect xtal input as source of pll0 and pll1 */ | |
78 | silabs,pll-source = <0 0>, <1 0>; | |
79 | ||
80 | /* | |
81 | * overwrite clkout0 configuration with: | |
82 | * - 8mA output drive strength | |
83 | * - pll0 as clock source of multisynth0 | |
84 | * - multisynth0 as clock source of output divider | |
85 | * - multisynth0 can change pll0 | |
86 | * - set initial clock frequency of 74.25MHz | |
87 | */ | |
88 | clkout0 { | |
89 | reg = <0>; | |
90 | silabs,drive-strength = <8>; | |
91 | silabs,multisynth-source = <0>; | |
92 | silabs,clock-source = <0>; | |
93 | silabs,pll-master; | |
94 | clock-frequency = <74250000>; | |
95 | }; | |
96 | ||
97 | /* | |
98 | * overwrite clkout1 configuration with: | |
99 | * - 4mA output drive strength | |
100 | * - pll1 as clock source of multisynth1 | |
101 | * - multisynth1 as clock source of output divider | |
102 | * - multisynth1 can change pll1 | |
103 | */ | |
104 | clkout1 { | |
105 | reg = <1>; | |
106 | silabs,drive-strength = <4>; | |
107 | silabs,multisynth-source = <1>; | |
108 | silabs,clock-source = <0>; | |
109 | pll-master; | |
110 | }; | |
111 | ||
112 | /* | |
113 | * overwrite clkout2 configuration with: | |
114 | * - xtal as clock source of output divider | |
115 | */ | |
116 | clkout2 { | |
117 | reg = <2>; | |
118 | silabs,clock-source = <2>; | |
119 | }; | |
120 | }; | |
121 | }; |