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Commit | Line | Data |
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416912a1 DD |
1 | Properties for an MDIO bus multiplexer/switch controlled by GPIO pins. |
2 | ||
3 | This is a special case of a MDIO bus multiplexer. One or more GPIO | |
4 | lines are used to control which child bus is connected. | |
5 | ||
6 | Required properties in addition to the generic multiplexer properties: | |
7 | ||
8 | - compatible : mdio-mux-gpio. | |
9 | - gpios : GPIO specifiers for each GPIO line. One or more must be specified. | |
10 | ||
11 | ||
12 | Example : | |
13 | ||
14 | /* The parent MDIO bus. */ | |
15 | smi1: mdio@1180000001900 { | |
16 | compatible = "cavium,octeon-3860-mdio"; | |
17 | #address-cells = <1>; | |
18 | #size-cells = <0>; | |
19 | reg = <0x11800 0x00001900 0x0 0x40>; | |
20 | }; | |
21 | ||
22 | /* | |
23 | An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a | |
24 | pair of GPIO lines. Child busses 2 and 3 populated with 4 | |
25 | PHYs each. | |
26 | */ | |
27 | mdio-mux { | |
28 | compatible = "mdio-mux-gpio"; | |
29 | gpios = <&gpio1 3 0>, <&gpio1 4 0>; | |
30 | mdio-parent-bus = <&smi1>; | |
31 | #address-cells = <1>; | |
32 | #size-cells = <0>; | |
33 | ||
34 | mdio@2 { | |
35 | reg = <2>; | |
36 | #address-cells = <1>; | |
37 | #size-cells = <0>; | |
38 | ||
39 | phy11: ethernet-phy@1 { | |
40 | reg = <1>; | |
416912a1 DD |
41 | marvell,reg-init = <3 0x10 0 0x5777>, |
42 | <3 0x11 0 0x00aa>, | |
43 | <3 0x12 0 0x4105>, | |
44 | <3 0x13 0 0x0a60>; | |
45 | interrupt-parent = <&gpio>; | |
46 | interrupts = <10 8>; /* Pin 10, active low */ | |
47 | }; | |
48 | phy12: ethernet-phy@2 { | |
49 | reg = <2>; | |
416912a1 DD |
50 | marvell,reg-init = <3 0x10 0 0x5777>, |
51 | <3 0x11 0 0x00aa>, | |
52 | <3 0x12 0 0x4105>, | |
53 | <3 0x13 0 0x0a60>; | |
54 | interrupt-parent = <&gpio>; | |
55 | interrupts = <10 8>; /* Pin 10, active low */ | |
56 | }; | |
57 | phy13: ethernet-phy@3 { | |
58 | reg = <3>; | |
416912a1 DD |
59 | marvell,reg-init = <3 0x10 0 0x5777>, |
60 | <3 0x11 0 0x00aa>, | |
61 | <3 0x12 0 0x4105>, | |
62 | <3 0x13 0 0x0a60>; | |
63 | interrupt-parent = <&gpio>; | |
64 | interrupts = <10 8>; /* Pin 10, active low */ | |
65 | }; | |
66 | phy14: ethernet-phy@4 { | |
67 | reg = <4>; | |
416912a1 DD |
68 | marvell,reg-init = <3 0x10 0 0x5777>, |
69 | <3 0x11 0 0x00aa>, | |
70 | <3 0x12 0 0x4105>, | |
71 | <3 0x13 0 0x0a60>; | |
72 | interrupt-parent = <&gpio>; | |
73 | interrupts = <10 8>; /* Pin 10, active low */ | |
74 | }; | |
75 | }; | |
76 | ||
77 | mdio@3 { | |
78 | reg = <3>; | |
79 | #address-cells = <1>; | |
80 | #size-cells = <0>; | |
81 | ||
82 | phy21: ethernet-phy@1 { | |
83 | reg = <1>; | |
416912a1 DD |
84 | marvell,reg-init = <3 0x10 0 0x5777>, |
85 | <3 0x11 0 0x00aa>, | |
86 | <3 0x12 0 0x4105>, | |
87 | <3 0x13 0 0x0a60>; | |
88 | interrupt-parent = <&gpio>; | |
89 | interrupts = <12 8>; /* Pin 12, active low */ | |
90 | }; | |
91 | phy22: ethernet-phy@2 { | |
92 | reg = <2>; | |
416912a1 DD |
93 | marvell,reg-init = <3 0x10 0 0x5777>, |
94 | <3 0x11 0 0x00aa>, | |
95 | <3 0x12 0 0x4105>, | |
96 | <3 0x13 0 0x0a60>; | |
97 | interrupt-parent = <&gpio>; | |
98 | interrupts = <12 8>; /* Pin 12, active low */ | |
99 | }; | |
100 | phy23: ethernet-phy@3 { | |
101 | reg = <3>; | |
416912a1 DD |
102 | marvell,reg-init = <3 0x10 0 0x5777>, |
103 | <3 0x11 0 0x00aa>, | |
104 | <3 0x12 0 0x4105>, | |
105 | <3 0x13 0 0x0a60>; | |
106 | interrupt-parent = <&gpio>; | |
107 | interrupts = <12 8>; /* Pin 12, active low */ | |
108 | }; | |
109 | phy24: ethernet-phy@4 { | |
110 | reg = <4>; | |
416912a1 DD |
111 | marvell,reg-init = <3 0x10 0 0x5777>, |
112 | <3 0x11 0 0x00aa>, | |
113 | <3 0x12 0 0x4105>, | |
114 | <3 0x13 0 0x0a60>; | |
115 | interrupt-parent = <&gpio>; | |
116 | interrupts = <12 8>; /* Pin 12, active low */ | |
117 | }; | |
118 | }; | |
119 | }; |