[mirror_ubuntu-artful-kernel.git] / Documentation / devicetree / bindings / pci / layerscape-pci.txt

Freescale Layerscape PCIe controller

This PCIe host controller is based on the Synopsys DesignWare PCIe IP
and thus inherits all the common properties defined in designware-pcie.txt.

This controller derives its clocks from the Reset Configuration Word (RCW)
which is used to describe the PLL settings at the time of chip-reset.

Also as per the available Reference Manuals, there is no specific 'version'
register available in the Freescale PCIe controller register set,
which can allow determining the underlying DesignWare PCIe controller version
information.

Required properties:
- compatible: should contain the platform identifier such as:
        "fsl,ls1021a-pcie", "snps,dw-pcie"
        "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie"
        "fsl,ls1046a-pcie"
- reg: base addresses and lengths of the PCIe controller
- interrupts: A list of interrupt outputs of the controller. Must contain an
  entry for each entry in the interrupt-names property.
- interrupt-names: Must include the following entries:
  "intr": The interrupt that is asserted for controller interrupts
- fsl,pcie-scfg: Must include two entries.
  The first entry must be a link to the SCFG device node
  The second entry must be '0' or '1' based on physical PCIe controller index.
  This is used to get SCFG PEXN registers
- dma-coherent: Indicates that the hardware IP block can ensure the coherency
  of the data transferred from/to the IP block. This can avoid the software
  cache flush/invalid actions, and improve the performance significantly.

Example:

	pcie@3400000 {
		compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
		reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
		       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
		reg-names = "regs", "config";
		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
		interrupt-names = "intr";
		fsl,pcie-scfg = <&scfg 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
		dma-coherent;
		num-lanes = <4>;
		bus-range = <0x0 0xff>;
		ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
			  0xc2000000 0x0 0x20000000 0x40 0x20000000 0x0 0x20000000   /* prefetchable memory */
			  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0000 0 0 1 &gic GIC_SPI 91  IRQ_TYPE_LEVEL_HIGH>,
				<0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
				<0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
				<0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
	};
Commit	Line	Data
62d0ff83 ML	1	Freescale Layerscape PCIe controller
62d0ff83 ML	2
5192ec7b	3	This PCIe host controller is based on the Synopsys DesignWare PCIe IP
62d0ff83 ML	4	and thus inherits all the common properties defined in designware-pcie.txt.
62d0ff83 ML	5
5192ec7b ML	6	This controller derives its clocks from the Reset Configuration Word (RCW)
	7	which is used to describe the PLL settings at the time of chip-reset.
	8
	9	Also as per the available Reference Manuals, there is no specific 'version'
	10	register available in the Freescale PCIe controller register set,
	11	which can allow determining the underlying DesignWare PCIe controller version
	12	information.
	13
62d0ff83	14	Required properties:
5192ec7b ML	15	- compatible: should contain the platform identifier such as:
5192ec7b ML	16	"fsl,ls1021a-pcie", "snps,dw-pcie"
f21a3c7d	17	"fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie"
1d77040b	18	"fsl,ls1046a-pcie"
62d0ff83 ML	19	- reg: base addresses and lengths of the PCIe controller
	20	- interrupts: A list of interrupt outputs of the controller. Must contain an
	21	entry for each entry in the interrupt-names property.
	22	- interrupt-names: Must include the following entries:
	23	"intr": The interrupt that is asserted for controller interrupts
	24	- fsl,pcie-scfg: Must include two entries.
	25	The first entry must be a link to the SCFG device node
	26	The second entry must be '0' or '1' based on physical PCIe controller index.
	27	This is used to get SCFG PEXN registers
2f082b13 LG	28	- dma-coherent: Indicates that the hardware IP block can ensure the coherency
	29	of the data transferred from/to the IP block. This can avoid the software
	30	cache flush/invalid actions, and improve the performance significantly.
62d0ff83 ML	31
	32	Example:
	33
	34	pcie@3400000 {
	35	compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
	36	reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
	37	0x40 0x00000000 0x0 0x00002000>; /* configuration space */
	38	reg-names = "regs", "config";
	39	interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
	40	interrupt-names = "intr";
	41	fsl,pcie-scfg = <&scfg 0>;
	42	#address-cells = <3>;
	43	#size-cells = <2>;
	44	device_type = "pci";
2f082b13	45	dma-coherent;
62d0ff83 ML	46	num-lanes = <4>;
	47	bus-range = <0x0 0xff>;
	48	ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
	49	0xc2000000 0x0 0x20000000 0x40 0x20000000 0x0 0x20000000 /* prefetchable memory */
	50	0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
	51	#interrupt-cells = <1>;
	52	interrupt-map-mask = <0 0 0 7>;
	53	interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
	54	<0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
	55	<0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
	56	<0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
	57	};