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Commit | Line | Data |
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76ce6770 MB |
1 | * Mediatek Universal Asynchronous Receiver/Transmitter (UART) |
2 | ||
3 | Required properties: | |
4 | - compatible should contain: | |
ab407df7 EH |
5 | * "mediatek,mt8135-uart" for MT8135 compatible UARTS |
6 | * "mediatek,mt8127-uart" for MT8127 compatible UARTS | |
83af225c | 7 | * "mediatek,mt8173-uart" for MT8173 compatible UARTS |
afc257bc | 8 | * "mediatek,mt6795-uart" for MT6795 compatible UARTS |
76ce6770 MB |
9 | * "mediatek,mt6589-uart" for MT6589 compatible UARTS |
10 | * "mediatek,mt6582-uart" for MT6582 compatible UARTS | |
69a462b9 | 11 | * "mediatek,mt6580-uart" for MT6580 compatible UARTS |
8d01b66b LT |
12 | * "mediatek,mt6577-uart" for all compatible UARTS (MT8173, MT6795, |
13 | MT6589, MT6582, MT6580, MT6577) | |
76ce6770 MB |
14 | |
15 | - reg: The base address of the UART register bank. | |
16 | ||
17 | - interrupts: A single interrupt specifier. | |
18 | ||
c1c325d7 SH |
19 | - clocks : Must contain an entry for each entry in clock-names. |
20 | See ../clocks/clock-bindings.txt for details. | |
21 | - clock-names: | |
22 | - "baud": The clock the baudrate is derived from | |
23 | - "bus": The bus clock for register accesses (optional) | |
24 | ||
25 | For compatibility with older device trees an unnamed clock is used for the | |
26 | baud clock if the baudclk does not exist. Do not use this for new designs. | |
76ce6770 MB |
27 | |
28 | Example: | |
29 | ||
30 | uart0: serial@11006000 { | |
31 | compatible = "mediatek,mt6589-uart", "mediatek,mt6577-uart"; | |
32 | reg = <0x11006000 0x400>; | |
33 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; | |
c1c325d7 SH |
34 | clocks = <&uart_clk>, <&bus_clk>; |
35 | clock-names = "baud", "bus"; | |
76ce6770 | 36 | }; |