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9cdd273e | 1 | ============================== |
96de0e25 | 2 | PXA2xx SPI on SSP driver HOWTO |
9cdd273e MCC |
3 | ============================== |
4 | ||
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5 | This a mini howto on the pxa2xx_spi driver. The driver turns a PXA2xx |
6 | synchronous serial port into a SPI master controller | |
9cdd273e | 7 | (see Documentation/spi/spi-summary.rst). The driver has the following features |
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8 | |
9 | - Support for any PXA2xx SSP | |
10 | - SSP PIO and SSP DMA data transfers. | |
11 | - External and Internal (SSPFRM) chip selects. | |
12 | - Per slave device (chip) configuration. | |
13 | - Full suspend, freeze, resume support. | |
14 | ||
15 | The driver is built around a "spi_message" fifo serviced by workqueue and a | |
16 | tasklet. The workqueue, "pump_messages", drives message fifo and the tasklet | |
17 | (pump_transfer) is responsible for queuing SPI transactions and setting up and | |
18 | launching the dma/interrupt driven transfers. | |
19 | ||
20 | Declaring PXA2xx Master Controllers | |
21 | ----------------------------------- | |
22 | Typically a SPI master is defined in the arch/.../mach-*/board-*.c as a | |
23 | "platform device". The master configuration is passed to the driver via a table | |
9cdd273e | 24 | found in include/linux/spi/pxa2xx_spi.h:: |
e0c9905e | 25 | |
9cdd273e | 26 | struct pxa2xx_spi_controller { |
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27 | u16 num_chipselect; |
28 | u8 enable_dma; | |
9cdd273e | 29 | }; |
e0c9905e | 30 | |
51eea52d | 31 | The "pxa2xx_spi_controller.num_chipselect" field is used to determine the number of |
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32 | slave device (chips) attached to this SPI master. |
33 | ||
51eea52d | 34 | The "pxa2xx_spi_controller.enable_dma" field informs the driver that SSP DMA should |
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35 | be used. This caused the driver to acquire two DMA channels: rx_channel and |
36 | tx_channel. The rx_channel has a higher DMA service priority the tx_channel. | |
37 | See the "PXA2xx Developer Manual" section "DMA Controller". | |
38 | ||
39 | NSSP MASTER SAMPLE | |
40 | ------------------ | |
9cdd273e | 41 | Below is a sample configuration using the PXA255 NSSP:: |
e0c9905e | 42 | |
9cdd273e | 43 | static struct resource pxa_spi_nssp_resources[] = { |
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44 | [0] = { |
45 | .start = __PREG(SSCR0_P(2)), /* Start address of NSSP */ | |
46 | .end = __PREG(SSCR0_P(2)) + 0x2c, /* Range of registers */ | |
47 | .flags = IORESOURCE_MEM, | |
48 | }, | |
49 | [1] = { | |
50 | .start = IRQ_NSSP, /* NSSP IRQ */ | |
51 | .end = IRQ_NSSP, | |
52 | .flags = IORESOURCE_IRQ, | |
53 | }, | |
9cdd273e | 54 | }; |
e0c9905e | 55 | |
9cdd273e | 56 | static struct pxa2xx_spi_controller pxa_nssp_master_info = { |
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57 | .num_chipselect = 1, /* Matches the number of chips attached to NSSP */ |
58 | .enable_dma = 1, /* Enables NSSP DMA */ | |
9cdd273e | 59 | }; |
e0c9905e | 60 | |
9cdd273e | 61 | static struct platform_device pxa_spi_nssp = { |
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62 | .name = "pxa2xx-spi", /* MUST BE THIS VALUE, so device match driver */ |
63 | .id = 2, /* Bus number, MUST MATCH SSP number 1..n */ | |
64 | .resource = pxa_spi_nssp_resources, | |
65 | .num_resources = ARRAY_SIZE(pxa_spi_nssp_resources), | |
66 | .dev = { | |
67 | .platform_data = &pxa_nssp_master_info, /* Passed to driver */ | |
68 | }, | |
9cdd273e | 69 | }; |
e0c9905e | 70 | |
9cdd273e | 71 | static struct platform_device *devices[] __initdata = { |
e0c9905e | 72 | &pxa_spi_nssp, |
9cdd273e | 73 | }; |
e0c9905e | 74 | |
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75 | static void __init board_init(void) |
76 | { | |
e0c9905e | 77 | (void)platform_add_device(devices, ARRAY_SIZE(devices)); |
9cdd273e | 78 | } |
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79 | |
80 | Declaring Slave Devices | |
81 | ----------------------- | |
82 | Typically each SPI slave (chip) is defined in the arch/.../mach-*/board-*.c | |
83 | using the "spi_board_info" structure found in "linux/spi/spi.h". See | |
9cdd273e | 84 | "Documentation/spi/spi-summary.rst" for additional information. |
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85 | |
86 | Each slave device attached to the PXA must provide slave specific configuration | |
87 | information via the structure "pxa2xx_spi_chip" found in | |
8348c259 | 88 | "include/linux/spi/pxa2xx_spi.h". The pxa2xx_spi master controller driver |
e0c9905e | 89 | will uses the configuration whenever the driver communicates with the slave |
f1f640a9 | 90 | device. All fields are optional. |
e0c9905e | 91 | |
9cdd273e MCC |
92 | :: |
93 | ||
94 | struct pxa2xx_spi_chip { | |
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95 | u8 tx_threshold; |
96 | u8 rx_threshold; | |
97 | u8 dma_burst_size; | |
8d94cc50 | 98 | u32 timeout; |
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99 | u8 enable_loopback; |
100 | void (*cs_control)(u32 command); | |
9cdd273e | 101 | }; |
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102 | |
103 | The "pxa2xx_spi_chip.tx_threshold" and "pxa2xx_spi_chip.rx_threshold" fields are | |
104 | used to configure the SSP hardware fifo. These fields are critical to the | |
105 | performance of pxa2xx_spi driver and misconfiguration will result in rx | |
9cdd273e | 106 | fifo overruns (especially in PIO mode transfers). Good default values are:: |
e0c9905e | 107 | |
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108 | .tx_threshold = 8, |
109 | .rx_threshold = 8, | |
110 | ||
111 | The range is 1 to 16 where zero indicates "use default". | |
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112 | |
113 | The "pxa2xx_spi_chip.dma_burst_size" field is used to configure PXA2xx DMA | |
114 | engine and is related the "spi_device.bits_per_word" field. Read and understand | |
115 | the PXA2xx "Developer Manual" sections on the DMA controller and SSP Controllers | |
116 | to determine the correct value. An SSP configured for byte-wide transfers would | |
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117 | use a value of 8. The driver will determine a reasonable default if |
118 | dma_burst_size == 0. | |
e0c9905e | 119 | |
8d94cc50 | 120 | The "pxa2xx_spi_chip.timeout" fields is used to efficiently handle |
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121 | trailing bytes in the SSP receiver fifo. The correct value for this field is |
122 | dependent on the SPI bus speed ("spi_board_info.max_speed_hz") and the specific | |
670e9f34 | 123 | slave device. Please note that the PXA2xx SSP 1 does not support trailing byte |
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124 | timeouts and must busy-wait any trailing bytes. |
125 | ||
126 | The "pxa2xx_spi_chip.enable_loopback" field is used to place the SSP porting | |
127 | into internal loopback mode. In this mode the SSP controller internally | |
670e9f34 | 128 | connects the SSPTX pin to the SSPRX pin. This is useful for initial setup |
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129 | testing. |
130 | ||
131 | The "pxa2xx_spi_chip.cs_control" field is used to point to a board specific | |
132 | function for asserting/deasserting a slave device chip select. If the field is | |
133 | NULL, the pxa2xx_spi master controller driver assumes that the SSP port is | |
134 | configured to use SSPFRM instead. | |
135 | ||
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136 | NOTE: the SPI driver cannot control the chip select if SSPFRM is used, so the |
137 | chipselect is dropped after each spi_transfer. Most devices need chip select | |
138 | asserted around the complete message. Use SSPFRM as a GPIO (through cs_control) | |
25985edc | 139 | to accommodate these chips. |
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140 | |
141 | ||
142 | NSSP SLAVE SAMPLE | |
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143 | ----------------- |
144 | The pxa2xx_spi_chip structure is passed to the pxa2xx_spi driver in the | |
145 | "spi_board_info.controller_data" field. Below is a sample configuration using | |
146 | the PXA255 NSSP. | |
147 | ||
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148 | :: |
149 | ||
150 | /* Chip Select control for the CS8415A SPI slave device */ | |
151 | static void cs8415a_cs_control(u32 command) | |
152 | { | |
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153 | if (command & PXA2XX_CS_ASSERT) |
154 | GPCR(2) = GPIO_bit(2); | |
155 | else | |
156 | GPSR(2) = GPIO_bit(2); | |
9cdd273e | 157 | } |
e0c9905e | 158 | |
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159 | /* Chip Select control for the CS8405A SPI slave device */ |
160 | static void cs8405a_cs_control(u32 command) | |
161 | { | |
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162 | if (command & PXA2XX_CS_ASSERT) |
163 | GPCR(3) = GPIO_bit(3); | |
164 | else | |
165 | GPSR(3) = GPIO_bit(3); | |
9cdd273e | 166 | } |
e0c9905e | 167 | |
9cdd273e | 168 | static struct pxa2xx_spi_chip cs8415a_chip_info = { |
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169 | .tx_threshold = 8, /* SSP hardward FIFO threshold */ |
170 | .rx_threshold = 8, /* SSP hardward FIFO threshold */ | |
e0c9905e | 171 | .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */ |
8d94cc50 | 172 | .timeout = 235, /* See Intel documentation */ |
e0c9905e | 173 | .cs_control = cs8415a_cs_control, /* Use external chip select */ |
9cdd273e | 174 | }; |
e0c9905e | 175 | |
9cdd273e | 176 | static struct pxa2xx_spi_chip cs8405a_chip_info = { |
8d94cc50 SS |
177 | .tx_threshold = 8, /* SSP hardward FIFO threshold */ |
178 | .rx_threshold = 8, /* SSP hardward FIFO threshold */ | |
e0c9905e | 179 | .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */ |
8d94cc50 | 180 | .timeout = 235, /* See Intel documentation */ |
e0c9905e | 181 | .cs_control = cs8405a_cs_control, /* Use external chip select */ |
9cdd273e | 182 | }; |
e0c9905e | 183 | |
9cdd273e | 184 | static struct spi_board_info streetracer_spi_board_info[] __initdata = { |
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185 | { |
186 | .modalias = "cs8415a", /* Name of spi_driver for this device */ | |
187 | .max_speed_hz = 3686400, /* Run SSP as fast a possbile */ | |
188 | .bus_num = 2, /* Framework bus number */ | |
189 | .chip_select = 0, /* Framework chip select */ | |
190 | .platform_data = NULL; /* No spi_driver specific config */ | |
191 | .controller_data = &cs8415a_chip_info, /* Master chip config */ | |
192 | .irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */ | |
193 | }, | |
194 | { | |
195 | .modalias = "cs8405a", /* Name of spi_driver for this device */ | |
196 | .max_speed_hz = 3686400, /* Run SSP as fast a possbile */ | |
197 | .bus_num = 2, /* Framework bus number */ | |
198 | .chip_select = 1, /* Framework chip select */ | |
199 | .controller_data = &cs8405a_chip_info, /* Master chip config */ | |
200 | .irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */ | |
201 | }, | |
9cdd273e | 202 | }; |
e0c9905e | 203 | |
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204 | static void __init streetracer_init(void) |
205 | { | |
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206 | spi_register_board_info(streetracer_spi_board_info, |
207 | ARRAY_SIZE(streetracer_spi_board_info)); | |
9cdd273e | 208 | } |
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209 | |
210 | ||
211 | DMA and PIO I/O Support | |
212 | ----------------------- | |
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213 | The pxa2xx_spi driver supports both DMA and interrupt driven PIO message |
214 | transfers. The driver defaults to PIO mode and DMA transfers must be enabled | |
51eea52d | 215 | by setting the "enable_dma" flag in the "pxa2xx_spi_controller" structure. The DMA |
f1f640a9 | 216 | mode supports both coherent and stream based DMA mappings. |
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217 | |
218 | The following logic is used to determine the type of I/O to be used on | |
9cdd273e | 219 | a per "spi_transfer" basis:: |
e0c9905e | 220 | |
9cdd273e | 221 | if !enable_dma then |
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222 | always use PIO transfers |
223 | ||
9cdd273e | 224 | if spi_message.len > 8191 then |
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225 | print "rate limited" warning |
226 | use PIO transfers | |
227 | ||
9cdd273e | 228 | if spi_message.is_dma_mapped and rx_dma_buf != 0 and tx_dma_buf != 0 then |
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229 | use coherent DMA mode |
230 | ||
9cdd273e | 231 | if rx_buf and tx_buf are aligned on 8 byte boundary then |
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232 | use streaming DMA mode |
233 | ||
9cdd273e | 234 | otherwise |
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235 | use PIO transfer |
236 | ||
237 | THANKS TO | |
238 | --------- | |
239 | ||
240 | David Brownell and others for mentoring the development of this driver. |