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c69dd9df | 1 | /*++\r |
2 | \r | |
b1f700a8 HT |
3 | Copyright (c) 2005 - 2006, Intel Corporation. All rights reserved.<BR>\r |
4 | This program and the accompanying materials \r | |
c69dd9df | 5 | are licensed and made available under the terms and conditions of the BSD License \r |
6 | which accompanies this distribution. The full text of the license may be found at \r | |
7 | http://opensource.org/licenses/bsd-license.php \r | |
8 | \r | |
9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
11 | \r | |
12 | Module Name:\r | |
13 | PcatPciRootBridge.h\r | |
14 | \r | |
15 | Abstract:\r | |
16 | \r | |
17 | The driver for the host to pci bridge (root bridge).\r | |
18 | \r | |
19 | --*/\r | |
20 | \r | |
21 | #ifndef _PCAT_PCI_ROOT_BRIDGE_H_\r | |
22 | #define _PCAT_PCI_ROOT_BRIDGE_H_\r | |
23 | \r | |
24 | #include <PiDxe.h>\r | |
25 | #include <Protocol/PciRootBridgeIo.h>\r | |
26 | #include <Protocol/DeviceIo.h>\r | |
b6d793e3 | 27 | #include <Protocol/CpuIo2.h>\r |
c69dd9df | 28 | \r |
29 | #include <Library/UefiLib.h>\r | |
30 | #include <Library/BaseLib.h>\r | |
31 | #include <Library/MemoryAllocationLib.h>\r | |
32 | #include <Library/UefiBootServicesTableLib.h>\r | |
33 | #include <Library/DebugLib.h>\r | |
34 | #include <Library/BaseMemoryLib.h>\r | |
35 | #include <Library/DevicePathLib.h>\r | |
36 | #include <Library/HobLib.h>\r | |
37 | \r | |
38 | #include <Guid/PciOptionRomTable.h>\r | |
39 | #include <Guid/HobList.h>\r | |
40 | #include <Guid/PciExpressBaseAddress.h>\r | |
41 | \r | |
42 | #include <IndustryStandard/Acpi.h>\r | |
43 | #include <IndustryStandard/Pci.h>\r | |
a51a9ea3 | 44 | \r |
45 | #define PCI_MAX_SEGMENT 0\r | |
c69dd9df | 46 | //\r |
47 | // Driver Instance Data Prototypes\r | |
48 | //\r | |
eea53ce1 | 49 | #define PCAT_PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32('p', 'c', 'r', 'b')\r |
c69dd9df | 50 | \r |
51 | typedef struct {\r | |
52 | UINT32 Signature;\r | |
53 | EFI_HANDLE Handle;\r | |
54 | \r | |
55 | EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r | |
56 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io;\r | |
b6d793e3 | 57 | EFI_CPU_IO2_PROTOCOL *CpuIo;\r |
c69dd9df | 58 | \r |
59 | UINT32 RootBridgeNumber;\r | |
60 | UINT32 PrimaryBus;\r | |
61 | UINT32 SubordinateBus;\r | |
62 | \r | |
63 | UINT64 MemBase; // Offsets host to bus memory addr.\r | |
64 | UINT64 MemLimit; // Max allowable memory access\r | |
65 | \r | |
66 | UINT64 IoBase; // Offsets host to bus io addr.\r | |
67 | UINT64 IoLimit; // Max allowable io access\r | |
68 | \r | |
69 | UINT64 PciAddress;\r | |
70 | UINT64 PciData;\r | |
71 | \r | |
72 | UINT64 PhysicalMemoryBase;\r | |
73 | UINT64 PhysicalIoBase;\r | |
74 | \r | |
75 | EFI_LOCK PciLock;\r | |
76 | \r | |
77 | UINT64 Attributes;\r | |
78 | \r | |
79 | UINT64 Mem32Base;\r | |
80 | UINT64 Mem32Limit;\r | |
81 | UINT64 Pmem32Base;\r | |
82 | UINT64 Pmem32Limit;\r | |
83 | UINT64 Mem64Base;\r | |
84 | UINT64 Mem64Limit;\r | |
85 | UINT64 Pmem64Base;\r | |
86 | UINT64 Pmem64Limit;\r | |
87 | \r | |
88 | UINT64 PciExpressBaseAddress;\r | |
89 | \r | |
90 | EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;\r | |
91 | \r | |
92 | LIST_ENTRY MapInfo;\r | |
93 | } PCAT_PCI_ROOT_BRIDGE_INSTANCE;\r | |
94 | \r | |
95 | //\r | |
96 | // Driver Instance Data Macros\r | |
97 | //\r | |
98 | #define DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) \\r | |
99 | CR(a, PCAT_PCI_ROOT_BRIDGE_INSTANCE, Io, PCAT_PCI_ROOT_BRIDGE_SIGNATURE)\r | |
100 | \r | |
c69dd9df | 101 | //\r |
102 | // Private data types\r | |
103 | //\r | |
104 | typedef union {\r | |
e1cdd2eb | 105 | UINT8 volatile *buf;\r |
106 | UINT8 volatile *ui8;\r | |
107 | UINT16 volatile *ui16;\r | |
108 | UINT32 volatile *ui32;\r | |
109 | UINT64 volatile *ui64;\r | |
110 | UINTN volatile ui;\r | |
c69dd9df | 111 | } PTR;\r |
112 | \r | |
113 | typedef struct {\r | |
114 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation;\r | |
115 | UINTN NumberOfBytes;\r | |
116 | UINTN NumberOfPages;\r | |
117 | EFI_PHYSICAL_ADDRESS HostAddress;\r | |
118 | EFI_PHYSICAL_ADDRESS MappedHostAddress;\r | |
119 | } MAP_INFO;\r | |
120 | \r | |
121 | typedef struct {\r | |
122 | LIST_ENTRY Link;\r | |
123 | MAP_INFO * Map; \r | |
124 | } MAP_INFO_INSTANCE;\r | |
125 | \r | |
126 | typedef\r | |
127 | VOID\r | |
128 | (*EFI_PCI_BUS_SCAN_CALLBACK) (\r | |
129 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r | |
130 | UINT16 MinBus,\r | |
131 | UINT16 MaxBus,\r | |
132 | UINT16 MinDevice,\r | |
133 | UINT16 MaxDevice,\r | |
134 | UINT16 MinFunc,\r | |
135 | UINT16 MaxFunc,\r | |
136 | UINT16 Bus,\r | |
137 | UINT16 Device,\r | |
138 | UINT16 Func,\r | |
139 | IN VOID *Context\r | |
140 | );\r | |
141 | \r | |
142 | typedef struct {\r | |
143 | UINT16 *CommandRegisterBuffer;\r | |
144 | UINT32 PpbMemoryWindow; \r | |
145 | } PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT;\r | |
146 | \r | |
8ad48840 | 147 | typedef struct {\r |
148 | UINT8 Register;\r | |
149 | UINT8 Function;\r | |
150 | UINT8 Device;\r | |
151 | UINT8 Bus;\r | |
152 | UINT8 Reserved[4];\r | |
153 | } DEFIO_PCI_ADDR;\r | |
154 | \r | |
c69dd9df | 155 | //\r |
156 | // Driver Protocol Constructor Prototypes\r | |
157 | //\r | |
158 | EFI_STATUS \r | |
159 | ConstructConfiguration(\r | |
160 | IN OUT PCAT_PCI_ROOT_BRIDGE_INSTANCE *PrivateData\r | |
161 | );\r | |
162 | \r | |
163 | EFI_STATUS\r | |
164 | PcatPciRootBridgeParseBars (\r | |
165 | IN PCAT_PCI_ROOT_BRIDGE_INSTANCE *PrivateData,\r | |
166 | IN UINT16 Command,\r | |
167 | IN UINTN Bus,\r | |
168 | IN UINTN Device,\r | |
169 | IN UINTN Function\r | |
170 | );\r | |
171 | \r | |
172 | EFI_STATUS\r | |
173 | ScanPciRootBridgeForRoms(\r | |
174 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r | |
175 | );\r | |
176 | \r | |
177 | EFI_STATUS\r | |
178 | PcatRootBridgeDevicePathConstructor (\r | |
179 | IN EFI_DEVICE_PATH_PROTOCOL **Protocol,\r | |
180 | IN UINTN RootBridgeNumber,\r | |
181 | IN BOOLEAN IsPciExpress\r | |
182 | );\r | |
183 | \r | |
184 | EFI_STATUS\r | |
185 | PcatRootBridgeIoConstructor (\r | |
186 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol,\r | |
187 | IN UINTN SegmentNumber\r | |
188 | );\r | |
189 | \r | |
190 | EFI_STATUS\r | |
191 | PcatRootBridgeIoGetIoPortMapping (\r | |
192 | OUT EFI_PHYSICAL_ADDRESS *IoPortMapping,\r | |
193 | OUT EFI_PHYSICAL_ADDRESS *MemoryPortMapping\r | |
194 | );\r | |
195 | \r | |
196 | EFI_STATUS\r | |
197 | PcatRootBridgeIoPciRW (\r | |
198 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
199 | IN BOOLEAN Write,\r | |
200 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r | |
201 | IN UINT64 UserAddress,\r | |
202 | IN UINTN Count,\r | |
203 | IN OUT VOID *UserBuffer\r | |
204 | );\r | |
205 | \r | |
206 | UINT64\r | |
207 | GetPciExpressBaseAddressForRootBridge (\r | |
208 | IN UINTN HostBridgeNumber,\r | |
209 | IN UINTN RootBridgeNumber\r | |
210 | );\r | |
211 | \r | |
0492698a | 212 | EFI_STATUS\r |
213 | EFIAPI\r | |
214 | PcatRootBridgeIoIoRead (\r | |
215 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
216 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r | |
217 | IN UINT64 UserAddress,\r | |
218 | IN UINTN Count,\r | |
219 | IN OUT VOID *UserBuffer\r | |
220 | );\r | |
221 | \r | |
222 | EFI_STATUS\r | |
223 | EFIAPI\r | |
224 | PcatRootBridgeIoIoWrite (\r | |
225 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
226 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r | |
227 | IN UINT64 UserAddress,\r | |
228 | IN UINTN Count,\r | |
229 | IN OUT VOID *UserBuffer\r | |
230 | );\r | |
231 | \r | |
c69dd9df | 232 | //\r |
233 | // Driver entry point prototype\r | |
234 | //\r | |
235 | EFI_STATUS\r | |
236 | EFIAPI\r | |
237 | InitializePcatPciRootBridge (\r | |
238 | IN EFI_HANDLE ImageHandle,\r | |
239 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
240 | );\r | |
241 | \r | |
b6d793e3 | 242 | extern EFI_CPU_IO2_PROTOCOL *gCpuIo;\r |
c69dd9df | 243 | \r |
244 | #endif\r |