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b341712e | 1 | #------------------------------------------------------------------------------\r |
2 | #\r | |
be3b67bc | 3 | # Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r |
2c7e5c2f | 4 | # This program and the accompanying materials\r |
b341712e | 5 | # are licensed and made available under the terms and conditions of the BSD License\r |
6 | # which accompanies this distribution. The full text of the license may be found at\r | |
7 | # http://opensource.org/licenses/bsd-license.php\r | |
8 | #\r | |
9 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
10 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
11 | #\r | |
12 | # Module Name:\r | |
13 | #\r | |
14 | # Thunk16.S\r | |
15 | #\r | |
16 | # Abstract:\r | |
17 | #\r | |
18 | # Real mode thunk\r | |
19 | #\r | |
20 | #------------------------------------------------------------------------------\r | |
21 | \r | |
22 | #include <EdkIIGlueBase.h>\r | |
23 | \r | |
24 | .globl ASM_PFX(m16Start)\r | |
25 | .globl ASM_PFX(m16Size)\r | |
26 | .globl ASM_PFX(mThunk16Attr)\r | |
27 | .globl ASM_PFX(m16Gdt)\r | |
28 | .globl ASM_PFX(m16GdtrBase)\r | |
29 | .globl ASM_PFX(mTransition)\r | |
30 | .globl ASM_PFX(InternalAsmThunk16)\r | |
31 | \r | |
32 | # define the structure of IA32_REGS\r | |
33 | .equ _EDI, 0 #size 4\r | |
34 | .equ _ESI, 4 #size 4\r | |
35 | .equ _EBP, 8 #size 4\r | |
36 | .equ _ESP, 12 #size 4\r | |
37 | .equ _EBX, 16 #size 4\r | |
38 | .equ _EDX, 20 #size 4\r | |
39 | .equ _ECX, 24 #size 4\r | |
40 | .equ _EAX, 28 #size 4\r | |
41 | .equ _DS, 32 #size 2\r | |
42 | .equ _ES, 34 #size 2\r | |
43 | .equ _FS, 36 #size 2\r | |
44 | .equ _GS, 38 #size 2\r | |
45 | .equ _EFLAGS, 40 #size 8\r | |
46 | .equ _EIP, 48 #size 4\r | |
47 | .equ _CS, 52 #size 2\r | |
48 | .equ _SS, 54 #size 2\r | |
49 | .equ IA32_REGS_SIZE, 56\r | |
50 | \r | |
51 | .data\r | |
52 | \r | |
53 | ASM_PFX(m16Size): .word ASM_PFX(InternalAsmThunk16) - ASM_PFX(m16Start)\r | |
54 | ASM_PFX(mThunk16Attr): .word _ThunkAttr - ASM_PFX(m16Start)\r | |
55 | ASM_PFX(m16Gdt): .word ASM_PFX(NullSeg) - ASM_PFX(m16Start)\r | |
56 | ASM_PFX(m16GdtrBase): .word _16GdtrBase - ASM_PFX(m16Start)\r | |
57 | ASM_PFX(mTransition): .word _EntryPoint - ASM_PFX(m16Start)\r | |
58 | \r | |
59 | .text\r | |
60 | \r | |
61 | ASM_PFX(m16Start):\r | |
62 | \r | |
63 | SavedGdt: .space 10\r | |
64 | \r | |
65 | #------------------------------------------------------------------------------\r | |
66 | # _BackFromUserCode() takes control in real mode after 'retf' has been executed\r | |
67 | # by user code. It will be shadowed to somewhere in memory below 1MB.\r | |
68 | #------------------------------------------------------------------------------\r | |
69 | .globl ASM_PFX(BackFromUserCode)\r | |
70 | ASM_PFX(BackFromUserCode):\r | |
71 | #\r | |
72 | # The order of saved registers on the stack matches the order they appears\r | |
73 | # in IA32_REGS structure. This facilitates wrapper function to extract them\r | |
74 | # into that structure.\r | |
75 | #\r | |
76 | # Some instructions for manipulation of segment registers have to be written\r | |
77 | # in opcode since 64-bit MASM prevents accesses to those registers.\r | |
78 | #\r | |
79 | .byte 0x16 # push ss\r | |
80 | .byte 0xe # push cs\r | |
81 | .byte 0x66\r | |
82 | call L_Base # push eip\r | |
83 | L_Base: \r | |
84 | .byte 0x66\r | |
85 | pushq $0 # reserved high order 32 bits of EFlags\r | |
86 | .byte 0x66, 0x9c # pushfd actually\r | |
87 | cli # disable interrupts\r | |
88 | push %gs\r | |
89 | push %fs\r | |
90 | .byte 6 # push es\r | |
91 | .byte 0x1e # push ds\r | |
92 | .byte 0x66,0x60 # pushad\r | |
93 | .byte 0x66,0xba # mov edx, imm32\r | |
94 | _ThunkAttr: .space 4\r | |
95 | testb $THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15, %dl\r | |
96 | jz L_1\r | |
97 | movl $0x15cd2401,%eax # mov ax, 2401h & int 15h\r | |
98 | cli # disable interrupts\r | |
99 | jnc L_2\r | |
100 | L_1: \r | |
101 | testb $THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL, %dl\r | |
102 | jz L_2\r | |
103 | inb $0x92,%al\r | |
104 | orb $2,%al\r | |
105 | outb %al, $0x92 # deactivate A20M#\r | |
106 | L_2: \r | |
be3b67bc | 107 | movw %ss,%ax\r |
b341712e | 108 | lea IA32_REGS_SIZE(%esp), %bp\r |
109 | #\r | |
110 | # rsi in the following 2 instructions is indeed bp in 16-bit code\r | |
111 | #\r | |
112 | movw %bp, (_ESP - IA32_REGS_SIZE)(%rsi)\r | |
113 | .byte 0x66\r | |
114 | movl (_EIP - IA32_REGS_SIZE)(%rsi), %ebx\r | |
115 | shlw $4,%ax # shl eax, 4\r | |
116 | addw %ax,%bp # add ebp, eax\r | |
117 | movw %cs,%ax\r | |
118 | shlw $4,%ax\r | |
119 | lea (L_64BitCode - L_Base)(%ebx, %eax), %ax\r | |
120 | .byte 0x66,0x2e,0x89,0x87 # mov cs:[bx + (L_64Eip - L_Base)], eax\r | |
121 | .word L_64Eip - L_Base\r | |
122 | .byte 0x66,0xb8 # mov eax, imm32\r | |
123 | SavedCr4: .space 4\r | |
124 | movq %rax, %cr4\r | |
125 | #\r | |
126 | # rdi in the instruction below is indeed bx in 16-bit code\r | |
127 | #\r | |
128 | .byte 0x66,0x2e # 2eh is "cs:" segment override\r | |
129 | lgdt (SavedGdt - L_Base)(%rdi)\r | |
130 | .byte 0x66\r | |
131 | movl $0xc0000080,%ecx\r | |
132 | rdmsr\r | |
133 | orb $1,%ah\r | |
134 | wrmsr\r | |
135 | .byte 0x66,0xb8 # mov eax, imm32\r | |
136 | SavedCr0: .space 4\r | |
137 | movq %rax, %cr0\r | |
138 | .byte 0x66,0xea # jmp far cs:L_64Bit\r | |
139 | L_64Eip: .space 4\r | |
140 | SavedCs: .space 2\r | |
141 | L_64BitCode: \r | |
142 | .byte 0x90\r | |
143 | .byte 0x67,0xbc # mov esp, imm32\r | |
144 | SavedSp: .space 4 # restore stack\r | |
145 | nop\r | |
146 | ret\r | |
147 | \r | |
148 | _EntryPoint: .long ASM_PFX(ToUserCode) - ASM_PFX(m16Start)\r | |
149 | .word CODE16\r | |
150 | _16Gdtr: .word GDT_SIZE - 1\r | |
151 | _16GdtrBase: .quad ASM_PFX(NullSeg)\r | |
152 | _16Idtr: .word 0x3ff\r | |
153 | .long 0\r | |
154 | \r | |
155 | #------------------------------------------------------------------------------\r | |
156 | # _ToUserCode() takes control in real mode before passing control to user code.\r | |
157 | # It will be shadowed to somewhere in memory below 1MB.\r | |
158 | #------------------------------------------------------------------------------\r | |
159 | .globl ASM_PFX(ToUserCode)\r | |
160 | ASM_PFX(ToUserCode):\r | |
161 | movl %edx,%ss # set new segment selectors\r | |
162 | movl %edx,%ds\r | |
163 | movl %edx,%es\r | |
164 | movl %edx,%fs\r | |
165 | movl %edx,%gs\r | |
166 | .byte 0x66\r | |
167 | movl $0xc0000080,%ecx\r | |
168 | movq %rax, %cr0\r | |
169 | rdmsr\r | |
170 | andb $0b11111110, %ah \r | |
171 | wrmsr\r | |
172 | movq %rbp, %cr4\r | |
173 | movl %esi,%ss # set up 16-bit stack segment\r | |
174 | movw %bx,%sp # set up 16-bit stack pointer\r | |
175 | .byte 0x66 # make the following call 32-bit\r | |
176 | call L_Base1 # push eip\r | |
177 | L_Base1: \r | |
178 | popw %bp # ebp <- address of L_Base1\r | |
179 | pushq (IA32_REGS_SIZE + 2)(%esp)\r | |
180 | lea 0x0c(%rsi), %eax\r | |
181 | pushq %rax\r | |
182 | lret # execution begins at next instruction\r | |
183 | L_RealMode: \r | |
184 | .byte 0x66,0x2e # CS and operand size override\r | |
185 | lidt (_16Idtr - L_Base1)(%rsi)\r | |
186 | .byte 0x66,0x61 # popad\r | |
187 | .byte 0x1f # pop ds\r | |
188 | .byte 0x7 # pop es\r | |
189 | .byte 0x0f, 0xa1 # pop fs\r | |
190 | .byte 0x0f, 0xa9 # pop gs\r | |
191 | .byte 0x66, 0x9d # popfd\r | |
192 | leaw 4(%esp),%sp # skip high order 32 bits of EFlags\r | |
193 | .byte 0x66 # make the following retf 32-bit\r | |
194 | lret # transfer control to user code\r | |
195 | \r | |
196 | .equ CODE16, ASM_PFX(_16Code) - .\r | |
197 | .equ DATA16, ASM_PFX(_16Data) - .\r | |
198 | .equ DATA32, ASM_PFX(_32Data) - .\r | |
199 | \r | |
200 | ASM_PFX(NullSeg): .quad 0\r | |
201 | ASM_PFX(_16Code):\r | |
202 | .word -1\r | |
203 | .word 0\r | |
204 | .byte 0\r | |
205 | .byte 0x9b\r | |
206 | .byte 0x8f # 16-bit segment, 4GB limit\r | |
207 | .byte 0\r | |
208 | ASM_PFX(_16Data):\r | |
209 | .word -1\r | |
210 | .word 0\r | |
211 | .byte 0\r | |
212 | .byte 0x93\r | |
213 | .byte 0x8f # 16-bit segment, 4GB limit\r | |
214 | .byte 0\r | |
215 | ASM_PFX(_32Data):\r | |
216 | .word -1\r | |
217 | .word 0\r | |
218 | .byte 0\r | |
219 | .byte 0x93\r | |
220 | .byte 0xcf # 16-bit segment, 4GB limit\r | |
221 | .byte 0\r | |
222 | \r | |
223 | .equ GDT_SIZE, . - ASM_PFX(NullSeg)\r | |
224 | \r | |
225 | #------------------------------------------------------------------------------\r | |
226 | # IA32_REGISTER_SET *\r | |
227 | # EFIAPI\r | |
228 | # InternalAsmThunk16 (\r | |
229 | # IN IA32_REGISTER_SET *RegisterSet,\r | |
230 | # IN OUT VOID *Transition\r | |
231 | # );\r | |
232 | #------------------------------------------------------------------------------\r | |
233 | \r | |
234 | .globl ASM_PFX(InternalAsmThunk16)\r | |
235 | ASM_PFX(InternalAsmThunk16):\r | |
236 | pushq %rbp\r | |
237 | pushq %rbx\r | |
238 | pushq %rsi\r | |
239 | pushq %rdi\r | |
240 | \r | |
241 | movq %ds, %rbx\r | |
242 | pushq %rbx # Save ds segment register on the stack\r | |
243 | movq %es, %rbx\r | |
244 | pushq %rbx # Save es segment register on the stack\r | |
245 | movq %ss, %rbx\r | |
246 | pushq %rbx # Save ss segment register on the stack\r | |
247 | \r | |
248 | .byte 0x0f, 0xa0 #push fs\r | |
249 | .byte 0x0f, 0xa8 #push gs\r | |
250 | movq %rcx, %rsi\r | |
251 | movzwl _SS(%rsi), %r8d\r | |
252 | movl _ESP(%rsi), %edi\r | |
253 | lea -(IA32_REGS_SIZE + 4)(%edi), %rdi\r | |
254 | imul $16, %r8d, %eax \r | |
255 | movl %edi,%ebx # ebx <- stack for 16-bit code\r | |
256 | pushq $(IA32_REGS_SIZE / 4)\r | |
257 | addl %eax,%edi # edi <- linear address of 16-bit stack\r | |
258 | popq %rcx\r | |
259 | rep\r | |
260 | movsl # copy RegSet\r | |
261 | lea (SavedCr4 - ASM_PFX(m16Start))(%rdx), %ecx\r | |
262 | movl %edx,%eax # eax <- transition code address\r | |
263 | andl $0xf,%edx\r | |
264 | shll $12,%eax # segment address in high order 16 bits\r | |
265 | lea (_BackFromUserCode - ASM_PFX(m16Start))(%rdx), %ax\r | |
266 | stosl # [edi] <- return address of user code\r | |
267 | sgdt (SavedGdt - SavedCr4)(%rcx) \r | |
268 | sidt 0x50(%rsp)\r | |
269 | movq %cr0, %rax\r | |
270 | movl %eax, (SavedCr0 - SavedCr4)(%rcx)\r | |
271 | andl $0x7ffffffe,%eax # clear PE, PG bits\r | |
272 | movq %cr4, %rbp\r | |
273 | movl %ebp, (%rcx) # save CR4 in SavedCr4\r | |
274 | andl $0x300,%ebp # clear all but PCE and OSFXSR bits\r | |
275 | movl %r8d, %esi # esi <- 16-bit stack segment\r | |
276 | .byte 0x6a, DATA32\r | |
277 | popq %rdx\r | |
278 | lgdt (_16Gdtr - SavedCr4)(%rcx)\r | |
279 | movl %edx,%ss\r | |
280 | pushfq\r | |
281 | lea -8(%rdx), %edx\r | |
282 | lea L_RetFromRealMode, %r8\r | |
283 | pushq %r8\r | |
284 | movl %cs, %r8d\r | |
285 | movw %r8w, (SavedCs - SavedCr4)(%rcx)\r | |
286 | movl %esp, (SavedSp - SavedCr4)(%rcx)\r | |
287 | .byte 0xff, 0x69 # jmp (_EntryPoint - SavedCr4)(%rcx)\r | |
288 | .byte _EntryPoint - SavedCr4\r | |
289 | L_RetFromRealMode: \r | |
290 | popfq\r | |
291 | lidt 0x50(%rsp)\r | |
292 | lea -IA32_REGS_SIZE(%rbp), %eax\r | |
293 | .byte 0x0f, 0xa9 # pop gs\r | |
294 | .byte 0x0f, 0xa1 # pop fs\r | |
295 | \r | |
296 | popq %rbx\r | |
297 | movq %rbx, %ss\r | |
298 | popq %rbx\r | |
299 | movq %rbx, %es\r | |
300 | popq %rbx\r | |
301 | movq %rbx, %ds\r | |
302 | \r | |
303 | popq %rdi\r | |
304 | popq %rsi\r | |
305 | popq %rbx\r | |
306 | popq %rbp\r | |
307 | \r | |
308 | ret\r |