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1 | /** @file\r |
2 | * Header containing the structure specific to the Silicon Image I3132 Sata PCI card\r | |
3 | *\r | |
4 | * Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r | |
5 | *\r | |
6 | * This program and the accompanying materials\r | |
7 | * are licensed and made available under the terms and conditions of the BSD License\r | |
8 | * which accompanies this distribution. The full text of the license may be found at\r | |
9 | * http://opensource.org/licenses/bsd-license.php\r | |
10 | *\r | |
11 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | *\r | |
14 | **/\r | |
15 | \r | |
16 | #ifndef __SATASII3132_H\r | |
17 | #define __SATASII3132_H\r | |
18 | \r | |
19 | #include <PiDxe.h>\r | |
20 | \r | |
21 | #include <Protocol/AtaPassThru.h>\r | |
22 | #include <Protocol/PciIo.h>\r | |
23 | \r | |
24 | #include <Library/UefiLib.h>\r | |
25 | #include <Library/DebugLib.h>\r | |
26 | #include <Library/PcdLib.h>\r | |
27 | #include <Library/BaseMemoryLib.h>\r | |
28 | #include <Library/UefiBootServicesTableLib.h>\r | |
29 | \r | |
30 | #include <IndustryStandard/Pci.h>\r | |
31 | \r | |
32 | #define SATA_SII3132_DEVICE_ID 0x3132\r | |
33 | #define SATA_SII3132_VENDOR_ID 0x1095\r | |
34 | \r | |
35 | #define SII3132_PORT_SIGNATURE_PMP 0x96690101\r | |
36 | #define SII3132_PORT_SIGNATURE_ATAPI 0xEB140101\r | |
37 | #define SII3132_PORT_SIGNATURE_ATA 0x00000101\r | |
38 | \r | |
39 | /*\r | |
40 | * Silicon Image SiI3132 Registers\r | |
41 | */\r | |
42 | #define SII3132_GLOBAL_CONTROL_REG 0x40\r | |
43 | #define SII3132_GLOBAL_FLASHADDR_REG 0x70\r | |
44 | \r | |
45 | #define SII3132_PORT_STATUS_REG 0x1000\r | |
46 | #define SII3132_PORT_CONTROLSET_REG 0x1000\r | |
47 | #define SII3132_PORT_CONTROLCLEAR_REG 0x1004\r | |
48 | #define SII3132_PORT_INTSTATUS_REG 0x1008\r | |
49 | #define SII3132_PORT_ENABLEINT_REG 0x1010\r | |
50 | #define SII3132_PORT_INTCLEAR_REG 0x1014\r | |
51 | #define SII3132_PORT_32BITACTIVADDR_REG 0x101C\r | |
52 | #define SII3132_PORT_CMDEXECFIFO_REG 0x1020\r | |
53 | #define SII3132_PORT_CMDERROR_REG 0x1024\r | |
54 | #define SII3132_PORT_ERRCOUNTDECODE 0x1040\r | |
55 | #define SII3132_PORT_ERRCOUNTCRC 0x1044\r | |
56 | #define SII3132_PORT_ERRCOUNTHANDSHAKE 0x1048\r | |
57 | #define SII3132_PORT_SLOTSTATUS_REG 0x1800\r | |
58 | #define SII3132_PORT_CMDACTIV_REG 0x1C00\r | |
59 | #define SII3132_PORT_SSTATUS_REG 0x1F04\r | |
60 | \r | |
61 | #define SII3132_PORT_CONTROL_RESET (1 << 0)\r | |
62 | #define SII3132_PORT_DEVICE_RESET (1 << 1)\r | |
63 | #define SII3132_PORT_CONTROL_INT (1 << 2)\r | |
64 | #define SII3132_PORT_CONTROL_32BITACTIVATION (1 << 10)\r | |
65 | \r | |
66 | #define SII3132_PORT_STATUS_PORTREADY 0x80000000\r | |
67 | \r | |
68 | #define SII3132_PORT_INT_CMDCOMPL (1 << 0)\r | |
69 | #define SII3132_PORT_INT_CMDERR (1 << 1)\r | |
70 | #define SII3132_PORT_INT_PORTRDY (1 << 2)\r | |
71 | \r | |
72 | #define SATA_SII3132_MAXPORT 2\r | |
73 | \r | |
74 | #define PRB_CTRL_ATA 0x0\r | |
75 | #define PRB_CTRL_PROT_OVERRIDE 0x1\r | |
76 | #define PRB_CTRL_RESTRANSMIT 0x2\r | |
77 | #define PRB_CTRL_EXT_CMD 0x4\r | |
78 | #define PRB_CTRL_RCV 0x8\r | |
79 | #define PRB_CTRL_PKT_READ 0x10\r | |
80 | #define PRB_CTRL_PKT_WRITE 0x20\r | |
81 | #define PRB_CTRL_INT_MASK 0x40\r | |
82 | #define PRB_CTRL_SRST 0x80\r | |
83 | \r | |
84 | #define PRB_PROT_PACKET 0x01\r | |
85 | #define PRB_PROT_LEGACY_QUEUE 0x02\r | |
86 | #define PRB_PROT_NATIVE_QUEUE 0x04\r | |
87 | #define PRB_PROT_READ 0x08\r | |
88 | #define PRB_PROT_WRITE 0x10\r | |
89 | #define PRB_PROT_TRANSPARENT 0x20\r | |
90 | \r | |
91 | #define SGE_XCF (1 << 28)\r | |
92 | #define SGE_DRD (1 << 29)\r | |
93 | #define SGE_LNK (1 << 30)\r | |
94 | #define SGE_TRM 0x80000000\r | |
95 | \r | |
96 | typedef struct _SATA_SI3132_SGE {\r | |
97 | UINT32 DataAddressLow;\r | |
98 | UINT32 DataAddressHigh;\r | |
99 | UINT32 DataCount;\r | |
100 | UINT32 Attributes;\r | |
101 | } SATA_SI3132_SGE;\r | |
102 | \r | |
103 | typedef struct _SATA_SI3132_FIS {\r | |
104 | UINT8 FisType;\r | |
105 | UINT8 Control;\r | |
106 | UINT8 Command;\r | |
107 | UINT8 Features;\r | |
108 | UINT8 Fis[5 * 4];\r | |
109 | } SATA_SI3132_FIS;\r | |
110 | \r | |
111 | typedef struct _SATA_SI3132_PRB {\r | |
112 | UINT16 Control;\r | |
113 | UINT16 ProtocolOverride;\r | |
114 | UINT32 RecTransCount;\r | |
115 | SATA_SI3132_FIS Fis;\r | |
116 | SATA_SI3132_SGE Sge[2];\r | |
117 | } SATA_SI3132_PRB;\r | |
118 | \r | |
119 | typedef struct _SATA_SI3132_DEVICE {\r | |
120 | LIST_ENTRY Link; // This attribute must be the first entry of this structure (to avoid pointer computation)\r | |
121 | UINTN Index;\r | |
122 | struct _SATA_SI3132_PORT *Port; //Parent Port\r | |
123 | UINT32 BlockSize;\r | |
124 | } SATA_SI3132_DEVICE;\r | |
125 | \r | |
126 | typedef struct _SATA_SI3132_PORT {\r | |
127 | UINTN Index;\r | |
128 | UINTN RegBase;\r | |
129 | struct _SATA_SI3132_INSTANCE *Instance;\r | |
130 | \r | |
131 | //TODO: Support Port multiplier\r | |
132 | LIST_ENTRY Devices;\r | |
133 | \r | |
134 | SATA_SI3132_PRB* HostPRB;\r | |
135 | EFI_PHYSICAL_ADDRESS PhysAddrHostPRB;\r | |
136 | VOID* PciAllocMappingPRB;\r | |
137 | } SATA_SI3132_PORT;\r | |
138 | \r | |
139 | typedef struct _SATA_SI3132_INSTANCE {\r | |
140 | UINTN Signature;\r | |
141 | \r | |
142 | SATA_SI3132_PORT Ports[SATA_SII3132_MAXPORT];\r | |
143 | \r | |
144 | EFI_ATA_PASS_THRU_PROTOCOL AtaPassThruProtocol;\r | |
145 | \r | |
146 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
147 | } SATA_SI3132_INSTANCE;\r | |
148 | \r | |
149 | #define SATA_SII3132_SIGNATURE SIGNATURE_32('s', 'i', '3', '2')\r | |
150 | #define INSTANCE_FROM_ATAPASSTHRU_THIS(a) CR(a, SATA_SI3132_INSTANCE, AtaPassThruProtocol, SATA_SII3132_SIGNATURE)\r | |
151 | \r | |
152 | #define SATA_GLOBAL_READ32(Offset, Value) PciIo->Mem.Read (PciIo, EfiPciIoWidthUint32, 0, Offset, 1, Value)\r | |
153 | #define SATA_GLOBAL_WRITE32(Offset, Value) { UINT32 Value32 = Value; PciIo->Mem.Write (PciIo, EfiPciIoWidthUint32, 0, Offset, 1, &Value32); }\r | |
154 | \r | |
155 | #define SATA_PORT_READ32(Offset, Value) PciIo->Mem.Read (PciIo, EfiPciIoWidthUint32, 1, Offset, 1, Value)\r | |
156 | #define SATA_PORT_WRITE32(Offset, Value) { UINT32 Value32 = Value; PciIo->Mem.Write (PciIo, EfiPciIoWidthUint32, 1, Offset, 1, &Value32); }\r | |
157 | \r | |
158 | #define SATA_TRACE(txt) DEBUG((EFI_D_VERBOSE, "ARM_SATA: " txt "\n"))\r | |
159 | \r | |
160 | extern EFI_COMPONENT_NAME_PROTOCOL gSataSiI3132ComponentName;\r | |
161 | extern EFI_COMPONENT_NAME2_PROTOCOL gSataSiI3132ComponentName2;\r | |
162 | \r | |
163 | /*\r | |
164 | * Component Name Protocol Functions\r | |
165 | */\r | |
166 | EFI_STATUS\r | |
167 | EFIAPI\r | |
168 | SataSiI3132ComponentNameGetDriverName (\r | |
169 | IN EFI_COMPONENT_NAME_PROTOCOL *This,\r | |
170 | IN CHAR8 *Language,\r | |
171 | OUT CHAR16 **DriverName\r | |
172 | );\r | |
173 | \r | |
174 | EFI_STATUS\r | |
175 | EFIAPI\r | |
176 | SataSiI3132ComponentNameGetControllerName (\r | |
177 | IN EFI_COMPONENT_NAME_PROTOCOL *This,\r | |
178 | IN EFI_HANDLE ControllerHandle,\r | |
179 | IN EFI_HANDLE ChildHandle OPTIONAL,\r | |
180 | IN CHAR8 *Language,\r | |
181 | OUT CHAR16 **ControllerName\r | |
182 | );\r | |
183 | \r | |
184 | EFI_STATUS SiI3132HwResetPort (SATA_SI3132_PORT *Port);\r | |
185 | \r | |
186 | /*\r | |
187 | * Driver Binding Protocol Functions\r | |
188 | */\r | |
189 | EFI_STATUS\r | |
190 | EFIAPI\r | |
191 | SataSiI3132DriverBindingSupported (\r | |
192 | IN EFI_DRIVER_BINDING_PROTOCOL *This,\r | |
193 | IN EFI_HANDLE Controller,\r | |
194 | IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r | |
195 | );\r | |
196 | \r | |
197 | EFI_STATUS\r | |
198 | EFIAPI\r | |
199 | SataSiI3132DriverBindingStart (\r | |
200 | IN EFI_DRIVER_BINDING_PROTOCOL *This,\r | |
201 | IN EFI_HANDLE Controller,\r | |
202 | IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r | |
203 | );\r | |
204 | \r | |
205 | EFI_STATUS\r | |
206 | EFIAPI\r | |
207 | SataSiI3132DriverBindingStop (\r | |
208 | IN EFI_DRIVER_BINDING_PROTOCOL *This,\r | |
209 | IN EFI_HANDLE Controller,\r | |
210 | IN UINTN NumberOfChildren,\r | |
211 | IN EFI_HANDLE *ChildHandleBuffer\r | |
212 | );\r | |
213 | \r | |
214 | EFI_STATUS SiI3132AtaPassThruCommand (\r | |
215 | IN SATA_SI3132_INSTANCE *pSataSiI3132Instance,\r | |
216 | IN SATA_SI3132_PORT *pSataPort,\r | |
217 | IN UINT16 PortMultiplierPort,\r | |
218 | IN OUT EFI_ATA_PASS_THRU_COMMAND_PACKET *Packet,\r | |
219 | IN EFI_EVENT Event OPTIONAL\r | |
220 | );\r | |
221 | \r | |
222 | /**\r | |
223 | * EFI ATA Pass Thru Protocol\r | |
224 | */\r | |
225 | EFI_STATUS SiI3132AtaPassThru (\r | |
226 | IN EFI_ATA_PASS_THRU_PROTOCOL *This,\r | |
227 | IN UINT16 Port,\r | |
228 | IN UINT16 PortMultiplierPort,\r | |
229 | IN OUT EFI_ATA_PASS_THRU_COMMAND_PACKET *Packet,\r | |
230 | IN EFI_EVENT Event OPTIONAL\r | |
231 | );\r | |
232 | \r | |
233 | EFI_STATUS SiI3132GetNextPort (\r | |
234 | IN EFI_ATA_PASS_THRU_PROTOCOL *This,\r | |
235 | IN OUT UINT16 *Port\r | |
236 | );\r | |
237 | \r | |
238 | EFI_STATUS SiI3132GetNextDevice (\r | |
239 | IN EFI_ATA_PASS_THRU_PROTOCOL *This,\r | |
240 | IN UINT16 Port,\r | |
241 | IN OUT UINT16 *PortMultiplierPort\r | |
242 | );\r | |
243 | \r | |
244 | EFI_STATUS SiI3132BuildDevicePath (\r | |
245 | IN EFI_ATA_PASS_THRU_PROTOCOL *This,\r | |
246 | IN UINT16 Port,\r | |
247 | IN UINT16 PortMultiplierPort,\r | |
248 | IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath\r | |
249 | );\r | |
250 | \r | |
251 | EFI_STATUS SiI3132GetDevice (\r | |
252 | IN EFI_ATA_PASS_THRU_PROTOCOL *This,\r | |
253 | IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r | |
254 | OUT UINT16 *Port,\r | |
255 | OUT UINT16 *PortMultiplierPort\r | |
256 | );\r | |
257 | \r | |
258 | EFI_STATUS SiI3132ResetPort (\r | |
259 | IN EFI_ATA_PASS_THRU_PROTOCOL *This,\r | |
260 | IN UINT16 Port\r | |
261 | );\r | |
262 | \r | |
263 | EFI_STATUS SiI3132ResetDevice (\r | |
264 | IN EFI_ATA_PASS_THRU_PROTOCOL *This,\r | |
265 | IN UINT16 Port,\r | |
266 | IN UINT16 PortMultiplierPort\r | |
267 | );\r | |
268 | \r | |
269 | #endif\r |