]>
Commit | Line | Data |
---|---|---|
2ef2b01e A |
1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2008-2009, Apple Inc. All rights reserved.\r | |
4 | \r | |
5 | All rights reserved. This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #include "CpuDxe.h"\r | |
16 | \r | |
17 | \r | |
18 | \r | |
19 | /**\r | |
20 | This function flushes the range of addresses from Start to Start+Length \r | |
21 | from the processor's data cache. If Start is not aligned to a cache line \r | |
22 | boundary, then the bytes before Start to the preceding cache line boundary \r | |
23 | are also flushed. If Start+Length is not aligned to a cache line boundary, \r | |
24 | then the bytes past Start+Length to the end of the next cache line boundary \r | |
25 | are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be \r | |
26 | supported. If the data cache is fully coherent with all DMA operations, then \r | |
27 | this function can just return EFI_SUCCESS. If the processor does not support \r | |
28 | flushing a range of the data cache, then the entire data cache can be flushed.\r | |
29 | \r | |
30 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
31 | @param Start The beginning physical address to flush from the processor's data\r | |
32 | cache.\r | |
33 | @param Length The number of bytes to flush from the processor's data cache. This\r | |
34 | function may flush more bytes than Length specifies depending upon\r | |
35 | the granularity of the flush operation that the processor supports.\r | |
36 | @param FlushType Specifies the type of flush operation to perform.\r | |
37 | \r | |
38 | @retval EFI_SUCCESS The address range from Start to Start+Length was flushed from\r | |
39 | the processor's data cache.\r | |
40 | @retval EFI_UNSUPPORTED The processor does not support the cache flush type specified\r | |
41 | by FlushType.\r | |
42 | @retval EFI_DEVICE_ERROR The address range from Start to Start+Length could not be flushed\r | |
43 | from the processor's data cache.\r | |
44 | \r | |
45 | **/\r | |
46 | EFI_STATUS\r | |
47 | EFIAPI\r | |
48 | CpuFlushCpuDataCache (\r | |
49 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
50 | IN EFI_PHYSICAL_ADDRESS Start,\r | |
51 | IN UINT64 Length,\r | |
52 | IN EFI_CPU_FLUSH_TYPE FlushType\r | |
53 | )\r | |
54 | {\r | |
55 | return FlushCpuDataCache (Start, Length, FlushType);\r | |
56 | }\r | |
57 | \r | |
58 | \r | |
59 | /**\r | |
60 | This function enables interrupt processing by the processor. \r | |
61 | \r | |
62 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
63 | \r | |
64 | @retval EFI_SUCCESS Interrupts are enabled on the processor.\r | |
65 | @retval EFI_DEVICE_ERROR Interrupts could not be enabled on the processor.\r | |
66 | \r | |
67 | **/\r | |
68 | EFI_STATUS\r | |
69 | EFIAPI\r | |
70 | CpuEnableInterrupt (\r | |
71 | IN EFI_CPU_ARCH_PROTOCOL *This\r | |
72 | )\r | |
73 | {\r | |
74 | EnableInterrupts (); \r | |
75 | return EFI_SUCCESS;\r | |
76 | }\r | |
77 | \r | |
78 | \r | |
79 | /**\r | |
80 | This function disables interrupt processing by the processor.\r | |
81 | \r | |
82 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
83 | \r | |
84 | @retval EFI_SUCCESS Interrupts are disabled on the processor.\r | |
85 | @retval EFI_DEVICE_ERROR Interrupts could not be disabled on the processor.\r | |
86 | \r | |
87 | **/\r | |
88 | EFI_STATUS\r | |
89 | EFIAPI\r | |
90 | CpuDisableInterrupt (\r | |
91 | IN EFI_CPU_ARCH_PROTOCOL *This\r | |
92 | )\r | |
93 | /*++\r | |
94 | \r | |
95 | Routine Description:\r | |
96 | Disables CPU interrupts.\r | |
97 | \r | |
98 | Arguments:\r | |
99 | This - Protocol instance structure\r | |
100 | \r | |
101 | Returns: \r | |
102 | EFI_SUCCESS - If interrupts were disabled in the CPU.\r | |
103 | EFI_DEVICE_ERROR - If interrupts could not be disabled on the CPU.\r | |
104 | \r | |
105 | --*/\r | |
106 | {\r | |
107 | DisableInterrupts ();\r | |
108 | return EFI_SUCCESS;\r | |
109 | }\r | |
110 | \r | |
111 | \r | |
112 | /**\r | |
113 | This function retrieves the processor's current interrupt state a returns it in \r | |
114 | State. If interrupts are currently enabled, then TRUE is returned. If interrupts \r | |
115 | are currently disabled, then FALSE is returned.\r | |
116 | \r | |
117 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
118 | @param State A pointer to the processor's current interrupt state. Set to TRUE if\r | |
119 | interrupts are enabled and FALSE if interrupts are disabled.\r | |
120 | \r | |
121 | @retval EFI_SUCCESS The processor's current interrupt state was returned in State.\r | |
122 | @retval EFI_INVALID_PARAMETER State is NULL.\r | |
123 | \r | |
124 | **/\r | |
125 | EFI_STATUS\r | |
126 | EFIAPI\r | |
127 | CpuGetInterruptState (\r | |
128 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
129 | OUT BOOLEAN *State\r | |
130 | )\r | |
131 | {\r | |
132 | if (State == NULL) {\r | |
133 | return EFI_INVALID_PARAMETER;\r | |
134 | }\r | |
135 | \r | |
136 | *State = GetInterruptState ();\r | |
137 | return EFI_SUCCESS;\r | |
138 | }\r | |
139 | \r | |
140 | \r | |
141 | /**\r | |
142 | This function generates an INIT on the processor. If this function succeeds, then the\r | |
143 | processor will be reset, and control will not be returned to the caller. If InitType is \r | |
144 | not supported by this processor, or the processor cannot programmatically generate an \r | |
145 | INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error \r | |
146 | occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned.\r | |
147 | \r | |
148 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
149 | @param InitType The type of processor INIT to perform.\r | |
150 | \r | |
151 | @retval EFI_SUCCESS The processor INIT was performed. This return code should never be seen.\r | |
152 | @retval EFI_UNSUPPORTED The processor INIT operation specified by InitType is not supported\r | |
153 | by this processor.\r | |
154 | @retval EFI_DEVICE_ERROR The processor INIT failed.\r | |
155 | \r | |
156 | **/\r | |
157 | EFI_STATUS\r | |
158 | EFIAPI\r | |
159 | CpuInit (\r | |
160 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
161 | IN EFI_CPU_INIT_TYPE InitType\r | |
162 | )\r | |
163 | {\r | |
164 | return EFI_UNSUPPORTED;\r | |
165 | }\r | |
166 | \r | |
167 | \r | |
168 | /**\r | |
169 | This function registers and enables the handler specified by InterruptHandler for a processor \r | |
170 | interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the \r | |
171 | handler for the processor interrupt or exception type specified by InterruptType is uninstalled. \r | |
172 | The installed handler is called once for each processor interrupt or exception.\r | |
173 | \r | |
174 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
175 | @param InterruptType A pointer to the processor's current interrupt state. Set to TRUE if interrupts\r | |
176 | are enabled and FALSE if interrupts are disabled.\r | |
177 | @param InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called\r | |
178 | when a processor interrupt occurs. If this parameter is NULL, then the handler\r | |
179 | will be uninstalled.\r | |
180 | \r | |
181 | @retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled.\r | |
182 | @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was\r | |
183 | previously installed.\r | |
184 | @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not\r | |
185 | previously installed.\r | |
186 | @retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported.\r | |
187 | \r | |
188 | **/\r | |
189 | EFI_STATUS\r | |
190 | EFIAPI\r | |
191 | CpuRegisterInterruptHandler (\r | |
192 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
193 | IN EFI_EXCEPTION_TYPE InterruptType,\r | |
194 | IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r | |
195 | )\r | |
196 | {\r | |
197 | return RegisterInterruptHandler (InterruptType, InterruptHandler);\r | |
198 | }\r | |
199 | \r | |
200 | \r | |
201 | /**\r | |
202 | This function reads the processor timer specified by TimerIndex and returns it in TimerValue.\r | |
203 | \r | |
204 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
205 | @param TimerIndex Specifies which processor timer is to be returned in TimerValue. This parameter\r | |
206 | must be between 0 and NumberOfTimers-1.\r | |
207 | @param TimerValue Pointer to the returned timer value.\r | |
208 | @param TimerPeriod A pointer to the amount of time that passes in femtoseconds for each increment\r | |
209 | of TimerValue.\r | |
210 | \r | |
211 | @retval EFI_SUCCESS The processor timer value specified by TimerIndex was returned in TimerValue.\r | |
212 | @retval EFI_DEVICE_ERROR An error occurred attempting to read one of the processor's timers.\r | |
213 | @retval EFI_INVALID_PARAMETER TimerValue is NULL or TimerIndex is not valid.\r | |
214 | @retval EFI_UNSUPPORTED The processor does not have any readable timers.\r | |
215 | \r | |
216 | **/\r | |
217 | EFI_STATUS\r | |
218 | EFIAPI\r | |
219 | CpuGetTimerValue (\r | |
220 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
221 | IN UINT32 TimerIndex,\r | |
222 | OUT UINT64 *TimerValue,\r | |
223 | OUT UINT64 *TimerPeriod OPTIONAL\r | |
224 | )\r | |
225 | { \r | |
226 | return GetTimerValue (TimerIndex, TimerValue, TimerPeriod);\r | |
227 | }\r | |
228 | \r | |
229 | \r | |
230 | /**\r | |
231 | This function modifies the attributes for the memory region specified by BaseAddress and\r | |
232 | Length from their current attributes to the attributes specified by Attributes.\r | |
233 | \r | |
234 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
235 | @param BaseAddress The physical address that is the start address of a memory region.\r | |
236 | @param Length The size in bytes of the memory region.\r | |
237 | @param Attributes The bit mask of attributes to set for the memory region.\r | |
238 | \r | |
239 | @retval EFI_SUCCESS The attributes were set for the memory region.\r | |
240 | @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r | |
241 | BaseAddress and Length cannot be modified.\r | |
242 | @retval EFI_INVALID_PARAMETER Length is zero.\r | |
243 | @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r | |
244 | the memory resource range.\r | |
245 | @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r | |
246 | resource range specified by BaseAddress and Length.\r | |
247 | The bit mask of attributes is not support for the memory resource\r | |
248 | range specified by BaseAddress and Length.\r | |
249 | \r | |
250 | **/\r | |
251 | EFI_STATUS\r | |
252 | EFIAPI\r | |
253 | CpuSetMemoryAttributes (\r | |
254 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
255 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
256 | IN UINT64 Length,\r | |
257 | IN UINT64 Attributes\r | |
258 | )\r | |
259 | {\r | |
260 | //\r | |
261 | // This is used to set cachability via the MMU on ARM\r | |
262 | //\r | |
263 | // This more about optimization and we can usually run fine if the default\r | |
264 | // settings for cachability are good.\r | |
265 | //\r | |
266 | return EFI_UNSUPPORTED;\r | |
267 | }\r | |
268 | \r | |
269 | \r | |
270 | \r | |
271 | \r | |
272 | //\r | |
273 | // Globals used to initialize the protocol\r | |
274 | //\r | |
275 | EFI_HANDLE mCpuHandle = NULL;\r | |
276 | EFI_CPU_ARCH_PROTOCOL mCpu = {\r | |
277 | CpuFlushCpuDataCache,\r | |
278 | CpuEnableInterrupt,\r | |
279 | CpuDisableInterrupt,\r | |
280 | CpuGetInterruptState,\r | |
281 | CpuInit,\r | |
282 | CpuRegisterInterruptHandler,\r | |
283 | CpuGetTimerValue,\r | |
284 | CpuSetMemoryAttributes,\r | |
285 | 0, // NumberOfTimers\r | |
286 | 4, // DmaBufferAlignment\r | |
287 | };\r | |
288 | \r | |
289 | \r | |
290 | /**\r | |
291 | Initialize the state information for the CPU Architectural Protocol\r | |
292 | \r | |
293 | @param ImageHandle of the loaded driver\r | |
294 | @param SystemTable Pointer to the System Table\r | |
295 | \r | |
296 | @retval EFI_SUCCESS Protocol registered\r | |
297 | @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure\r | |
298 | @retval EFI_DEVICE_ERROR Hardware problems\r | |
299 | \r | |
300 | **/\r | |
301 | EFI_STATUS\r | |
302 | CpuDxeInitialize (\r | |
303 | IN EFI_HANDLE ImageHandle,\r | |
304 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
305 | )\r | |
306 | {\r | |
307 | EFI_STATUS Status;\r | |
308 | \r | |
309 | InitializeExceptions (&mCpu);\r | |
310 | \r | |
311 | //\r | |
312 | // Install CPU Architectural Protocol and the thunk protocol\r | |
313 | //\r | |
314 | Status = gBS->InstallMultipleProtocolInterfaces (\r | |
315 | &mCpuHandle,\r | |
316 | &gEfiCpuArchProtocolGuid, &mCpu,\r | |
317 | NULL\r | |
318 | );\r | |
319 | ASSERT_EFI_ERROR (Status);\r | |
320 | \r | |
321 | return Status;\r | |
322 | }\r | |
323 | \r |