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a33a2f62 JY |
1 | /** @file\r |
2 | Intel FSP API definition from Intel Firmware Support Package External\r | |
3b17b245 | 3 | Architecture Specification v1.1, April 2015, revision 001.\r |
a33a2f62 | 4 | \r |
d5fb1edf | 5 | Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r |
a33a2f62 JY |
6 | This program and the accompanying materials\r |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php.\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #ifndef _FSP_API_H_\r | |
17 | #define _FSP_API_H_\r | |
18 | \r | |
d5fb1edf | 19 | #define FSP_STATUS EFI_STATUS\r |
a33a2f62 JY |
20 | #define FSPAPI EFIAPI\r |
21 | \r | |
22 | /**\r | |
23 | FSP Init continuation function prototype.\r | |
24 | Control will be returned to this callback function after FspInit API call.\r | |
25 | \r | |
26 | @param[in] Status Status of the FSP INIT API.\r | |
27 | @param[in] HobBufferPtr Pointer to the HOB data structure defined in the PI specification.\r | |
28 | **/\r | |
29 | typedef\r | |
30 | VOID\r | |
31 | (* CONTINUATION_PROC) (\r | |
d5fb1edf | 32 | IN EFI_STATUS Status,\r |
a33a2f62 JY |
33 | IN VOID *HobListPtr\r |
34 | );\r | |
35 | \r | |
36 | #pragma pack(1)\r | |
37 | \r | |
38 | typedef struct {\r | |
39 | ///\r | |
40 | /// Base address of the microcode region.\r | |
41 | ///\r | |
42 | UINT32 MicrocodeRegionBase;\r | |
43 | ///\r | |
44 | /// Length of the microcode region.\r | |
45 | ///\r | |
46 | UINT32 MicrocodeRegionLength;\r | |
47 | ///\r | |
48 | /// Base address of the cacheable flash region.\r | |
49 | ///\r | |
50 | UINT32 CodeRegionBase;\r | |
51 | ///\r | |
52 | /// Length of the cacheable flash region.\r | |
53 | ///\r | |
54 | UINT32 CodeRegionLength;\r | |
55 | } FSP_TEMP_RAM_INIT_PARAMS;\r | |
56 | \r | |
57 | typedef struct {\r | |
58 | ///\r | |
59 | /// Non-volatile storage buffer pointer.\r | |
60 | ///\r | |
61 | VOID *NvsBufferPtr;\r | |
62 | ///\r | |
63 | /// Runtime buffer pointer\r | |
64 | ///\r | |
65 | VOID *RtBufferPtr;\r | |
66 | ///\r | |
67 | /// Continuation function address\r | |
68 | ///\r | |
69 | CONTINUATION_PROC ContinuationFunc;\r | |
70 | } FSP_INIT_PARAMS;\r | |
71 | \r | |
72 | typedef struct {\r | |
73 | ///\r | |
74 | /// Stack top pointer used by the bootloader.\r | |
75 | /// The new stack frame will be set up at this location after FspInit API call.\r | |
76 | ///\r | |
77 | UINT32 *StackTop;\r | |
78 | ///\r | |
79 | /// Current system boot mode.\r | |
80 | ///\r | |
81 | UINT32 BootMode;\r | |
82 | ///\r | |
83 | /// User platform configuraiton data region pointer.\r | |
84 | ///\r | |
85 | VOID *UpdDataRgnPtr;\r | |
9da59186 JY |
86 | //\r |
87 | // Below field is added in FSP EAS v1.1\r | |
88 | //\r | |
89 | ///\r | |
90 | /// The size of memory to be reserved below the top of low usable memory (TOLUM)\r | |
91 | /// for BootLoader usage. This is optional and value can be zero. If non-zero, the\r | |
92 | /// size must be a multiple of 4KB.\r | |
93 | ///\r | |
94 | UINT32 BootLoaderTolumSize;\r | |
a33a2f62 JY |
95 | ///\r |
96 | /// Reserved\r | |
97 | ///\r | |
9da59186 | 98 | UINT32 Reserved[6];\r |
a33a2f62 JY |
99 | } FSP_INIT_RT_COMMON_BUFFER;\r |
100 | \r | |
101 | typedef enum {\r | |
102 | ///\r | |
103 | /// Notification code for post PCI enuermation\r | |
104 | ///\r | |
105 | EnumInitPhaseAfterPciEnumeration = 0x20,\r | |
106 | ///\r | |
107 | /// Notification code before transfering control to the payload\r | |
108 | ///\r | |
109 | EnumInitPhaseReadyToBoot = 0x40\r | |
110 | } FSP_INIT_PHASE;\r | |
111 | \r | |
112 | typedef struct {\r | |
113 | ///\r | |
114 | /// Notification phase used for NotifyPhase API\r | |
115 | ///\r | |
116 | FSP_INIT_PHASE Phase;\r | |
117 | } NOTIFY_PHASE_PARAMS;\r | |
118 | \r | |
d5fb1edf JY |
119 | typedef struct {\r |
120 | ///\r | |
121 | /// Non-volatile storage buffer pointer.\r | |
122 | ///\r | |
123 | VOID *NvsBufferPtr;\r | |
124 | ///\r | |
125 | /// Runtime buffer pointer\r | |
126 | ///\r | |
127 | VOID *RtBufferPtr;\r | |
128 | ///\r | |
129 | /// Pointer to the HOB data structure defined in the PI specification\r | |
130 | ///\r | |
131 | VOID **HobListPtr;\r | |
132 | } FSP_MEMORY_INIT_PARAMS;\r | |
133 | \r | |
a33a2f62 JY |
134 | #pragma pack()\r |
135 | \r | |
136 | /**\r | |
137 | This FSP API is called soon after coming out of reset and before memory and stack is\r | |
138 | available. This FSP API will load the microcode update, enable code caching for the\r | |
139 | region specified by the boot loader and also setup a temporary stack to be used until\r | |
140 | main memory is initialized.\r | |
141 | \r | |
142 | A hardcoded stack can be set up with the following values, and the "esp" register\r | |
143 | initialized to point to this hardcoded stack.\r | |
144 | 1. The return address where the FSP will return control after setting up a temporary\r | |
145 | stack.\r | |
146 | 2. A pointer to the input parameter structure\r | |
147 | \r | |
148 | However, since the stack is in ROM and not writeable, this FSP API cannot be called\r | |
149 | using the "call" instruction, but needs to be jumped to.\r | |
150 | \r | |
151 | @param[in] TempRaminitParamPtr Address pointer to the FSP_TEMP_RAM_INIT_PARAMS structure.\r | |
152 | \r | |
d5fb1edf JY |
153 | @retval EFI_SUCCESS Temp RAM was initialized successfully.\r |
154 | @retval EFI_INVALID_PARAMETER Input parameters are invalid..\r | |
155 | @retval EFI_NOT_FOUND No valid microcode was found in the microcode region.\r | |
156 | @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r | |
157 | @retval EFI_DEVICE_ERROR Temp RAM initialization failed.\r | |
a33a2f62 JY |
158 | \r |
159 | If this function is successful, the FSP initializes the ECX and EDX registers to point to\r | |
160 | a temporary but writeable memory range available to the boot loader and returns with\r | |
161 | FSP_SUCCESS in register EAX. Register ECX points to the start of this temporary\r | |
162 | memory range and EDX points to the end of the range. Boot loader is free to use the\r | |
163 | whole range described. Typically the boot loader can reload the ESP register to point\r | |
164 | to the end of this returned range so that it can be used as a standard stack.\r | |
165 | **/\r | |
166 | typedef\r | |
d5fb1edf JY |
167 | EFI_STATUS\r |
168 | (EFIAPI *FSP_TEMP_RAM_INIT) (\r | |
a33a2f62 JY |
169 | IN FSP_TEMP_RAM_INIT_PARAMS *FspTempRamInitPtr\r |
170 | );\r | |
171 | \r | |
172 | /**\r | |
173 | This FSP API is called after TempRamInitEntry. This FSP API initializes the memory,\r | |
174 | the CPU and the chipset to enable normal operation of these devices. This FSP API\r | |
175 | accepts a pointer to a data structure that will be platform dependent and defined for\r | |
176 | each FSP binary. This will be documented in the Integration Guide for each FSP\r | |
177 | release.\r | |
178 | The boot loader provides a continuation function as a parameter when calling FspInit.\r | |
179 | After FspInit completes its execution, it does not return to the boot loader from where\r | |
180 | it was called but instead returns control to the boot loader by calling the continuation\r | |
181 | function which is passed to FspInit as an argument.\r | |
182 | \r | |
183 | @param[in] FspInitParamPtr Address pointer to the FSP_INIT_PARAMS structure.\r | |
184 | \r | |
d5fb1edf JY |
185 | @retval EFI_SUCCESS FSP execution environment was initialized successfully.\r |
186 | @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r | |
187 | @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r | |
188 | @retval EFI_DEVICE_ERROR FSP initialization failed.\r | |
a33a2f62 JY |
189 | **/\r |
190 | typedef\r | |
d5fb1edf JY |
191 | EFI_STATUS\r |
192 | (EFIAPI *FSP_INIT) (\r | |
a33a2f62 JY |
193 | IN OUT FSP_INIT_PARAMS *FspInitParamPtr\r |
194 | );\r | |
195 | \r | |
d5fb1edf JY |
196 | #define FSP_FSP_INIT FSP_INIT\r |
197 | \r | |
a33a2f62 JY |
198 | /**\r |
199 | This FSP API is used to notify the FSP about the different phases in the boot process.\r | |
200 | This allows the FSP to take appropriate actions as needed during different initialization\r | |
201 | phases. The phases will be platform dependent and will be documented with the FSP\r | |
202 | release. The current FSP supports two notify phases:\r | |
203 | Post PCI enumeration\r | |
204 | Ready To Boot\r | |
205 | \r | |
206 | @param[in] NotifyPhaseParamPtr Address pointer to the NOTIFY_PHASE_PRAMS\r | |
207 | \r | |
d5fb1edf JY |
208 | @retval EFI_SUCCESS The notification was handled successfully.\r |
209 | @retval EFI_UNSUPPORTED The notification was not called in the proper order.\r | |
210 | @retval EFI_INVALID_PARAMETER The notification code is invalid.\r | |
a33a2f62 JY |
211 | **/\r |
212 | typedef\r | |
d5fb1edf JY |
213 | EFI_STATUS\r |
214 | (EFIAPI *FSP_NOTIFY_PHASE) (\r | |
a33a2f62 JY |
215 | IN NOTIFY_PHASE_PARAMS *NotifyPhaseParamPtr\r |
216 | );\r | |
217 | \r | |
d5fb1edf JY |
218 | /**\r |
219 | This FSP API is called after TempRamInit and initializes the memory.\r | |
220 | This FSP API accepts a pointer to a data structure that will be platform dependent\r | |
221 | and defined for each FSP binary. This will be documented in Integration guide with\r | |
222 | each FSP release.\r | |
223 | After FspMemInit completes its execution, it passes the pointer to the HobList and\r | |
9da59186 | 224 | returns to the boot loader from where it was called. BootLoader is responsible to \r |
6ca9135a | 225 | migrate it's stack and data to Memory.\r |
d5fb1edf JY |
226 | FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to\r |
227 | complete the silicon initialization and provides bootloader an opportunity to get\r | |
228 | control after system memory is available and before the temporary RAM is torn down.\r | |
229 | These APIs are mutually exclusive to the FspInit API.\r | |
230 | \r | |
231 | @param[in][out] FspMemoryInitParamPtr Address pointer to the FSP_MEMORY_INIT_PARAMS\r | |
232 | structure.\r | |
233 | \r | |
234 | @retval EFI_SUCCESS FSP execution environment was initialized successfully.\r | |
235 | @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r | |
236 | @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r | |
237 | @retval EFI_DEVICE_ERROR FSP initialization failed.\r | |
238 | **/\r | |
239 | typedef\r | |
240 | EFI_STATUS\r | |
241 | (EFIAPI *FSP_MEMORY_INIT) (\r | |
242 | IN OUT FSP_MEMORY_INIT_PARAMS *FspMemoryInitParamPtr\r | |
243 | );\r | |
244 | \r | |
245 | \r | |
246 | /**\r | |
247 | This FSP API is called after FspMemoryInit API. This FSP API tears down the temporary\r | |
248 | memory setup by TempRamInit API. This FSP API accepts a pointer to a data structure\r | |
249 | that will be platform dependent and defined for each FSP binary. This will be\r | |
250 | documented in Integration Guide.\r | |
251 | FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to\r | |
252 | complete the silicon initialization and provides bootloader an opportunity to get\r | |
253 | control after system memory is available and before the temporary RAM is torn down.\r | |
254 | These APIs are mutually exclusive to the FspInit API.\r | |
255 | \r | |
256 | @param[in][out] TempRamExitParamPtr Pointer to the Temp Ram Exit parameters structure.\r | |
257 | This structure is normally defined in the Integration Guide.\r | |
258 | And if it is not defined in the Integration Guide, pass NULL.\r | |
259 | \r | |
260 | @retval EFI_SUCCESS FSP execution environment was initialized successfully.\r | |
261 | @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r | |
262 | @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r | |
263 | @retval EFI_DEVICE_ERROR FSP initialization failed.\r | |
264 | **/\r | |
265 | typedef\r | |
266 | EFI_STATUS\r | |
267 | (EFIAPI *FSP_TEMP_RAM_EXIT) (\r | |
268 | IN OUT VOID *TempRamExitParamPtr\r | |
269 | );\r | |
270 | \r | |
271 | \r | |
272 | /**\r | |
273 | This FSP API is called after TempRamExit API.\r | |
274 | FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to complete the\r | |
275 | silicon initialization.\r | |
276 | These APIs are mutually exclusive to the FspInit API.\r | |
277 | \r | |
278 | @param[in][out] FspSiliconInitParamPtr Pointer to the Silicon Init parameters structure.\r | |
279 | This structure is normally defined in the Integration Guide.\r | |
280 | And if it is not defined in the Integration Guide, pass NULL.\r | |
281 | \r | |
282 | @retval EFI_SUCCESS FSP execution environment was initialized successfully.\r | |
283 | @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r | |
284 | @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r | |
285 | @retval EFI_DEVICE_ERROR FSP initialization failed.\r | |
286 | **/\r | |
287 | typedef\r | |
288 | EFI_STATUS\r | |
289 | (EFIAPI *FSP_SILICON_INIT) (\r | |
290 | IN OUT VOID *FspSiliconInitParamPtr\r | |
291 | );\r | |
292 | \r | |
a33a2f62 | 293 | ///\r |
d5fb1edf JY |
294 | /// FSP API Return Status Code for backward compatibility with v1.0\r |
295 | ///@{\r | |
296 | #define FSP_SUCCESS EFI_SUCCESS\r | |
297 | #define FSP_INVALID_PARAMETER EFI_INVALID_PARAMETER\r | |
298 | #define FSP_UNSUPPORTED EFI_UNSUPPORTED\r | |
299 | #define FSP_NOT_READY EFI_NOT_READY\r | |
300 | #define FSP_DEVICE_ERROR EFI_DEVICE_ERROR\r | |
301 | #define FSP_OUT_OF_RESOURCES EFI_OUT_OF_RESOURCES\r | |
302 | #define FSP_VOLUME_CORRUPTED EFI_VOLUME_CORRUPTED\r | |
303 | #define FSP_NOT_FOUND EFI_NOT_FOUND\r | |
304 | #define FSP_TIMEOUT EFI_TIMEOUT\r | |
305 | #define FSP_ABORTED EFI_ABORTED\r | |
306 | #define FSP_INCOMPATIBLE_VERSION EFI_INCOMPATIBLE_VERSION\r | |
307 | #define FSP_SECURITY_VIOLATION EFI_SECURITY_VIOLATION\r | |
308 | #define FSP_CRC_ERROR EFI_CRC_ERROR\r | |
309 | ///@}\r | |
a33a2f62 JY |
310 | \r |
311 | #endif\r |