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a33a2f62 JY |
1 | /** @file\r |
2 | Provide FSP API related function.\r | |
3 | \r | |
bcee1b9f | 4 | Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>\r |
a33a2f62 JY |
5 | This program and the accompanying materials\r |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php.\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #include <PiPei.h>\r | |
16 | \r | |
17 | #include <Guid/FspHeaderFile.h>\r | |
18 | \r | |
19 | #include <Library/FspApiLib.h>\r | |
d8043ce9 | 20 | #include <Library/BaseLib.h>\r |
a33a2f62 JY |
21 | #include <Library/BaseMemoryLib.h>\r |
22 | \r | |
23 | /**\r | |
24 | Wrapper for a thunk to transition from long mode to compatibility mode to execute 32-bit code and then transit back to\r | |
25 | long mode.\r | |
26 | \r | |
27 | @param[in] Function The 32bit code entry to be executed.\r | |
28 | @param[in] Param1 The first parameter to pass to 32bit code.\r | |
29 | \r | |
d8043ce9 | 30 | @return EFI_STATUS.\r |
a33a2f62 | 31 | **/\r |
d8043ce9 | 32 | EFI_STATUS\r |
a33a2f62 JY |
33 | Execute32BitCode (\r |
34 | IN UINT64 Function,\r | |
35 | IN UINT64 Param1\r | |
36 | );\r | |
37 | \r | |
38 | /**\r | |
39 | Find FSP header pointer.\r | |
40 | \r | |
41 | @param[in] FlashFvFspBase Flash address of FSP FV.\r | |
42 | \r | |
43 | @return FSP header pointer.\r | |
44 | **/\r | |
45 | FSP_INFO_HEADER *\r | |
46 | EFIAPI\r | |
47 | FspFindFspHeader (\r | |
48 | IN EFI_PHYSICAL_ADDRESS FlashFvFspBase\r | |
49 | )\r | |
50 | {\r | |
51 | UINT8 *CheckPointer;\r | |
52 | \r | |
53 | CheckPointer = (UINT8 *) (UINTN) FlashFvFspBase;\r | |
54 | \r | |
55 | if (((EFI_FIRMWARE_VOLUME_HEADER *)CheckPointer)->Signature != EFI_FVH_SIGNATURE) {\r | |
56 | return NULL;\r | |
57 | }\r | |
58 | \r | |
59 | if (((EFI_FIRMWARE_VOLUME_HEADER *)CheckPointer)->ExtHeaderOffset != 0) {\r | |
60 | CheckPointer = CheckPointer + ((EFI_FIRMWARE_VOLUME_HEADER *)CheckPointer)->ExtHeaderOffset;\r | |
61 | CheckPointer = CheckPointer + ((EFI_FIRMWARE_VOLUME_EXT_HEADER *)CheckPointer)->ExtHeaderSize;\r | |
62 | CheckPointer = (UINT8 *) ALIGN_POINTER (CheckPointer, 8);\r | |
63 | } else {\r | |
64 | CheckPointer = CheckPointer + ((EFI_FIRMWARE_VOLUME_HEADER *)CheckPointer)->HeaderLength;\r | |
65 | }\r | |
66 | \r | |
67 | if (!CompareGuid (&((EFI_FFS_FILE_HEADER *)CheckPointer)->Name, &gFspHeaderFileGuid)) {\r | |
68 | return NULL;\r | |
69 | }\r | |
70 | \r | |
71 | CheckPointer = CheckPointer + sizeof (EFI_FFS_FILE_HEADER);\r | |
72 | \r | |
73 | if (((EFI_RAW_SECTION *)CheckPointer)->Type != EFI_SECTION_RAW) {\r | |
74 | return NULL;\r | |
75 | }\r | |
76 | \r | |
77 | CheckPointer = CheckPointer + sizeof (EFI_RAW_SECTION);\r | |
78 | \r | |
79 | return (FSP_INFO_HEADER *)CheckPointer;\r | |
80 | }\r | |
81 | \r | |
82 | /**\r | |
83 | Call FSP API - FspInit.\r | |
84 | \r | |
85 | @param[in] FspHeader FSP header pointer.\r | |
86 | @param[in] FspInitParams Address pointer to the FSP_INIT_PARAMS structure.\r | |
87 | \r | |
d8043ce9 | 88 | @return EFI status returned by FspInit API.\r |
a33a2f62 | 89 | **/\r |
d8043ce9 | 90 | EFI_STATUS\r |
a33a2f62 JY |
91 | EFIAPI\r |
92 | CallFspInit (\r | |
93 | IN FSP_INFO_HEADER *FspHeader,\r | |
94 | IN FSP_INIT_PARAMS *FspInitParams\r | |
95 | )\r | |
96 | {\r | |
d8043ce9 JY |
97 | FSP_INIT FspInitApi;\r |
98 | EFI_STATUS Status;\r | |
99 | BOOLEAN InterruptState;\r | |
a33a2f62 | 100 | \r |
bcee1b9f | 101 | FspInitApi = (FSP_INIT)((UINTN)FspHeader->ImageBase + FspHeader->FspInitEntryOffset);\r |
d8043ce9 JY |
102 | InterruptState = SaveAndDisableInterrupts ();\r |
103 | Status = Execute32BitCode ((UINTN)FspInitApi, (UINTN)FspInitParams);\r | |
104 | SetInterruptState (InterruptState);\r | |
a33a2f62 | 105 | \r |
d8043ce9 | 106 | return Status;\r |
a33a2f62 JY |
107 | }\r |
108 | \r | |
109 | /**\r | |
110 | Call FSP API - FspNotifyPhase.\r | |
111 | \r | |
112 | @param[in] FspHeader FSP header pointer.\r | |
113 | @param[in] NotifyPhaseParams Address pointer to the NOTIFY_PHASE_PARAMS structure.\r | |
114 | \r | |
d8043ce9 | 115 | @return EFI status returned by FspNotifyPhase API.\r |
a33a2f62 | 116 | **/\r |
d8043ce9 | 117 | EFI_STATUS\r |
a33a2f62 JY |
118 | EFIAPI\r |
119 | CallFspNotifyPhase (\r | |
120 | IN FSP_INFO_HEADER *FspHeader,\r | |
121 | IN NOTIFY_PHASE_PARAMS *NotifyPhaseParams\r | |
122 | )\r | |
123 | {\r | |
8e89d9ce | 124 | FSP_NOTIFY_PHASE NotifyPhaseApi;\r |
d8043ce9 JY |
125 | EFI_STATUS Status;\r |
126 | BOOLEAN InterruptState;\r | |
a33a2f62 | 127 | \r |
bcee1b9f | 128 | NotifyPhaseApi = (FSP_NOTIFY_PHASE)((UINTN)FspHeader->ImageBase + FspHeader->NotifyPhaseEntryOffset);\r |
d8043ce9 JY |
129 | InterruptState = SaveAndDisableInterrupts ();\r |
130 | Status = Execute32BitCode ((UINTN)NotifyPhaseApi, (UINTN)NotifyPhaseParams);\r | |
131 | SetInterruptState (InterruptState);\r | |
a33a2f62 | 132 | \r |
d8043ce9 JY |
133 | return Status;\r |
134 | }\r | |
135 | \r | |
136 | /**\r | |
137 | Call FSP API - FspMemoryInit.\r | |
138 | \r | |
139 | @param[in] FspHeader FSP header pointer.\r | |
140 | @param[in,out] FspMemoryInitParams Address pointer to the FSP_MEMORY_INIT_PARAMS structure.\r | |
141 | \r | |
142 | @return EFI status returned by FspMemoryInit API.\r | |
143 | **/\r | |
144 | EFI_STATUS\r | |
145 | EFIAPI\r | |
146 | CallFspMemoryInit (\r | |
147 | IN FSP_INFO_HEADER *FspHeader,\r | |
148 | IN OUT FSP_MEMORY_INIT_PARAMS *FspMemoryInitParams\r | |
149 | )\r | |
150 | {\r | |
151 | FSP_MEMORY_INIT FspMemoryInitApi;\r | |
152 | EFI_STATUS Status;\r | |
153 | BOOLEAN InterruptState;\r | |
154 | \r | |
bcee1b9f | 155 | FspMemoryInitApi = (FSP_MEMORY_INIT)((UINTN)FspHeader->ImageBase + FspHeader->FspMemoryInitEntryOffset);\r |
d8043ce9 JY |
156 | InterruptState = SaveAndDisableInterrupts ();\r |
157 | Status = Execute32BitCode ((UINTN)FspMemoryInitApi, (UINTN)FspMemoryInitParams);\r | |
158 | SetInterruptState (InterruptState);\r | |
159 | \r | |
160 | return Status;\r | |
161 | }\r | |
162 | \r | |
163 | /**\r | |
164 | Call FSP API - TempRamExit.\r | |
165 | \r | |
166 | @param[in] FspHeader FSP header pointer.\r | |
167 | @param[in,out] TempRamExitParam Address pointer to the TempRamExit parameters structure.\r | |
168 | \r | |
169 | @return EFI status returned by TempRamExit API.\r | |
170 | **/\r | |
171 | EFI_STATUS\r | |
172 | EFIAPI\r | |
173 | CallTempRamExit (\r | |
174 | IN FSP_INFO_HEADER *FspHeader,\r | |
175 | IN OUT VOID *TempRamExitParam\r | |
176 | )\r | |
177 | {\r | |
178 | FSP_TEMP_RAM_EXIT TempRamExitApi;\r | |
179 | EFI_STATUS Status;\r | |
180 | BOOLEAN InterruptState;\r | |
181 | \r | |
bcee1b9f | 182 | TempRamExitApi = (FSP_TEMP_RAM_EXIT)((UINTN)FspHeader->ImageBase + FspHeader->TempRamExitEntryOffset);\r |
d8043ce9 JY |
183 | InterruptState = SaveAndDisableInterrupts ();\r |
184 | Status = Execute32BitCode ((UINTN)TempRamExitApi, (UINTN)TempRamExitParam);\r | |
185 | SetInterruptState (InterruptState);\r | |
186 | \r | |
187 | return Status;\r | |
188 | }\r | |
189 | \r | |
190 | /**\r | |
191 | Call FSP API - FspSiliconInit.\r | |
192 | \r | |
193 | @param[in] FspHeader FSP header pointer.\r | |
194 | @param[in,out] FspSiliconInitParam Address pointer to the Silicon Init parameters structure.\r | |
195 | \r | |
196 | @return EFI status returned by FspSiliconInit API.\r | |
197 | **/\r | |
198 | EFI_STATUS\r | |
199 | EFIAPI\r | |
200 | CallFspSiliconInit (\r | |
201 | IN FSP_INFO_HEADER *FspHeader,\r | |
202 | IN OUT VOID *FspSiliconInitParam\r | |
203 | )\r | |
204 | {\r | |
205 | FSP_SILICON_INIT FspSiliconInitApi;\r | |
206 | EFI_STATUS Status;\r | |
207 | BOOLEAN InterruptState;\r | |
208 | \r | |
bcee1b9f | 209 | FspSiliconInitApi = (FSP_SILICON_INIT)((UINTN)FspHeader->ImageBase + FspHeader->FspSiliconInitEntryOffset);\r |
d8043ce9 JY |
210 | InterruptState = SaveAndDisableInterrupts ();\r |
211 | Status = Execute32BitCode ((UINTN)FspSiliconInitApi, (UINTN)FspSiliconInitParam);\r | |
212 | SetInterruptState (InterruptState);\r | |
213 | \r | |
214 | return Status;\r | |
a33a2f62 | 215 | }\r |