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9060e3ec | 1 | /** @file\r |
2 | PCI command register operations supporting functions declaration for PCI Bus module.\r | |
3 | \r | |
cd5ebaa0 HT |
4 | Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r |
5 | This program and the accompanying materials\r | |
9060e3ec | 6 | are licensed and made available under the terms and conditions of the BSD License\r |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | \r | |
16 | #ifndef _EFI_PCI_COMMAND_H_\r | |
17 | #define _EFI_PCI_COMMAND_H_\r | |
18 | \r | |
19 | //\r | |
20 | // The PCI Command register bits owned by PCI Bus driver.\r | |
21 | //\r | |
22 | // They should be cleared at the beginning. The other registers\r | |
23 | // are owned by chipset, we should not touch them.\r | |
24 | //\r | |
25 | #define EFI_PCI_COMMAND_BITS_OWNED ( \\r | |
26 | EFI_PCI_COMMAND_IO_SPACE | \\r | |
27 | EFI_PCI_COMMAND_MEMORY_SPACE | \\r | |
28 | EFI_PCI_COMMAND_BUS_MASTER | \\r | |
29 | EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE | \\r | |
30 | EFI_PCI_COMMAND_VGA_PALETTE_SNOOP | \\r | |
31 | EFI_PCI_COMMAND_FAST_BACK_TO_BACK \\r | |
32 | )\r | |
33 | \r | |
34 | //\r | |
35 | // The PCI Bridge Control register bits owned by PCI Bus driver.\r | |
36 | //\r | |
37 | // They should be cleared at the beginning. The other registers\r | |
38 | // are owned by chipset, we should not touch them.\r | |
39 | //\r | |
40 | #define EFI_PCI_BRIDGE_CONTROL_BITS_OWNED ( \\r | |
41 | EFI_PCI_BRIDGE_CONTROL_ISA | \\r | |
42 | EFI_PCI_BRIDGE_CONTROL_VGA | \\r | |
43 | EFI_PCI_BRIDGE_CONTROL_VGA_16 | \\r | |
44 | EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK \\r | |
45 | )\r | |
46 | \r | |
47 | //\r | |
48 | // The PCCard Bridge Control register bits owned by PCI Bus driver.\r | |
49 | //\r | |
50 | // They should be cleared at the beginning. The other registers\r | |
51 | // are owned by chipset, we should not touch them.\r | |
52 | //\r | |
53 | #define EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED ( \\r | |
54 | EFI_PCI_BRIDGE_CONTROL_ISA | \\r | |
55 | EFI_PCI_BRIDGE_CONTROL_VGA | \\r | |
56 | EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK \\r | |
57 | )\r | |
58 | \r | |
59 | \r | |
60 | #define EFI_GET_REGISTER 1\r | |
61 | #define EFI_SET_REGISTER 2\r | |
62 | #define EFI_ENABLE_REGISTER 3\r | |
63 | #define EFI_DISABLE_REGISTER 4\r | |
64 | \r | |
65 | /**\r | |
66 | Operate the PCI register via PciIo function interface.\r | |
67 | \r | |
68 | @param PciIoDevice Pointer to instance of PCI_IO_DEVICE.\r | |
69 | @param Command Operator command.\r | |
70 | @param Offset The address within the PCI configuration space for the PCI controller.\r | |
71 | @param Operation Type of Operation.\r | |
72 | @param PtrCommand Return buffer holding old PCI command, if operation is not EFI_SET_REGISTER.\r | |
73 | \r | |
74 | @return Status of PciIo operation.\r | |
75 | \r | |
76 | **/\r | |
77 | EFI_STATUS\r | |
78 | PciOperateRegister (\r | |
79 | IN PCI_IO_DEVICE *PciIoDevice,\r | |
80 | IN UINT16 Command,\r | |
81 | IN UINT8 Offset,\r | |
82 | IN UINT8 Operation,\r | |
83 | OUT UINT16 *PtrCommand\r | |
84 | );\r | |
85 | \r | |
86 | /**\r | |
87 | Check the cpability supporting by given device.\r | |
88 | \r | |
89 | @param PciIoDevice Pointer to instance of PCI_IO_DEVICE.\r | |
90 | \r | |
91 | @retval TRUE Cpability supportted.\r | |
92 | @retval FALSE Cpability not supportted.\r | |
93 | \r | |
94 | **/\r | |
95 | BOOLEAN\r | |
96 | PciCapabilitySupport (\r | |
97 | IN PCI_IO_DEVICE *PciIoDevice\r | |
98 | );\r | |
99 | \r | |
100 | /**\r | |
101 | Locate capability register block per capability ID.\r | |
102 | \r | |
103 | @param PciIoDevice A pointer to the PCI_IO_DEVICE.\r | |
104 | @param CapId The capability ID.\r | |
105 | @param Offset A pointer to the offset returned.\r | |
106 | @param NextRegBlock A pointer to the next block returned.\r | |
107 | \r | |
108 | @retval EFI_SUCCESS Successfuly located capability register block.\r | |
109 | @retval EFI_UNSUPPORTED Pci device does not support capability.\r | |
110 | @retval EFI_NOT_FOUND Pci device support but can not find register block.\r | |
111 | \r | |
112 | **/\r | |
113 | EFI_STATUS\r | |
114 | LocateCapabilityRegBlock (\r | |
115 | IN PCI_IO_DEVICE *PciIoDevice,\r | |
116 | IN UINT8 CapId,\r | |
117 | IN OUT UINT8 *Offset,\r | |
118 | OUT UINT8 *NextRegBlock OPTIONAL\r | |
119 | );\r | |
120 | \r | |
121 | /**\r | |
122 | Locate PciExpress capability register block per capability ID.\r | |
123 | \r | |
124 | @param PciIoDevice A pointer to the PCI_IO_DEVICE.\r | |
125 | @param CapId The capability ID.\r | |
126 | @param Offset A pointer to the offset returned.\r | |
127 | @param NextRegBlock A pointer to the next block returned.\r | |
128 | \r | |
129 | @retval EFI_SUCCESS Successfuly located capability register block.\r | |
130 | @retval EFI_UNSUPPORTED Pci device does not support capability.\r | |
131 | @retval EFI_NOT_FOUND Pci device support but can not find register block.\r | |
132 | \r | |
133 | **/\r | |
134 | EFI_STATUS\r | |
135 | LocatePciExpressCapabilityRegBlock (\r | |
136 | IN PCI_IO_DEVICE *PciIoDevice,\r | |
137 | IN UINT16 CapId,\r | |
138 | IN OUT UINT32 *Offset,\r | |
139 | OUT UINT32 *NextRegBlock OPTIONAL\r | |
140 | );\r | |
141 | \r | |
142 | /**\r | |
143 | Macro that reads command register.\r | |
144 | \r | |
145 | @param a[in] Pointer to instance of PCI_IO_DEVICE.\r | |
146 | @param b[out] Pointer to the 16-bit value read from command register.\r | |
147 | \r | |
148 | @return status of PciIo operation\r | |
149 | \r | |
150 | **/\r | |
151 | #define PCI_READ_COMMAND_REGISTER(a,b) \\r | |
152 | PciOperateRegister (a, 0, PCI_COMMAND_OFFSET, EFI_GET_REGISTER, b)\r | |
153 | \r | |
154 | /**\r | |
155 | Macro that writes command register.\r | |
156 | \r | |
157 | @param a[in] Pointer to instance of PCI_IO_DEVICE.\r | |
158 | @param b[in] The 16-bit value written into command register.\r | |
159 | \r | |
160 | @return status of PciIo operation\r | |
161 | \r | |
162 | **/\r | |
163 | #define PCI_SET_COMMAND_REGISTER(a,b) \\r | |
164 | PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_SET_REGISTER, NULL)\r | |
165 | \r | |
166 | /**\r | |
167 | Macro that enables command register.\r | |
168 | \r | |
169 | @param a[in] Pointer to instance of PCI_IO_DEVICE.\r | |
170 | @param b[in] The enabled value written into command register.\r | |
171 | \r | |
172 | @return status of PciIo operation\r | |
173 | \r | |
174 | **/\r | |
175 | #define PCI_ENABLE_COMMAND_REGISTER(a,b) \\r | |
176 | PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_ENABLE_REGISTER, NULL)\r | |
177 | \r | |
178 | /**\r | |
179 | Macro that disalbes command register.\r | |
180 | \r | |
181 | @param a[in] Pointer to instance of PCI_IO_DEVICE.\r | |
182 | @param b[in] The disabled value written into command register.\r | |
183 | \r | |
184 | @return status of PciIo operation\r | |
185 | \r | |
186 | **/\r | |
187 | #define PCI_DISABLE_COMMAND_REGISTER(a,b) \\r | |
188 | PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_DISABLE_REGISTER, NULL)\r | |
189 | \r | |
190 | /**\r | |
191 | Macro that reads PCI bridge control register.\r | |
192 | \r | |
193 | @param a[in] Pointer to instance of PCI_IO_DEVICE.\r | |
194 | @param b[out] The 16-bit value read from control register.\r | |
195 | \r | |
196 | @return status of PciIo operation\r | |
197 | \r | |
198 | **/\r | |
199 | #define PCI_READ_BRIDGE_CONTROL_REGISTER(a,b) \\r | |
200 | PciOperateRegister (a, 0, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_GET_REGISTER, b)\r | |
201 | \r | |
202 | /**\r | |
203 | Macro that writes PCI bridge control register.\r | |
204 | \r | |
205 | @param a[in] Pointer to instance of PCI_IO_DEVICE.\r | |
206 | @param b[in] The 16-bit value written into control register.\r | |
207 | \r | |
208 | @return status of PciIo operation\r | |
209 | \r | |
210 | **/\r | |
211 | #define PCI_SET_BRIDGE_CONTROL_REGISTER(a,b) \\r | |
212 | PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_SET_REGISTER, NULL)\r | |
213 | \r | |
214 | /**\r | |
215 | Macro that enables PCI bridge control register.\r | |
216 | \r | |
217 | @param a[in] Pointer to instance of PCI_IO_DEVICE.\r | |
218 | @param b[in] The enabled value written into command register.\r | |
219 | \r | |
220 | @return status of PciIo operation\r | |
221 | \r | |
222 | **/\r | |
223 | #define PCI_ENABLE_BRIDGE_CONTROL_REGISTER(a,b) \\r | |
224 | PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_ENABLE_REGISTER, NULL)\r | |
225 | \r | |
226 | /**\r | |
227 | Macro that disalbes PCI bridge control register.\r | |
228 | \r | |
229 | @param a[in] Pointer to instance of PCI_IO_DEVICE.\r | |
230 | @param b[in] The disabled value written into command register.\r | |
231 | \r | |
232 | @return status of PciIo operation\r | |
233 | \r | |
234 | **/\r | |
235 | #define PCI_DISABLE_BRIDGE_CONTROL_REGISTER(a,b) \\r | |
236 | PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_DISABLE_REGISTER, NULL)\r | |
237 | \r | |
238 | #endif\r |