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913cb9dc | 1 | /** @file\r |
2 | \r | |
ab6495ea | 3 | The definition for UHCI register operation routines.\r |
4 | \r | |
cd5ebaa0 HT |
5 | Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>\r |
6 | This program and the accompanying materials\r | |
913cb9dc | 7 | are licensed and made available under the terms and conditions of the BSD License\r |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
913cb9dc | 14 | **/\r |
15 | \r | |
16 | #ifndef _EFI_UHCI_REG_H_\r | |
17 | #define _EFI_UHCI_REG_H_\r | |
18 | \r | |
1ccdbf2a | 19 | //\r |
20 | // UHCI register offset\r | |
21 | //\r | |
22 | \r | |
23 | #define UHCI_FRAME_NUM 1024\r | |
24 | \r | |
25 | //\r | |
26 | // Register offset and PCI related staff\r | |
27 | //\r | |
28 | #define USB_BAR_INDEX 4\r | |
29 | \r | |
30 | #define USBCMD_OFFSET 0\r | |
31 | #define USBSTS_OFFSET 2\r | |
32 | #define USBINTR_OFFSET 4\r | |
33 | #define USBPORTSC_OFFSET 0x10\r | |
34 | #define USB_FRAME_NO_OFFSET 6\r | |
35 | #define USB_FRAME_BASE_OFFSET 8\r | |
36 | #define USB_EMULATION_OFFSET 0xC0\r | |
37 | \r | |
38 | //\r | |
39 | // Packet IDs\r | |
40 | //\r | |
41 | #define SETUP_PACKET_ID 0x2D\r | |
42 | #define INPUT_PACKET_ID 0x69\r | |
43 | #define OUTPUT_PACKET_ID 0xE1\r | |
44 | #define ERROR_PACKET_ID 0x55\r | |
45 | \r | |
46 | //\r | |
47 | // USB port status and control bit definition.\r | |
48 | //\r | |
49 | #define USBPORTSC_CCS BIT0 // Current Connect Status\r | |
50 | #define USBPORTSC_CSC BIT1 // Connect Status Change\r | |
51 | #define USBPORTSC_PED BIT2 // Port Enable / Disable\r | |
52 | #define USBPORTSC_PEDC BIT3 // Port Enable / Disable Change\r | |
53 | #define USBPORTSC_LSL BIT4 // Line Status Low BIT\r | |
54 | #define USBPORTSC_LSH BIT5 // Line Status High BIT\r | |
55 | #define USBPORTSC_RD BIT6 // Resume Detect\r | |
56 | #define USBPORTSC_LSDA BIT8 // Low Speed Device Attached\r | |
57 | #define USBPORTSC_PR BIT9 // Port Reset\r | |
58 | #define USBPORTSC_SUSP BIT12 // Suspend\r | |
59 | \r | |
60 | //\r | |
61 | // UHCI Spec said it must implement 2 ports each host at least,\r | |
62 | // and if more, check whether the bit7 of PORTSC is always 1.\r | |
63 | // So here assume the max of port number each host is 16.\r | |
64 | //\r | |
65 | #define USB_MAX_ROOTHUB_PORT 0x0F\r | |
66 | \r | |
67 | //\r | |
68 | // Command register bit definitions\r | |
69 | //\r | |
70 | #define USBCMD_RS BIT0 // Run/Stop\r | |
71 | #define USBCMD_HCRESET BIT1 // Host reset\r | |
72 | #define USBCMD_GRESET BIT2 // Global reset\r | |
73 | #define USBCMD_EGSM BIT3 // Global Suspend Mode\r | |
74 | #define USBCMD_FGR BIT4 // Force Global Resume\r | |
75 | #define USBCMD_SWDBG BIT5 // SW Debug mode\r | |
76 | #define USBCMD_CF BIT6 // Config Flag (sw only)\r | |
77 | #define USBCMD_MAXP BIT7 // Max Packet (0 = 32, 1 = 64)\r | |
78 | \r | |
79 | //\r | |
80 | // USB Status register bit definitions\r | |
81 | //\r | |
82 | #define USBSTS_USBINT BIT0 // Interrupt due to IOC\r | |
83 | #define USBSTS_ERROR BIT1 // Interrupt due to error\r | |
84 | #define USBSTS_RD BIT2 // Resume Detect\r | |
85 | #define USBSTS_HSE BIT3 // Host System Error\r | |
86 | #define USBSTS_HCPE BIT4 // Host Controller Process Error\r | |
87 | #define USBSTS_HCH BIT5 // HC Halted\r | |
88 | \r | |
89 | #define USBTD_ACTIVE BIT7 // TD is still active\r | |
90 | #define USBTD_STALLED BIT6 // TD is stalled\r | |
91 | #define USBTD_BUFFERR BIT5 // Buffer underflow or overflow\r | |
92 | #define USBTD_BABBLE BIT4 // Babble condition\r | |
93 | #define USBTD_NAK BIT3 // NAK is received\r | |
94 | #define USBTD_CRC BIT2 // CRC/Time out error\r | |
95 | #define USBTD_BITSTUFF BIT1 // Bit stuff error\r | |
913cb9dc | 96 | \r |
97 | \r | |
98 | /**\r | |
ab6495ea | 99 | Read a UHCI register.\r |
913cb9dc | 100 | \r |
ab6495ea | 101 | @param PciIo The EFI_PCI_IO_PROTOCOL to use.\r |
102 | @param Offset Register offset to USB_BAR_INDEX.\r | |
913cb9dc | 103 | \r |
ab6495ea | 104 | @return Content of register.\r |
913cb9dc | 105 | \r |
106 | **/\r | |
107 | UINT16\r | |
108 | UhciReadReg (\r | |
109 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
110 | IN UINT32 Offset\r | |
ed66e1bc | 111 | );\r |
913cb9dc | 112 | \r |
113 | \r | |
114 | \r | |
115 | /**\r | |
ab6495ea | 116 | Write data to UHCI register.\r |
913cb9dc | 117 | \r |
ab6495ea | 118 | @param PciIo The EFI_PCI_IO_PROTOCOL to use.\r |
119 | @param Offset Register offset to USB_BAR_INDEX.\r | |
120 | @param Data Data to write.\r | |
913cb9dc | 121 | \r |
ab6495ea | 122 | @return None.\r |
913cb9dc | 123 | \r |
124 | **/\r | |
125 | VOID\r | |
126 | UhciWriteReg (\r | |
127 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
128 | IN UINT32 Offset,\r | |
129 | IN UINT16 Data\r | |
ed66e1bc | 130 | );\r |
913cb9dc | 131 | \r |
132 | \r | |
133 | \r | |
134 | /**\r | |
ab6495ea | 135 | Set a bit of the UHCI Register.\r |
913cb9dc | 136 | \r |
ab6495ea | 137 | @param PciIo The EFI_PCI_IO_PROTOCOL to use.\r |
138 | @param Offset Register offset to USB_BAR_INDEX.\r | |
139 | @param Bit The bit to set.\r | |
913cb9dc | 140 | \r |
ab6495ea | 141 | @return None.\r |
913cb9dc | 142 | \r |
143 | **/\r | |
144 | VOID\r | |
145 | UhciSetRegBit (\r | |
146 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
147 | IN UINT32 Offset,\r | |
148 | IN UINT16 Bit\r | |
ed66e1bc | 149 | );\r |
913cb9dc | 150 | \r |
151 | \r | |
152 | \r | |
153 | /**\r | |
ab6495ea | 154 | Clear a bit of the UHCI Register.\r |
913cb9dc | 155 | \r |
ab6495ea | 156 | @param PciIo The PCI_IO protocol to access the PCI.\r |
157 | @param Offset Register offset to USB_BAR_INDEX.\r | |
158 | @param Bit The bit to clear.\r | |
913cb9dc | 159 | \r |
ab6495ea | 160 | @return None.\r |
913cb9dc | 161 | \r |
162 | **/\r | |
163 | VOID\r | |
164 | UhciClearRegBit (\r | |
165 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
166 | IN UINT32 Offset,\r | |
167 | IN UINT16 Bit\r | |
ed66e1bc | 168 | );\r |
913cb9dc | 169 | \r |
170 | \r | |
171 | /**\r | |
172 | Clear all the interrutp status bits, these bits\r | |
ab6495ea | 173 | are Write-Clean.\r |
913cb9dc | 174 | \r |
ab6495ea | 175 | @param Uhc The UHCI device.\r |
913cb9dc | 176 | \r |
ab6495ea | 177 | @return None.\r |
913cb9dc | 178 | \r |
179 | **/\r | |
180 | VOID\r | |
181 | UhciAckAllInterrupt (\r | |
182 | IN USB_HC_DEV *Uhc\r | |
ed66e1bc | 183 | );\r |
913cb9dc | 184 | \r |
185 | \r | |
186 | /**\r | |
ab6495ea | 187 | Stop the host controller.\r |
913cb9dc | 188 | \r |
ab6495ea | 189 | @param Uhc The UHCI device.\r |
190 | @param Timeout Max time allowed.\r | |
913cb9dc | 191 | \r |
ab6495ea | 192 | @retval EFI_SUCCESS The host controller is stopped.\r |
193 | @retval EFI_TIMEOUT Failed to stop the host controller.\r | |
913cb9dc | 194 | \r |
195 | **/\r | |
196 | EFI_STATUS\r | |
197 | UhciStopHc (\r | |
198 | IN USB_HC_DEV *Uhc,\r | |
199 | IN UINTN Timeout\r | |
ed66e1bc | 200 | );\r |
913cb9dc | 201 | \r |
202 | \r | |
203 | \r | |
204 | /**\r | |
ab6495ea | 205 | Check whether the host controller operates well.\r |
913cb9dc | 206 | \r |
ab6495ea | 207 | @param PciIo The PCI_IO protocol to use.\r |
913cb9dc | 208 | \r |
ab6495ea | 209 | @retval TRUE Host controller is working.\r |
210 | @retval FALSE Host controller is halted or system error.\r | |
913cb9dc | 211 | \r |
212 | **/\r | |
213 | BOOLEAN\r | |
214 | UhciIsHcWorking (\r | |
215 | IN EFI_PCI_IO_PROTOCOL *PciIo\r | |
ed66e1bc | 216 | );\r |
913cb9dc | 217 | \r |
218 | \r | |
219 | /**\r | |
220 | Set the UHCI frame list base address. It can't use\r | |
221 | UhciWriteReg which access memory in UINT16.\r | |
222 | \r | |
ab6495ea | 223 | @param PciIo The EFI_PCI_IO_PROTOCOL to use.\r |
224 | @param Addr Address to set.\r | |
913cb9dc | 225 | \r |
ab6495ea | 226 | @return None.\r |
913cb9dc | 227 | \r |
228 | **/\r | |
229 | VOID\r | |
230 | UhciSetFrameListBaseAddr (\r | |
231 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
232 | IN VOID *Addr\r | |
ed66e1bc | 233 | );\r |
913cb9dc | 234 | \r |
235 | \r | |
236 | /**\r | |
ab6495ea | 237 | Disable USB Emulation.\r |
913cb9dc | 238 | \r |
ab6495ea | 239 | @param PciIo The EFI_PCI_IO_PROTOCOL protocol to use.\r |
913cb9dc | 240 | \r |
ab6495ea | 241 | @return None.\r |
913cb9dc | 242 | \r |
243 | **/\r | |
244 | VOID\r | |
245 | UhciTurnOffUsbEmulation (\r | |
246 | IN EFI_PCI_IO_PROTOCOL *PciIo\r | |
ed66e1bc | 247 | );\r |
913cb9dc | 248 | #endif\r |