]>
Commit | Line | Data |
---|---|---|
ea060cfa | 1 | /** @file\r |
2 | Define the PPI to abstract the functions that enable IDE and SATA channels, and to retrieve\r | |
3 | the base I/O port address for each of the enabled IDE and SATA channels.\r | |
4 | \r | |
5 | Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r | |
6 | \r | |
7 | This program and the accompanying materials\r | |
8 | are licensed and made available under the terms and conditions\r | |
9 | of the BSD License which accompanies this distribution. The\r | |
10 | full text of the license may be found at\r | |
11 | http://opensource.org/licenses/bsd-license.php\r | |
12 | \r | |
13 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
14 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
15 | \r | |
16 | **/\r | |
17 | \r | |
18 | #ifndef _PEI_ATA_CONTROLLER_PPI_H_\r | |
19 | #define _PEI_ATA_CONTROLLER_PPI_H_\r | |
20 | \r | |
21 | ///\r | |
22 | /// Global ID for the PEI_ATA_CONTROLLER_PPI. \r | |
23 | ///\r | |
24 | #define PEI_ATA_CONTROLLER_PPI_GUID \\r | |
25 | { \\r | |
26 | 0xa45e60d1, 0xc719, 0x44aa, {0xb0, 0x7a, 0xaa, 0x77, 0x7f, 0x85, 0x90, 0x6d } \\r | |
27 | }\r | |
28 | \r | |
29 | ///\r | |
30 | /// Forward declaration for the PEI_ATA_CONTROLLER_PPI.\r | |
31 | ///\r | |
32 | typedef struct _PEI_ATA_CONTROLLER_PPI PEI_ATA_CONTROLLER_PPI;\r | |
33 | \r | |
34 | ///\r | |
35 | /// This bit is used in the ChannelMask parameter of EnableAtaChannel() to \r | |
36 | /// disable the IDE channels. \r | |
37 | /// This is designed for old generation chipset with PATA/SATA controllers. \r | |
38 | /// It may be ignored in PPI implementation for new generation chipset without PATA controller. \r | |
39 | ///\r | |
40 | #define PEI_ICH_IDE_NONE 0x00\r | |
41 | \r | |
42 | ///\r | |
43 | /// This bit is used in the ChannelMask parameter of EnableAtaChannel() to \r | |
44 | /// enable the Primary IDE channel.\r | |
45 | /// This is designed for old generation chipset with PATA/SATA controllers. \r | |
46 | /// It may be ignored in PPI implementation for new generation chipset without PATA controller. \r | |
47 | ///\r | |
48 | #define PEI_ICH_IDE_PRIMARY 0x01\r | |
49 | \r | |
50 | ///\r | |
51 | /// This bit is used in the ChannelMask parameter of EnableAtaChannel() to \r | |
52 | /// enable the Secondary IDE channel.\r | |
53 | /// This is designed for old generation chipset with PATA/SATA controllers. \r | |
54 | /// It may be ignored in PPI implementation for new generation chipset without PATA controller. \r | |
55 | ///\r | |
56 | #define PEI_ICH_IDE_SECONDARY 0x02\r | |
57 | \r | |
58 | ///\r | |
59 | /// This bit is used in the ChannelMask parameter of EnableAtaChannel() to \r | |
60 | /// disable the SATA channel.\r | |
61 | /// This is designed for old generation chipset with PATA/SATA controllers. \r | |
62 | /// It may be ignored in PPI implementation for new generation chipset without PATA controller. \r | |
63 | ///\r | |
64 | #define PEI_ICH_SATA_NONE 0x04\r | |
65 | \r | |
66 | ///\r | |
67 | /// This bit is used in the ChannelMask parameter of EnableAtaChannel() to \r | |
68 | /// enable the Primary SATA channel.\r | |
69 | /// This is designed for old generation chipset with PATA/SATA controllers. \r | |
70 | /// It may be ignored in PPI implementation for new generation chipset without PATA controller. \r | |
71 | ///\r | |
72 | #define PEI_ICH_SATA_PRIMARY 0x08\r | |
73 | \r | |
74 | ///\r | |
75 | /// This bit is used in the ChannelMask parameter of EnableAtaChannel() to \r | |
76 | /// enable the Secondary SATA channel.\r | |
77 | /// This is designed for old generation chipset with PATA/SATA controllers. \r | |
78 | /// It may be ignored in PPI implementation for new generation chipset without PATA controller. \r | |
79 | ///\r | |
80 | #define PEI_ICH_SATA_SECONDARY 0x010\r | |
81 | \r | |
82 | ///\r | |
83 | /// Structure that contains the base addresses for the IDE registers\r | |
84 | ///\r | |
85 | typedef struct {\r | |
86 | ///\r | |
87 | /// Base I/O port address of the IDE controller's command block\r | |
88 | ///\r | |
89 | UINT16 CommandBlockBaseAddr;\r | |
90 | ///\r | |
91 | /// Base I/O port address of the IDE controller's control block\r | |
92 | ///\r | |
93 | UINT16 ControlBlockBaseAddr;\r | |
94 | } IDE_REGS_BASE_ADDR;\r | |
95 | \r | |
96 | /**\r | |
97 | Sets IDE and SATA channels to an enabled or disabled state.\r | |
98 | \r | |
99 | This service enables or disables the IDE and SATA channels specified by ChannelMask.\r | |
100 | It may ignore ChannelMask setting to enable or disable IDE and SATA channels based on the platform policy. \r | |
101 | The number of the enabled channels will be returned by GET_IDE_REGS_BASE_ADDR() function. \r | |
102 | \r | |
103 | If the new state is set, then EFI_SUCCESS is returned. If the new state can\r | |
104 | not be set, then EFI_DEVICE_ERROR is returned.\r | |
105 | \r | |
106 | @param[in] PeiServices The pointer to the PEI Services Table.\r | |
107 | @param[in] This The pointer to this instance of the PEI_ATA_CONTROLLER_PPI.\r | |
108 | @param[in] ChannelMask The bitmask that identifies the IDE and SATA channels to \r | |
86ac8fb2 | 109 | enable or disable. This parameter is optional.\r |
ea060cfa | 110 | \r |
111 | @retval EFI_SUCCESS The IDE or SATA channels were enabled or disabled successfully.\r | |
112 | @retval EFI_DEVICE_ERROR The IDE or SATA channels could not be enabled or disabled.\r | |
113 | \r | |
114 | **/\r | |
115 | typedef\r | |
116 | EFI_STATUS\r | |
117 | (EFIAPI *PEI_ENABLE_ATA)(\r | |
118 | IN EFI_PEI_SERVICES **PeiServices,\r | |
119 | IN PEI_ATA_CONTROLLER_PPI *This,\r | |
120 | IN UINT8 ChannelMask\r | |
121 | );\r | |
122 | \r | |
123 | /**\r | |
124 | Retrieves the I/O port base addresses for command and control registers of the \r | |
125 | enabled IDE/SATA channels.\r | |
126 | \r | |
127 | This service fills in the structure poionted to by IdeRegsBaseAddr with the I/O\r | |
128 | port base addresses for the command and control registers of the IDE and SATA\r | |
129 | channels that were previously enabled in EnableAtaChannel(). The number of \r | |
130 | enabled IDE and SATA channels is returned.\r | |
131 | \r | |
132 | @param[in] PeiServices The pointer to the PEI Services Table.\r | |
133 | @param[in] This The pointer to this instance of the PEI_ATA_CONTROLLER_PPI.\r | |
134 | @param[out] IdeRegsBaseAddr The pointer to caller allocated space to return the \r | |
135 | I/O port base addresses of the IDE and SATA channels \r | |
136 | that were previosuly enabled with EnableAtaChannel().\r | |
137 | \r | |
138 | @return The number of enabled IDE and SATA channels in the platform.\r | |
139 | \r | |
140 | **/\r | |
141 | typedef\r | |
142 | UINT32\r | |
143 | (EFIAPI *GET_IDE_REGS_BASE_ADDR)(\r | |
144 | IN EFI_PEI_SERVICES **PeiServices,\r | |
145 | IN PEI_ATA_CONTROLLER_PPI *This,\r | |
146 | OUT IDE_REGS_BASE_ADDR *IdeRegsBaseAddr \r | |
147 | );\r | |
148 | \r | |
149 | ///\r | |
150 | /// This PPI contains services to enable and disable IDE and SATA channels and\r | |
151 | /// retrieves the base I/O port addresses to the enabled IDE and SATA channels.\r | |
152 | ///\r | |
153 | struct _PEI_ATA_CONTROLLER_PPI {\r | |
154 | PEI_ENABLE_ATA EnableAtaChannel;\r | |
155 | GET_IDE_REGS_BASE_ADDR GetIdeRegsBaseAddr;\r | |
156 | };\r | |
157 | \r | |
158 | extern EFI_GUID gPeiAtaControllerPpiGuid;\r | |
159 | \r | |
160 | #endif\r | |
161 | \r | |
162 | \r |