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ea060cfa | 1 | /** @file\r |
2 | Define the PPI to abstract the functions that enable IDE and SATA channels, and to retrieve\r | |
3 | the base I/O port address for each of the enabled IDE and SATA channels.\r | |
d1102dba LG |
4 | \r |
5 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r | |
ea060cfa | 6 | \r |
9d510e61 | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
ea060cfa | 8 | \r |
9 | **/\r | |
10 | \r | |
11 | #ifndef _PEI_ATA_CONTROLLER_PPI_H_\r | |
12 | #define _PEI_ATA_CONTROLLER_PPI_H_\r | |
13 | \r | |
14 | ///\r | |
d1102dba | 15 | /// Global ID for the PEI_ATA_CONTROLLER_PPI.\r |
ea060cfa | 16 | ///\r |
17 | #define PEI_ATA_CONTROLLER_PPI_GUID \\r | |
18 | { \\r | |
19 | 0xa45e60d1, 0xc719, 0x44aa, {0xb0, 0x7a, 0xaa, 0x77, 0x7f, 0x85, 0x90, 0x6d } \\r | |
20 | }\r | |
21 | \r | |
22 | ///\r | |
23 | /// Forward declaration for the PEI_ATA_CONTROLLER_PPI.\r | |
24 | ///\r | |
25 | typedef struct _PEI_ATA_CONTROLLER_PPI PEI_ATA_CONTROLLER_PPI;\r | |
26 | \r | |
27 | ///\r | |
d1102dba LG |
28 | /// This bit is used in the ChannelMask parameter of EnableAtaChannel() to\r |
29 | /// disable the IDE channels.\r | |
30 | /// This is designed for old generation chipset with PATA/SATA controllers.\r | |
31 | /// It may be ignored in PPI implementation for new generation chipset without PATA controller.\r | |
ea060cfa | 32 | ///\r |
33 | #define PEI_ICH_IDE_NONE 0x00\r | |
34 | \r | |
35 | ///\r | |
d1102dba | 36 | /// This bit is used in the ChannelMask parameter of EnableAtaChannel() to\r |
ea060cfa | 37 | /// enable the Primary IDE channel.\r |
d1102dba LG |
38 | /// This is designed for old generation chipset with PATA/SATA controllers.\r |
39 | /// It may be ignored in PPI implementation for new generation chipset without PATA controller.\r | |
ea060cfa | 40 | ///\r |
41 | #define PEI_ICH_IDE_PRIMARY 0x01\r | |
42 | \r | |
43 | ///\r | |
d1102dba | 44 | /// This bit is used in the ChannelMask parameter of EnableAtaChannel() to\r |
ea060cfa | 45 | /// enable the Secondary IDE channel.\r |
d1102dba LG |
46 | /// This is designed for old generation chipset with PATA/SATA controllers.\r |
47 | /// It may be ignored in PPI implementation for new generation chipset without PATA controller.\r | |
ea060cfa | 48 | ///\r |
49 | #define PEI_ICH_IDE_SECONDARY 0x02\r | |
50 | \r | |
51 | ///\r | |
d1102dba | 52 | /// This bit is used in the ChannelMask parameter of EnableAtaChannel() to\r |
ea060cfa | 53 | /// disable the SATA channel.\r |
d1102dba LG |
54 | /// This is designed for old generation chipset with PATA/SATA controllers.\r |
55 | /// It may be ignored in PPI implementation for new generation chipset without PATA controller.\r | |
ea060cfa | 56 | ///\r |
57 | #define PEI_ICH_SATA_NONE 0x04\r | |
58 | \r | |
59 | ///\r | |
d1102dba | 60 | /// This bit is used in the ChannelMask parameter of EnableAtaChannel() to\r |
ea060cfa | 61 | /// enable the Primary SATA channel.\r |
d1102dba LG |
62 | /// This is designed for old generation chipset with PATA/SATA controllers.\r |
63 | /// It may be ignored in PPI implementation for new generation chipset without PATA controller.\r | |
ea060cfa | 64 | ///\r |
65 | #define PEI_ICH_SATA_PRIMARY 0x08\r | |
66 | \r | |
67 | ///\r | |
d1102dba | 68 | /// This bit is used in the ChannelMask parameter of EnableAtaChannel() to\r |
ea060cfa | 69 | /// enable the Secondary SATA channel.\r |
d1102dba LG |
70 | /// This is designed for old generation chipset with PATA/SATA controllers.\r |
71 | /// It may be ignored in PPI implementation for new generation chipset without PATA controller.\r | |
ea060cfa | 72 | ///\r |
73 | #define PEI_ICH_SATA_SECONDARY 0x010\r | |
74 | \r | |
75 | ///\r | |
76 | /// Structure that contains the base addresses for the IDE registers\r | |
77 | ///\r | |
78 | typedef struct {\r | |
79 | ///\r | |
80 | /// Base I/O port address of the IDE controller's command block\r | |
81 | ///\r | |
82 | UINT16 CommandBlockBaseAddr;\r | |
83 | ///\r | |
84 | /// Base I/O port address of the IDE controller's control block\r | |
85 | ///\r | |
86 | UINT16 ControlBlockBaseAddr;\r | |
87 | } IDE_REGS_BASE_ADDR;\r | |
88 | \r | |
89 | /**\r | |
90 | Sets IDE and SATA channels to an enabled or disabled state.\r | |
91 | \r | |
92 | This service enables or disables the IDE and SATA channels specified by ChannelMask.\r | |
d1102dba LG |
93 | It may ignore ChannelMask setting to enable or disable IDE and SATA channels based on the platform policy.\r |
94 | The number of the enabled channels will be returned by GET_IDE_REGS_BASE_ADDR() function.\r | |
ea060cfa | 95 | \r |
96 | If the new state is set, then EFI_SUCCESS is returned. If the new state can\r | |
97 | not be set, then EFI_DEVICE_ERROR is returned.\r | |
98 | \r | |
99 | @param[in] PeiServices The pointer to the PEI Services Table.\r | |
100 | @param[in] This The pointer to this instance of the PEI_ATA_CONTROLLER_PPI.\r | |
d1102dba | 101 | @param[in] ChannelMask The bitmask that identifies the IDE and SATA channels to\r |
86ac8fb2 | 102 | enable or disable. This parameter is optional.\r |
ea060cfa | 103 | \r |
104 | @retval EFI_SUCCESS The IDE or SATA channels were enabled or disabled successfully.\r | |
105 | @retval EFI_DEVICE_ERROR The IDE or SATA channels could not be enabled or disabled.\r | |
106 | \r | |
107 | **/\r | |
108 | typedef\r | |
109 | EFI_STATUS\r | |
110 | (EFIAPI *PEI_ENABLE_ATA)(\r | |
111 | IN EFI_PEI_SERVICES **PeiServices,\r | |
112 | IN PEI_ATA_CONTROLLER_PPI *This,\r | |
113 | IN UINT8 ChannelMask\r | |
114 | );\r | |
115 | \r | |
116 | /**\r | |
d1102dba | 117 | Retrieves the I/O port base addresses for command and control registers of the\r |
ea060cfa | 118 | enabled IDE/SATA channels.\r |
119 | \r | |
120 | This service fills in the structure poionted to by IdeRegsBaseAddr with the I/O\r | |
121 | port base addresses for the command and control registers of the IDE and SATA\r | |
d1102dba | 122 | channels that were previously enabled in EnableAtaChannel(). The number of\r |
ea060cfa | 123 | enabled IDE and SATA channels is returned.\r |
124 | \r | |
125 | @param[in] PeiServices The pointer to the PEI Services Table.\r | |
126 | @param[in] This The pointer to this instance of the PEI_ATA_CONTROLLER_PPI.\r | |
d1102dba LG |
127 | @param[out] IdeRegsBaseAddr The pointer to caller allocated space to return the\r |
128 | I/O port base addresses of the IDE and SATA channels\r | |
ea060cfa | 129 | that were previosuly enabled with EnableAtaChannel().\r |
130 | \r | |
131 | @return The number of enabled IDE and SATA channels in the platform.\r | |
132 | \r | |
133 | **/\r | |
134 | typedef\r | |
135 | UINT32\r | |
136 | (EFIAPI *GET_IDE_REGS_BASE_ADDR)(\r | |
137 | IN EFI_PEI_SERVICES **PeiServices,\r | |
138 | IN PEI_ATA_CONTROLLER_PPI *This,\r | |
d1102dba | 139 | OUT IDE_REGS_BASE_ADDR *IdeRegsBaseAddr\r |
ea060cfa | 140 | );\r |
141 | \r | |
142 | ///\r | |
143 | /// This PPI contains services to enable and disable IDE and SATA channels and\r | |
144 | /// retrieves the base I/O port addresses to the enabled IDE and SATA channels.\r | |
145 | ///\r | |
146 | struct _PEI_ATA_CONTROLLER_PPI {\r | |
147 | PEI_ENABLE_ATA EnableAtaChannel;\r | |
148 | GET_IDE_REGS_BASE_ADDR GetIdeRegsBaseAddr;\r | |
149 | };\r | |
150 | \r | |
151 | extern EFI_GUID gPeiAtaControllerPpiGuid;\r | |
152 | \r | |
153 | #endif\r | |
154 | \r | |
155 | \r |