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1 | /** @file\r |
2 | DMA Remapping Reporting (DMAR) ACPI table definition from Intel(R)\r | |
3 | Virtualization Technology for Directed I/O (VT-D) Architecture Specification.\r | |
4 | \r | |
8ab0bd23 | 5 | Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r |
9344f092 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
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7 | \r |
8 | @par Revision Reference:\r | |
9 | - Intel(R) Virtualization Technology for Directed I/O (VT-D) Architecture\r | |
8ab0bd23 | 10 | Specification v2.5, Dated November 2017.\r |
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11 | http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-directed-io-spec.pdf\r |
12 | \r | |
13 | @par Glossary:\r | |
14 | - HPET - High Precision Event Timer\r | |
15 | - NUMA - Non-uniform Memory Access\r | |
16 | **/\r | |
17 | #ifndef _DMA_REMAPPING_REPORTING_TABLE_H_\r | |
18 | #define _DMA_REMAPPING_REPORTING_TABLE_H_\r | |
19 | \r | |
83a45784 JY |
20 | #include <IndustryStandard/Acpi.h>\r |
21 | \r | |
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22 | #pragma pack(1)\r |
23 | \r | |
24 | ///\r | |
25 | /// DMA-Remapping Reporting Structure definitions from section 8.1\r | |
26 | ///@{\r | |
8ab0bd23 | 27 | #define EFI_ACPI_DMAR_REVISION 0x01\r |
846ea5f5 | 28 | \r |
8ab0bd23 HW |
29 | #define EFI_ACPI_DMAR_FLAGS_INTR_REMAP BIT0\r |
30 | #define EFI_ACPI_DMAR_FLAGS_X2APIC_OPT_OUT BIT1\r | |
31 | #define EFI_ACPI_DMAR_FLAGS_DMA_CTRL_PLATFORM_OPT_IN_FLAG BIT2\r | |
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32 | ///@}\r |
33 | \r | |
34 | ///\r | |
35 | /// Remapping Structure Types definitions from section 8.2\r | |
36 | ///@{\r | |
37 | #define EFI_ACPI_DMAR_TYPE_DRHD 0x00\r | |
38 | #define EFI_ACPI_DMAR_TYPE_RMRR 0x01\r | |
39 | #define EFI_ACPI_DMAR_TYPE_ATSR 0x02\r | |
40 | #define EFI_ACPI_DMAR_TYPE_RHSA 0x03\r | |
41 | #define EFI_ACPI_DMAR_TYPE_ANDD 0x04\r | |
42 | ///@}\r | |
43 | \r | |
44 | ///\r | |
45 | /// DMA-Remapping Hardware Unit definitions from section 8.3\r | |
46 | ///\r | |
47 | #define EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL BIT0\r | |
48 | \r | |
49 | ///\r | |
50 | /// DMA-Remapping Device Scope Entry Structure definitions from section 8.3.1\r | |
51 | ///@{\r | |
52 | #define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT 0x01\r | |
53 | #define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_BRIDGE 0x02\r | |
54 | #define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_IOAPIC 0x03\r | |
55 | #define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_MSI_CAPABLE_HPET 0x04\r | |
56 | #define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_ACPI_NAMESPACE_DEVICE 0x05\r | |
57 | ///@}\r | |
58 | \r | |
59 | ///\r | |
60 | /// Root Port ATS Capability Reporting Structure definitions from section 8.5\r | |
61 | ///\r | |
62 | #define EFI_ACPI_DMAR_ATSR_FLAGS_ALL_PORTS BIT0\r | |
63 | \r | |
64 | ///\r | |
65 | /// Definition for DMA Remapping Structure Header\r | |
66 | ///\r | |
67 | typedef struct {\r | |
68 | UINT16 Type;\r | |
69 | UINT16 Length;\r | |
70 | } EFI_ACPI_DMAR_STRUCTURE_HEADER;\r | |
71 | \r | |
72 | ///\r | |
73 | /// Definition for DMA-Remapping PCI Path\r | |
74 | ///\r | |
75 | typedef struct {\r | |
76 | UINT8 Device;\r | |
77 | UINT8 Function;\r | |
78 | } EFI_ACPI_DMAR_PCI_PATH;\r | |
79 | \r | |
80 | ///\r | |
81 | /// Device Scope Structure is defined in section 8.3.1\r | |
82 | ///\r | |
83 | typedef struct {\r | |
84 | UINT8 Type;\r | |
85 | UINT8 Length;\r | |
86 | UINT16 Reserved2;\r | |
87 | UINT8 EnumerationId;\r | |
88 | UINT8 StartBusNumber;\r | |
89 | } EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER;\r | |
90 | \r | |
91 | /**\r | |
92 | DMA-remapping hardware unit definition (DRHD) structure is defined in\r | |
93 | section 8.3. This uniquely represents a remapping hardware unit present\r | |
94 | in the platform. There must be at least one instance of this structure\r | |
95 | for each PCI segment in the platform.\r | |
96 | **/\r | |
97 | typedef struct {\r | |
98 | EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r | |
99 | /**\r | |
100 | - Bit[0]: INCLUDE_PCI_ALL\r | |
101 | - If Set, this remapping hardware unit has under its scope all\r | |
102 | PCI compatible devices in the specified Segment, except devices\r | |
103 | reported under the scope of other remapping hardware units for\r | |
104 | the same Segment.\r | |
105 | - If Clear, this remapping hardware unit has under its scope only\r | |
106 | devices in the specified Segment that are explicitly identified\r | |
107 | through the DeviceScope field.\r | |
108 | - Bits[7:1] Reserved.\r | |
109 | **/\r | |
110 | UINT8 Flags;\r | |
111 | UINT8 Reserved;\r | |
112 | ///\r | |
113 | /// The PCI Segment associated with this unit.\r | |
114 | ///\r | |
115 | UINT16 SegmentNumber;\r | |
116 | ///\r | |
117 | /// Base address of remapping hardware register-set for this unit.\r | |
118 | ///\r | |
119 | UINT64 RegisterBaseAddress;\r | |
120 | } EFI_ACPI_DMAR_DRHD_HEADER;\r | |
121 | \r | |
122 | /**\r | |
123 | Reserved Memory Region Reporting Structure (RMRR) is described in section 8.4\r | |
124 | Reserved memory ranges that may be DMA targets may be reported through the\r | |
125 | RMRR structures, along with the devices that requires access to the specified\r | |
126 | reserved memory region.\r | |
127 | **/\r | |
128 | typedef struct {\r | |
129 | EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r | |
130 | UINT8 Reserved[2];\r | |
131 | ///\r | |
132 | /// PCI Segment Number associated with devices identified through\r | |
133 | /// the Device Scope field.\r | |
134 | ///\r | |
135 | UINT16 SegmentNumber;\r | |
136 | ///\r | |
137 | /// Base address of 4KB-aligned reserved memory region\r | |
138 | ///\r | |
139 | UINT64 ReservedMemoryRegionBaseAddress;\r | |
140 | /**\r | |
141 | Last address of the reserved memory region. Value in this field must be\r | |
142 | greater than the value in Reserved Memory Region Base Address field.\r | |
143 | The reserved memory region size (Limit - Base + 1) must be an integer\r | |
144 | multiple of 4KB.\r | |
145 | **/\r | |
146 | UINT64 ReservedMemoryRegionLimitAddress;\r | |
147 | } EFI_ACPI_DMAR_RMRR_HEADER;\r | |
148 | \r | |
149 | /**\r | |
150 | Root Port ATS Capability Reporting (ATSR) structure is defined in section 8.5.\r | |
151 | This structure is applicable only for platforms supporting Device-TLBs as\r | |
152 | reported through the Extended Capability Register. For each PCI Segment in\r | |
153 | the platform that supports Device-TLBs, BIOS provides an ATSR structure. The\r | |
154 | ATSR structures identifies PCI-Express Root-Ports supporting Address\r | |
155 | Translation Services (ATS) transactions. Software must enable ATS on endpoint\r | |
156 | devices behind a Root Port only if the Root Port is reported as supporting\r | |
157 | ATS transactions.\r | |
158 | **/\r | |
159 | typedef struct {\r | |
160 | EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r | |
161 | /**\r | |
162 | - Bit[0]: ALL_PORTS:\r | |
163 | - If Set, indicates all PCI Express Root Ports in the specified\r | |
164 | PCI Segment supports ATS transactions.\r | |
165 | - If Clear, indicates ATS transactions are supported only on\r | |
166 | Root Ports identified through the Device Scope field.\r | |
167 | - Bits[7:1] Reserved.\r | |
168 | **/\r | |
169 | UINT8 Flags;\r | |
170 | UINT8 Reserved;\r | |
171 | ///\r | |
172 | /// The PCI Segment associated with this ATSR structure\r | |
173 | ///\r | |
174 | UINT16 SegmentNumber;\r | |
175 | } EFI_ACPI_DMAR_ATSR_HEADER;\r | |
176 | \r | |
177 | /**\r | |
178 | Remapping Hardware Static Affinity (RHSA) is an optional structure defined\r | |
179 | in section 8.6. This is intended to be used only on NUMA platforms with\r | |
180 | Remapping hardware units and memory spanned across multiple nodes.\r | |
181 | When used, there must be a RHSA structure for each Remapping hardware unit\r | |
182 | reported through DRHD structure.\r | |
183 | **/\r | |
184 | typedef struct {\r | |
185 | EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r | |
186 | UINT8 Reserved[4];\r | |
187 | ///\r | |
188 | /// Register Base Address of this Remap hardware unit reported in the\r | |
189 | /// corresponding DRHD structure.\r | |
190 | ///\r | |
191 | UINT64 RegisterBaseAddress;\r | |
192 | ///\r | |
193 | /// Proximity Domain to which the Remap hardware unit identified by the\r | |
194 | /// Register Base Address field belongs.\r | |
195 | ///\r | |
196 | UINT32 ProximityDomain;\r | |
197 | } EFI_ACPI_DMAR_RHSA_HEADER;\r | |
198 | \r | |
199 | /**\r | |
200 | An ACPI Name-space Device Declaration (ANDD) structure is defined in section\r | |
201 | 8.7 and uniquely represents an ACPI name-space enumerated device capable of\r | |
202 | issuing DMA requests in the platform. ANDD structures are used in conjunction\r | |
203 | with Device-Scope entries of type ACPI_NAMESPACE_DEVICE.\r | |
204 | **/\r | |
205 | typedef struct {\r | |
206 | EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r | |
207 | UINT8 Reserved[3];\r | |
208 | /**\r | |
209 | Each ACPI device enumerated through an ANDD structure must have a unique\r | |
210 | value for this field. To report an ACPI device with ACPI Device Number\r | |
211 | value of X, under the scope of a DRHD unit, a Device-Scope entry of type\r | |
212 | ACPI_NAMESPACE_DEVICE is used with value of X in the Enumeration ID field.\r | |
213 | The Start Bus Number and Path fields in the Device-Scope together\r | |
214 | provides the 16-bit source-id allocated by platform for the ACPI device.\r | |
215 | **/\r | |
216 | UINT8 AcpiDeviceNumber;\r | |
217 | } EFI_ACPI_DMAR_ANDD_HEADER;\r | |
218 | \r | |
219 | /**\r | |
220 | DMA Remapping Reporting Structure Header as defined in section 8.1\r | |
221 | This header will be followed by list of Remapping Structures listed below\r | |
222 | - DMA Remapping Hardware Unit Definition (DRHD)\r | |
223 | - Reserved Memory Region Reporting (RMRR)\r | |
224 | - Root Port ATS Capability Reporting (ATSR)\r | |
225 | - Remapping Hardware Static Affinity (RHSA)\r | |
226 | - ACPI Name-space Device Declaration (ANDD)\r | |
227 | These structure types must by reported in numerical order.\r | |
228 | i.e., All remapping structures of type 0 (DRHD) enumerated before remapping\r | |
229 | structures of type 1 (RMRR), and so forth.\r | |
230 | **/\r | |
231 | typedef struct {\r | |
232 | EFI_ACPI_DESCRIPTION_HEADER Header;\r | |
233 | /**\r | |
234 | This field indicates the maximum DMA physical addressability supported by\r | |
235 | this platform. The system address map reported by the BIOS indicates what\r | |
236 | portions of this addresses are populated. The Host Address Width (HAW) of\r | |
237 | the platform is computed as (N+1), where N is the value reported in this\r | |
238 | field.\r | |
239 | For example, for a platform supporting 40 bits of physical addressability,\r | |
240 | the value of 100111b is reported in this field.\r | |
241 | **/\r | |
242 | UINT8 HostAddressWidth;\r | |
243 | /**\r | |
244 | - Bit[0]: INTR_REMAP - If Clear, the platform does not support interrupt\r | |
245 | remapping. If Set, the platform supports interrupt remapping.\r | |
246 | - Bit[1]: X2APIC_OPT_OUT - For firmware compatibility reasons, platform\r | |
247 | firmware may Set this field to request system software to opt\r | |
248 | out of enabling Extended xAPIC (X2APIC) mode. This field is\r | |
249 | valid only when the INTR_REMAP field (bit 0) is Set.\r | |
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250 | - Bit[2]: DMA_CTRL_PLATFORM_OPT_IN_FLAG - Platform firmware is\r |
251 | recommended to Set this field to report any platform initiated\r | |
252 | DMA is restricted to only reserved memory regions (reported in\r | |
253 | RMRR structures) when transferring control to system software\r | |
254 | such as on ExitBootServices().\r | |
255 | - Bits[7:3] Reserved.\r | |
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256 | **/\r |
257 | UINT8 Flags;\r | |
258 | UINT8 Reserved[10];\r | |
259 | } EFI_ACPI_DMAR_HEADER;\r | |
260 | \r | |
261 | #pragma pack()\r | |
262 | \r | |
263 | #endif\r |