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a7ed1e2e | 1 | /** @file\r |
2 | Support for PCI 2.3 standard.\r | |
3 | \r | |
826a66d4 | 4 | Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r |
9df063a0 | 5 | This program and the accompanying materials \r |
a7ed1e2e | 6 | are licensed and made available under the terms and conditions of the BSD License \r |
7 | which accompanies this distribution. The full text of the license may be found at \r | |
af2dc6a7 | 8 | http://opensource.org/licenses/bsd-license.php. \r |
a7ed1e2e | 9 | \r |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
12 | \r | |
a7ed1e2e | 13 | **/\r |
14 | \r | |
42eedea9 | 15 | #ifndef _PCI23_H_\r |
16 | #define _PCI23_H_\r | |
a7ed1e2e | 17 | \r |
bc14bdb3 | 18 | #include <IndustryStandard/Pci22.h>\r |
19 | \r | |
20 | ///\r | |
af2dc6a7 | 21 | /// PCI_CLASS_MASS_STORAGE, Base Class 01h.\r |
bc14bdb3 | 22 | ///\r |
179d85c8 | 23 | ///@{\r |
24 | #define PCI_CLASS_MASS_STORAGE_ATA 0x05\r | |
25 | #define PCI_IF_MASS_STORAGE_SINGLE_DMA 0x20\r | |
26 | #define PCI_IF_MASS_STORAGE_CHAINED_DMA 0x30\r | |
27 | ///@}\r | |
28 | \r | |
826a66d4 RN |
29 | ///\r |
30 | /// PCI_CLASS_NETWORK, Base Class 02h.\r | |
31 | ///\r | |
32 | ///@{\r | |
33 | #define PCI_CLASS_NETWORK_WORLDFIP 0x05\r | |
34 | #define PCI_CLASS_NETWORK_PICMG_MULTI_COMPUTING 0x06\r | |
35 | ///@}\r | |
36 | \r | |
37 | ///\r | |
38 | /// PCI_CLASS_BRIDGE, Base Class 06h.\r | |
39 | ///\r | |
40 | ///@{\r | |
41 | #define PCI_CLASS_BRIDGE_SEMI_TRANSPARENT_P2P 0x09\r | |
42 | #define PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_PRIMARY 0x40\r | |
43 | #define PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_SECONDARY 0x80\r | |
44 | #define PCI_CLASS_BRIDGE_INFINIBAND_TO_PCI 0x0A\r | |
45 | ///@}\r | |
46 | \r | |
47 | ///\r | |
48 | /// PCI_CLASS_SCC, Base Class 07h.\r | |
49 | ///\r | |
50 | ///@{\r | |
51 | #define PCI_SUBCLASS_GPIB 0x04\r | |
52 | #define PCI_SUBCLASS_SMART_CARD 0x05\r | |
53 | ///@}\r | |
54 | \r | |
179d85c8 | 55 | ///\r |
af2dc6a7 | 56 | /// PCI_CLASS_SERIAL, Base Class 0Ch.\r |
179d85c8 | 57 | ///\r |
58 | ///@{\r | |
59 | #define PCI_IF_EHCI 0x20\r | |
60 | #define PCI_CLASS_SERIAL_IB 0x06\r | |
826a66d4 RN |
61 | #define PCI_CLASS_SERIAL_IPMI 0x07\r |
62 | #define PCI_IF_IPMI_SMIC 0x00\r | |
63 | #define PCI_IF_IPMI_KCS 0x01 ///< Keyboard Controller Style\r | |
64 | #define PCI_IF_IPMI_BT 0x02 ///< Block Transfer\r | |
65 | #define PCI_CLASS_SERIAL_SERCOS 0x08\r | |
66 | #define PCI_CLASS_SERIAL_CANBUS 0x09\r | |
67 | ///@}\r | |
68 | \r | |
69 | ///\r | |
70 | /// PCI_CLASS_WIRELESS, Base Class 0Dh.\r | |
71 | ///\r | |
72 | ///@{\r | |
73 | #define PCI_SUBCLASS_BLUETOOTH 0x11\r | |
74 | #define PCI_SUBCLASS_BROADBAND 0x12\r | |
75 | ///@}\r | |
76 | \r | |
77 | ///\r | |
78 | /// PCI_CLASS_DPIO, Base Class 11h.\r | |
79 | ///\r | |
80 | ///@{\r | |
81 | #define PCI_SUBCLASS_PERFORMANCE_COUNTERS 0x01\r | |
82 | #define PCI_SUBCLASS_COMMUNICATION_SYNCHRONIZATION 0x10\r | |
83 | #define PCI_SUBCLASS_MANAGEMENT_CARD 0x20\r | |
179d85c8 | 84 | ///@}\r |
a7ed1e2e | 85 | \r |
bc14bdb3 | 86 | ///\r |
87 | /// defined in PCI Express Spec.\r | |
88 | ///\r | |
a7ed1e2e | 89 | #define PCI_EXP_MAX_CONFIG_OFFSET 0x1000\r |
a7ed1e2e | 90 | \r |
a2461f6b | 91 | ///\r |
af2dc6a7 | 92 | /// PCI Capability List IDs and records.\r |
a2461f6b | 93 | ///\r |
bc14bdb3 | 94 | #define EFI_PCI_CAPABILITY_ID_PCIX 0x07\r |
95 | \r | |
766f4bc1 | 96 | #pragma pack(1)\r |
bc14bdb3 | 97 | ///\r |
427987f5 | 98 | /// PCI-X Capabilities List, \r |
af2dc6a7 | 99 | /// Section 7.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.\r |
bc14bdb3 | 100 | ///\r |
101 | typedef struct {\r | |
102 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
103 | UINT16 CommandReg;\r | |
104 | UINT32 StatusReg;\r | |
105 | } EFI_PCI_CAPABILITY_PCIX;\r | |
106 | \r | |
427987f5 | 107 | ///\r |
108 | /// PCI-X Bridge Capabilities List, \r | |
af2dc6a7 | 109 | /// Section 8.6.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.\r |
bc14bdb3 | 110 | ///\r |
111 | typedef struct {\r | |
112 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
113 | UINT16 SecStatusReg;\r | |
114 | UINT32 StatusReg;\r | |
115 | UINT32 SplitTransCtrlRegUp;\r | |
116 | UINT32 SplitTransCtrlRegDn;\r | |
117 | } EFI_PCI_CAPABILITY_PCIX_BRDG;\r | |
118 | \r | |
766f4bc1 | 119 | #pragma pack()\r |
120 | \r | |
bc14bdb3 | 121 | #define PCI_CODE_TYPE_EFI_IMAGE 0x03\r |
a7ed1e2e | 122 | \r |
123 | #endif\r |