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533403e6 | 1 | /** @file\r |
2 | Support for the latest PCI standard.\r | |
3 | \r | |
9095d37b LG |
4 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r |
5 | (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>\r | |
9344f092 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
533403e6 | 7 | \r |
8 | **/\r | |
9 | \r | |
10 | #ifndef _PCIEXPRESS21_H_\r | |
11 | #define _PCIEXPRESS21_H_\r | |
12 | \r | |
cbedba86 RN |
13 | #include <IndustryStandard/Pci30.h>\r |
14 | \r | |
c9c27019 RN |
15 | /**\r |
16 | Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an\r | |
17 | ECAM (Enhanced Configuration Access Mechanism) address. The unused upper bits\r | |
18 | of Bus, Device, Function and Register are stripped prior to the generation of\r | |
19 | the address.\r | |
20 | \r | |
21 | @param Bus PCI Bus number. Range 0..255.\r | |
22 | @param Device PCI Device number. Range 0..31.\r | |
23 | @param Function PCI Function number. Range 0..7.\r | |
24 | @param Register PCI Register number. Range 0..4095.\r | |
25 | \r | |
26 | @return The encode ECAM address.\r | |
27 | \r | |
28 | **/\r | |
29 | #define PCI_ECAM_ADDRESS(Bus,Device,Function,Offset) \\r | |
30 | (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r | |
31 | \r | |
cbedba86 RN |
32 | #pragma pack(1)\r |
33 | ///\r | |
34 | /// PCI Express Capability Structure\r | |
35 | ///\r | |
36 | typedef union {\r | |
37 | struct {\r | |
38 | UINT16 Version : 4;\r | |
39 | UINT16 DevicePortType : 4;\r | |
40 | UINT16 SlotImplemented : 1;\r | |
41 | UINT16 InterruptMessageNumber : 5;\r | |
42 | UINT16 Undefined : 1;\r | |
43 | UINT16 Reserved : 1;\r | |
44 | } Bits;\r | |
45 | UINT16 Uint16;\r | |
46 | } PCI_REG_PCIE_CAPABILITY;\r | |
47 | \r | |
48 | #define PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT 0\r | |
49 | #define PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT 1\r | |
50 | #define PCIE_DEVICE_PORT_TYPE_ROOT_PORT 4\r | |
51 | #define PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT 5\r | |
52 | #define PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT 6\r | |
53 | #define PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE 7\r | |
54 | #define PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE 8\r | |
55 | #define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT 9\r | |
56 | #define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR 10\r | |
57 | \r | |
58 | typedef union {\r | |
59 | struct {\r | |
60 | UINT32 MaxPayloadSize : 3;\r | |
61 | UINT32 PhantomFunctions : 2;\r | |
62 | UINT32 ExtendedTagField : 1;\r | |
63 | UINT32 EndpointL0sAcceptableLatency : 3;\r | |
64 | UINT32 EndpointL1AcceptableLatency : 3;\r | |
65 | UINT32 Undefined : 3;\r | |
66 | UINT32 RoleBasedErrorReporting : 1;\r | |
67 | UINT32 Reserved : 2;\r | |
68 | UINT32 CapturedSlotPowerLimitValue : 8;\r | |
69 | UINT32 CapturedSlotPowerLimitScale : 2;\r | |
70 | UINT32 FunctionLevelReset : 1;\r | |
71 | UINT32 Reserved2 : 3;\r | |
72 | } Bits;\r | |
73 | UINT32 Uint32;\r | |
74 | } PCI_REG_PCIE_DEVICE_CAPABILITY;\r | |
75 | \r | |
76 | typedef union {\r | |
77 | struct {\r | |
78 | UINT16 CorrectableError : 1;\r | |
79 | UINT16 NonFatalError : 1;\r | |
80 | UINT16 FatalError : 1;\r | |
81 | UINT16 UnsupportedRequest : 1;\r | |
82 | UINT16 RelaxedOrdering : 1;\r | |
83 | UINT16 MaxPayloadSize : 3;\r | |
84 | UINT16 ExtendedTagField : 1;\r | |
85 | UINT16 PhantomFunctions : 1;\r | |
86 | UINT16 AuxPower : 1;\r | |
87 | UINT16 NoSnoop : 1;\r | |
88 | UINT16 MaxReadRequestSize : 3;\r | |
89 | UINT16 BridgeConfigurationRetryOrFunctionLevelReset : 1;\r | |
90 | } Bits;\r | |
91 | UINT16 Uint16;\r | |
92 | } PCI_REG_PCIE_DEVICE_CONTROL;\r | |
93 | \r | |
95fb7588 JA |
94 | #define PCIE_MAX_PAYLOAD_SIZE_128B 0\r |
95 | #define PCIE_MAX_PAYLOAD_SIZE_256B 1\r | |
96 | #define PCIE_MAX_PAYLOAD_SIZE_512B 2\r | |
97 | #define PCIE_MAX_PAYLOAD_SIZE_1024B 3\r | |
98 | #define PCIE_MAX_PAYLOAD_SIZE_2048B 4\r | |
99 | #define PCIE_MAX_PAYLOAD_SIZE_4096B 5\r | |
100 | #define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6\r | |
101 | #define PCIE_MAX_PAYLOAD_SIZE_RVSD2 7\r | |
102 | \r | |
103 | #define PCIE_MAX_READ_REQ_SIZE_128B 0\r | |
104 | #define PCIE_MAX_READ_REQ_SIZE_256B 1\r | |
105 | #define PCIE_MAX_READ_REQ_SIZE_512B 2\r | |
106 | #define PCIE_MAX_READ_REQ_SIZE_1024B 3\r | |
107 | #define PCIE_MAX_READ_REQ_SIZE_2048B 4\r | |
108 | #define PCIE_MAX_READ_REQ_SIZE_4096B 5\r | |
109 | #define PCIE_MAX_READ_REQ_SIZE_RVSD1 6\r | |
110 | #define PCIE_MAX_READ_REQ_SIZE_RVSD2 7\r | |
111 | \r | |
cbedba86 RN |
112 | typedef union {\r |
113 | struct {\r | |
114 | UINT16 CorrectableError : 1;\r | |
115 | UINT16 NonFatalError : 1;\r | |
116 | UINT16 FatalError : 1;\r | |
117 | UINT16 UnsupportedRequest : 1;\r | |
118 | UINT16 AuxPower : 1;\r | |
119 | UINT16 TransactionsPending : 1;\r | |
120 | UINT16 Reserved : 10;\r | |
121 | } Bits;\r | |
122 | UINT16 Uint16;\r | |
123 | } PCI_REG_PCIE_DEVICE_STATUS;\r | |
124 | \r | |
125 | typedef union {\r | |
126 | struct {\r | |
127 | UINT32 MaxLinkSpeed : 4;\r | |
128 | UINT32 MaxLinkWidth : 6;\r | |
129 | UINT32 Aspm : 2;\r | |
130 | UINT32 L0sExitLatency : 3;\r | |
131 | UINT32 L1ExitLatency : 3;\r | |
132 | UINT32 ClockPowerManagement : 1;\r | |
133 | UINT32 SurpriseDownError : 1;\r | |
134 | UINT32 DataLinkLayerLinkActive : 1;\r | |
135 | UINT32 LinkBandwidthNotification : 1;\r | |
136 | UINT32 AspmOptionalityCompliance : 1;\r | |
137 | UINT32 Reserved : 1;\r | |
138 | UINT32 PortNumber : 8;\r | |
139 | } Bits;\r | |
140 | UINT32 Uint32;\r | |
141 | } PCI_REG_PCIE_LINK_CAPABILITY;\r | |
142 | \r | |
143 | #define PCIE_LINK_ASPM_L0S BIT0\r | |
144 | #define PCIE_LINK_ASPM_L1 BIT1\r | |
145 | \r | |
146 | typedef union {\r | |
147 | struct {\r | |
148 | UINT16 AspmControl : 2;\r | |
149 | UINT16 Reserved : 1;\r | |
150 | UINT16 ReadCompletionBoundary : 1;\r | |
151 | UINT16 LinkDisable : 1;\r | |
152 | UINT16 RetrainLink : 1;\r | |
153 | UINT16 CommonClockConfiguration : 1;\r | |
154 | UINT16 ExtendedSynch : 1;\r | |
155 | UINT16 ClockPowerManagement : 1;\r | |
156 | UINT16 HardwareAutonomousWidthDisable : 1;\r | |
157 | UINT16 LinkBandwidthManagementInterrupt : 1;\r | |
158 | UINT16 LinkAutonomousBandwidthInterrupt : 1;\r | |
159 | } Bits;\r | |
160 | UINT16 Uint16;\r | |
161 | } PCI_REG_PCIE_LINK_CONTROL;\r | |
162 | \r | |
163 | typedef union {\r | |
164 | struct {\r | |
165 | UINT16 CurrentLinkSpeed : 4;\r | |
166 | UINT16 NegotiatedLinkWidth : 6;\r | |
167 | UINT16 Undefined : 1;\r | |
168 | UINT16 LinkTraining : 1;\r | |
169 | UINT16 SlotClockConfiguration : 1;\r | |
170 | UINT16 DataLinkLayerLinkActive : 1;\r | |
171 | UINT16 LinkBandwidthManagement : 1;\r | |
172 | UINT16 LinkAutonomousBandwidth : 1;\r | |
173 | } Bits;\r | |
174 | UINT16 Uint16;\r | |
175 | } PCI_REG_PCIE_LINK_STATUS;\r | |
176 | \r | |
177 | typedef union {\r | |
178 | struct {\r | |
179 | UINT32 AttentionButton : 1;\r | |
180 | UINT32 PowerController : 1;\r | |
181 | UINT32 MrlSensor : 1;\r | |
182 | UINT32 AttentionIndicator : 1;\r | |
183 | UINT32 PowerIndicator : 1;\r | |
184 | UINT32 HotPlugSurprise : 1;\r | |
185 | UINT32 HotPlugCapable : 1;\r | |
186 | UINT32 SlotPowerLimitValue : 8;\r | |
187 | UINT32 SlotPowerLimitScale : 2;\r | |
188 | UINT32 ElectromechanicalInterlock : 1;\r | |
189 | UINT32 NoCommandCompleted : 1;\r | |
190 | UINT32 PhysicalSlotNumber : 13;\r | |
191 | } Bits;\r | |
192 | UINT32 Uint32;\r | |
193 | } PCI_REG_PCIE_SLOT_CAPABILITY;\r | |
194 | \r | |
195 | typedef union {\r | |
196 | struct {\r | |
400a5973 RN |
197 | UINT16 AttentionButtonPressed : 1;\r |
198 | UINT16 PowerFaultDetected : 1;\r | |
199 | UINT16 MrlSensorChanged : 1;\r | |
200 | UINT16 PresenceDetectChanged : 1;\r | |
201 | UINT16 CommandCompletedInterrupt : 1;\r | |
202 | UINT16 HotPlugInterrupt : 1;\r | |
203 | UINT16 AttentionIndicator : 2;\r | |
204 | UINT16 PowerIndicator : 2;\r | |
205 | UINT16 PowerController : 1;\r | |
206 | UINT16 ElectromechanicalInterlock : 1;\r | |
207 | UINT16 DataLinkLayerStateChanged : 1;\r | |
208 | UINT16 Reserved : 3;\r | |
cbedba86 RN |
209 | } Bits;\r |
210 | UINT16 Uint16;\r | |
211 | } PCI_REG_PCIE_SLOT_CONTROL;\r | |
212 | \r | |
213 | typedef union {\r | |
214 | struct {\r | |
215 | UINT16 AttentionButtonPressed : 1;\r | |
216 | UINT16 PowerFaultDetected : 1;\r | |
217 | UINT16 MrlSensorChanged : 1;\r | |
218 | UINT16 PresenceDetectChanged : 1;\r | |
219 | UINT16 CommandCompleted : 1;\r | |
220 | UINT16 MrlSensor : 1;\r | |
221 | UINT16 PresenceDetect : 1;\r | |
222 | UINT16 ElectromechanicalInterlock : 1;\r | |
223 | UINT16 DataLinkLayerStateChanged : 1;\r | |
224 | UINT16 Reserved : 7;\r | |
225 | } Bits;\r | |
226 | UINT16 Uint16;\r | |
227 | } PCI_REG_PCIE_SLOT_STATUS;\r | |
228 | \r | |
229 | typedef union {\r | |
230 | struct {\r | |
231 | UINT16 SystemErrorOnCorrectableError : 1;\r | |
232 | UINT16 SystemErrorOnNonFatalError : 1;\r | |
233 | UINT16 SystemErrorOnFatalError : 1;\r | |
234 | UINT16 PmeInterrupt : 1;\r | |
235 | UINT16 CrsSoftwareVisibility : 1;\r | |
236 | UINT16 Reserved : 11;\r | |
237 | } Bits;\r | |
238 | UINT16 Uint16;\r | |
239 | } PCI_REG_PCIE_ROOT_CONTROL;\r | |
240 | \r | |
241 | typedef union {\r | |
242 | struct {\r | |
243 | UINT16 CrsSoftwareVisibility : 1;\r | |
244 | UINT16 Reserved : 15;\r | |
245 | } Bits;\r | |
246 | UINT16 Uint16;\r | |
247 | } PCI_REG_PCIE_ROOT_CAPABILITY;\r | |
248 | \r | |
249 | typedef union {\r | |
250 | struct {\r | |
251 | UINT32 PmeRequesterId : 16;\r | |
252 | UINT32 PmeStatus : 1;\r | |
253 | UINT32 PmePending : 1;\r | |
254 | UINT32 Reserved : 14;\r | |
255 | } Bits;\r | |
256 | UINT32 Uint32;\r | |
257 | } PCI_REG_PCIE_ROOT_STATUS;\r | |
258 | \r | |
259 | typedef union {\r | |
260 | struct {\r | |
261 | UINT32 CompletionTimeoutRanges : 4;\r | |
262 | UINT32 CompletionTimeoutDisable : 1;\r | |
263 | UINT32 AriForwarding : 1;\r | |
264 | UINT32 AtomicOpRouting : 1;\r | |
265 | UINT32 AtomicOp32Completer : 1;\r | |
266 | UINT32 AtomicOp64Completer : 1;\r | |
267 | UINT32 Cas128Completer : 1;\r | |
268 | UINT32 NoRoEnabledPrPrPassing : 1;\r | |
269 | UINT32 LtrMechanism : 1;\r | |
270 | UINT32 TphCompleter : 2;\r | |
95fb7588 JA |
271 | UINT32 LnSystemCLS : 2;\r |
272 | UINT32 TenBitTagCompleterSupported : 1;\r | |
273 | UINT32 TenBitTagRequesterSupported : 1;\r | |
cbedba86 RN |
274 | UINT32 Obff : 2;\r |
275 | UINT32 ExtendedFmtField : 1;\r | |
276 | UINT32 EndEndTlpPrefix : 1;\r | |
277 | UINT32 MaxEndEndTlpPrefixes : 2;\r | |
95fb7588 JA |
278 | UINT32 EmergencyPowerReductionSupported : 2;\r |
279 | UINT32 EmergencyPowerReductionInitializationRequired : 1;\r | |
280 | UINT32 Reserved3 : 4;\r | |
281 | UINT32 FrsSupported : 1;\r | |
cbedba86 RN |
282 | } Bits;\r |
283 | UINT32 Uint32;\r | |
284 | } PCI_REG_PCIE_DEVICE_CAPABILITY2;\r | |
285 | \r | |
95fb7588 JA |
286 | #define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0\r |
287 | #define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1\r | |
288 | #define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2\r | |
289 | #define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3\r | |
290 | #define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6\r | |
291 | #define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED 7\r | |
292 | #define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED 14\r | |
293 | #define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15\r | |
294 | \r | |
cbedba86 RN |
295 | #define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0\r |
296 | #define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1\r | |
297 | \r | |
298 | typedef union {\r | |
299 | struct {\r | |
300 | UINT16 CompletionTimeoutValue : 4;\r | |
301 | UINT16 CompletionTimeoutDisable : 1;\r | |
302 | UINT16 AriForwarding : 1;\r | |
303 | UINT16 AtomicOpRequester : 1;\r | |
304 | UINT16 AtomicOpEgressBlocking : 1;\r | |
305 | UINT16 IdoRequest : 1;\r | |
306 | UINT16 IdoCompletion : 1;\r | |
665afccc | 307 | UINT16 LtrMechanism : 1;\r |
95fb7588 JA |
308 | UINT16 EmergencyPowerReductionRequest : 1;\r |
309 | UINT16 TenBitTagRequesterEnable : 1;\r | |
cbedba86 RN |
310 | UINT16 Obff : 2;\r |
311 | UINT16 EndEndTlpPrefixBlocking : 1;\r | |
312 | } Bits;\r | |
313 | UINT16 Uint16;\r | |
314 | } PCI_REG_PCIE_DEVICE_CONTROL2;\r | |
315 | \r | |
316 | #define PCIE_COMPLETION_TIMEOUT_50US_50MS 0\r | |
317 | #define PCIE_COMPLETION_TIMEOUT_50US_100US 1\r | |
318 | #define PCIE_COMPLETION_TIMEOUT_1MS_10MS 2\r | |
319 | #define PCIE_COMPLETION_TIMEOUT_16MS_55MS 5\r | |
320 | #define PCIE_COMPLETION_TIMEOUT_65MS_210MS 6\r | |
321 | #define PCIE_COMPLETION_TIMEOUT_260MS_900MS 9\r | |
322 | #define PCIE_COMPLETION_TIMEOUT_1S_3_5S 10\r | |
323 | #define PCIE_COMPLETION_TIMEOUT_4S_13S 13\r | |
324 | #define PCIE_COMPLETION_TIMEOUT_17S_64S 14\r | |
325 | \r | |
326 | #define PCIE_DEVICE_CONTROL_OBFF_DISABLED 0\r | |
327 | #define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_A 1\r | |
328 | #define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_B 2\r | |
329 | #define PCIE_DEVICE_CONTROL_OBFF_WAKE 3\r | |
330 | \r | |
331 | typedef union {\r | |
332 | struct {\r | |
333 | UINT32 Reserved : 1;\r | |
334 | UINT32 LinkSpeedsVector : 7;\r | |
335 | UINT32 Crosslink : 1;\r | |
336 | UINT32 Reserved2 : 23;\r | |
337 | } Bits;\r | |
338 | UINT32 Uint32;\r | |
339 | } PCI_REG_PCIE_LINK_CAPABILITY2;\r | |
340 | \r | |
341 | typedef union {\r | |
342 | struct {\r | |
343 | UINT16 TargetLinkSpeed : 4;\r | |
344 | UINT16 EnterCompliance : 1;\r | |
345 | UINT16 HardwareAutonomousSpeedDisable : 1;\r | |
346 | UINT16 SelectableDeemphasis : 1;\r | |
347 | UINT16 TransmitMargin : 3;\r | |
348 | UINT16 EnterModifiedCompliance : 1;\r | |
349 | UINT16 ComplianceSos : 1;\r | |
350 | UINT16 CompliancePresetDeemphasis : 4;\r | |
351 | } Bits;\r | |
352 | UINT16 Uint16;\r | |
353 | } PCI_REG_PCIE_LINK_CONTROL2;\r | |
354 | \r | |
355 | typedef union {\r | |
356 | struct {\r | |
357 | UINT16 CurrentDeemphasisLevel : 1;\r | |
358 | UINT16 EqualizationComplete : 1;\r | |
359 | UINT16 EqualizationPhase1Successful : 1;\r | |
360 | UINT16 EqualizationPhase2Successful : 1;\r | |
361 | UINT16 EqualizationPhase3Successful : 1;\r | |
362 | UINT16 LinkEqualizationRequest : 1;\r | |
363 | UINT16 Reserved : 10;\r | |
364 | } Bits;\r | |
365 | UINT16 Uint16;\r | |
366 | } PCI_REG_PCIE_LINK_STATUS2;\r | |
367 | \r | |
368 | typedef struct {\r | |
369 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
370 | PCI_REG_PCIE_CAPABILITY Capability;\r | |
371 | PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCapability;\r | |
372 | PCI_REG_PCIE_DEVICE_CONTROL DeviceControl;\r | |
373 | PCI_REG_PCIE_DEVICE_STATUS DeviceStatus;\r | |
374 | PCI_REG_PCIE_LINK_CAPABILITY LinkCapability;\r | |
375 | PCI_REG_PCIE_LINK_CONTROL LinkControl;\r | |
376 | PCI_REG_PCIE_LINK_STATUS LinkStatus;\r | |
377 | PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability;\r | |
378 | PCI_REG_PCIE_SLOT_CONTROL SlotControl;\r | |
379 | PCI_REG_PCIE_SLOT_STATUS SlotStatus;\r | |
380 | PCI_REG_PCIE_ROOT_CONTROL RootControl;\r | |
381 | PCI_REG_PCIE_ROOT_CAPABILITY RootCapability;\r | |
382 | PCI_REG_PCIE_ROOT_STATUS RootStatus;\r | |
383 | PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCapability2;\r | |
384 | PCI_REG_PCIE_DEVICE_CONTROL2 DeviceControl2;\r | |
385 | UINT16 DeviceStatus2;\r | |
386 | PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2;\r | |
387 | PCI_REG_PCIE_LINK_CONTROL2 LinkControl2;\r | |
388 | PCI_REG_PCIE_LINK_STATUS2 LinkStatus2;\r | |
389 | UINT32 SlotCapability2;\r | |
390 | UINT16 SlotControl2;\r | |
391 | UINT16 SlotStatus2;\r | |
392 | } PCI_CAPABILITY_PCIEXP;\r | |
393 | \r | |
533403e6 | 394 | #define EFI_PCIE_CAPABILITY_BASE_OFFSET 0x100\r |
395 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY 0x10\r | |
396 | #define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET 0x24\r | |
397 | #define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING 0x20\r | |
398 | #define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET 0x28\r | |
399 | #define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING 0x20\r | |
400 | \r | |
401 | //\r | |
402 | // for SR-IOV\r | |
403 | //\r | |
404 | #define EFI_PCIE_CAPABILITY_ID_ARI 0x0E\r | |
405 | #define EFI_PCIE_CAPABILITY_ID_ATS 0x0F\r | |
406 | #define EFI_PCIE_CAPABILITY_ID_SRIOV 0x10\r | |
407 | #define EFI_PCIE_CAPABILITY_ID_MRIOV 0x11\r | |
408 | \r | |
409 | typedef struct {\r | |
410 | UINT32 CapabilityHeader;\r | |
411 | UINT32 Capability;\r | |
412 | UINT16 Control;\r | |
413 | UINT16 Status;\r | |
414 | UINT16 InitialVFs;\r | |
415 | UINT16 TotalVFs;\r | |
416 | UINT16 NumVFs;\r | |
417 | UINT8 FunctionDependencyLink;\r | |
418 | UINT8 Reserved0;\r | |
419 | UINT16 FirstVFOffset;\r | |
420 | UINT16 VFStride;\r | |
421 | UINT16 Reserved1;\r | |
422 | UINT16 VFDeviceID;\r | |
423 | UINT32 SupportedPageSize;\r | |
424 | UINT32 SystemPageSize;\r | |
425 | UINT32 VFBar[6];\r | |
426 | UINT32 VFMigrationStateArrayOffset;\r | |
427 | } SR_IOV_CAPABILITY_REGISTER;\r | |
428 | \r | |
429 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_CAPABILITIES 0x04\r | |
430 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL 0x08\r | |
431 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_STATUS 0x0A\r | |
432 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS 0x0C\r | |
433 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_TOTALVFS 0x0E\r | |
434 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_NUMVFS 0x10\r | |
435 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_FUNCTION_DEPENDENCY_LINK 0x12\r | |
436 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF 0x14\r | |
437 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE 0x16\r | |
438 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_VFDEVICEID 0x1A\r | |
439 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE 0x1C\r | |
440 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE 0x20\r | |
441 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0 0x24\r | |
442 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR1 0x28\r | |
443 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR2 0x2C\r | |
444 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR3 0x30\r | |
445 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR4 0x34\r | |
446 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5 0x38\r | |
447 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_VF_MIGRATION_STATE 0x3C\r | |
448 | \r | |
a1d20250 JC |
449 | typedef struct {\r |
450 | UINT32 CapabilityId:16;\r | |
451 | UINT32 CapabilityVersion:4;\r | |
452 | UINT32 NextCapabilityOffset:12;\r | |
453 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER;\r | |
454 | \r | |
455 | #define PCI_EXP_EXT_HDR PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER\r | |
456 | \r | |
457 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID 0x0001\r | |
458 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1 0x1\r | |
459 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2 0x2\r | |
460 | \r | |
cbedba86 RN |
461 | typedef union {\r |
462 | struct {\r | |
463 | UINT32 Undefined : 1;\r | |
464 | UINT32 Reserved : 3;\r | |
465 | UINT32 DataLinkProtocolError : 1;\r | |
466 | UINT32 SurpriseDownError : 1;\r | |
467 | UINT32 Reserved2 : 6;\r | |
468 | UINT32 PoisonedTlp : 1;\r | |
469 | UINT32 FlowControlProtocolError : 1;\r | |
470 | UINT32 CompletionTimeout : 1;\r | |
471 | UINT32 CompleterAbort : 1;\r | |
472 | UINT32 UnexpectedCompletion : 1;\r | |
473 | UINT32 ReceiverOverflow : 1;\r | |
474 | UINT32 MalformedTlp : 1;\r | |
475 | UINT32 EcrcError : 1;\r | |
476 | UINT32 UnsupportedRequestError : 1;\r | |
477 | UINT32 AcsVoilation : 1;\r | |
478 | UINT32 UncorrectableInternalError : 1;\r | |
479 | UINT32 McBlockedTlp : 1;\r | |
480 | UINT32 AtomicOpEgressBlocked : 1;\r | |
481 | UINT32 TlpPrefixBlockedError : 1;\r | |
482 | UINT32 Reserved3 : 6;\r | |
483 | } Bits;\r | |
484 | UINT32 Uint32;\r | |
485 | } PCI_EXPRESS_REG_UNCORRECTABLE_ERROR;\r | |
486 | \r | |
a1d20250 JC |
487 | typedef struct {\r |
488 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
cbedba86 RN |
489 | PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorStatus;\r |
490 | PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorMask;\r | |
491 | PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorSeverity;\r | |
a1d20250 JC |
492 | UINT32 CorrectableErrorStatus;\r |
493 | UINT32 CorrectableErrorMask;\r | |
494 | UINT32 AdvancedErrorCapabilitiesAndControl;\r | |
0a38a95a | 495 | UINT32 HeaderLog[4];\r |
a1d20250 JC |
496 | UINT32 RootErrorCommand;\r |
497 | UINT32 RootErrorStatus;\r | |
498 | UINT16 ErrorSourceIdentification;\r | |
499 | UINT16 CorrectableErrorSourceIdentification;\r | |
500 | UINT32 TlpPrefixLog[4];\r | |
501 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING;\r | |
502 | \r | |
503 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID 0x0002\r | |
504 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_MFVC 0x0009\r | |
505 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_VER1 0x1\r | |
506 | \r | |
507 | typedef struct {\r | |
508 | UINT32 VcResourceCapability:24;\r | |
509 | UINT32 PortArbTableOffset:8;\r | |
510 | UINT32 VcResourceControl;\r | |
511 | UINT16 Reserved1;\r | |
512 | UINT16 VcResourceStatus;\r | |
513 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC;\r | |
514 | \r | |
515 | typedef struct {\r | |
516 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
517 | UINT32 ExtendedVcCount:3;\r | |
518 | UINT32 PortVcCapability1:29;\r | |
519 | UINT32 PortVcCapability2:24;\r | |
520 | UINT32 VcArbTableOffset:8;\r | |
521 | UINT16 PortVcControl;\r | |
522 | UINT16 PortVcStatus;\r | |
523 | PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC Capability[1];\r | |
524 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY;\r | |
525 | \r | |
526 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID 0x0003\r | |
527 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_VER1 0x1\r | |
528 | \r | |
529 | typedef struct {\r | |
530 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
531 | UINT64 SerialNumber;\r | |
532 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER;\r | |
533 | \r | |
534 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID 0x0005\r | |
535 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_VER1 0x1\r | |
536 | \r | |
537 | typedef struct {\r | |
538 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
539 | UINT32 ElementSelfDescription;\r | |
540 | UINT32 Reserved;\r | |
541 | UINT32 LinkEntry[1];\r | |
542 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION;\r | |
543 | \r | |
544 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(LINK_DECLARATION) (UINT8)(((LINK_DECLARATION->ElementSelfDescription)&0x0000ff00)>>8)\r | |
545 | \r | |
546 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID 0x0006\r | |
547 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_VER1 0x1\r | |
548 | \r | |
549 | typedef struct {\r | |
550 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
551 | UINT32 RootComplexLinkCapabilities;\r | |
552 | UINT16 RootComplexLinkControl;\r | |
553 | UINT16 RootComplexLinkStatus;\r | |
554 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL;\r | |
555 | \r | |
556 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID 0x0004\r | |
557 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_VER1 0x1\r | |
558 | \r | |
559 | typedef struct {\r | |
560 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
561 | UINT32 DataSelect:8;\r | |
562 | UINT32 Reserved:24;\r | |
563 | UINT32 Data;\r | |
564 | UINT32 PowerBudgetCapability:1;\r | |
565 | UINT32 Reserved2:7;\r | |
566 | UINT32 Reserved3:24;\r | |
567 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING;\r | |
568 | \r | |
569 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID 0x000D\r | |
570 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_VER1 0x1\r | |
571 | \r | |
572 | typedef struct {\r | |
573 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
574 | UINT16 AcsCapability;\r | |
575 | UINT16 AcsControl;\r | |
576 | UINT8 EgressControlVectorArray[1];\r | |
577 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED;\r | |
578 | \r | |
579 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x00000020))\r | |
580 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x0000FF00))\r | |
581 | \r | |
582 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID 0x0007\r | |
583 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_VER1 0x1\r | |
584 | \r | |
585 | typedef struct {\r | |
586 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
587 | UINT32 AssociationBitmap;\r | |
588 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION;\r | |
589 | \r | |
590 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID 0x0008\r | |
591 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_VER1 0x1\r | |
592 | \r | |
593 | typedef PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTI_FUNCTION_VIRTUAL_CHANNEL_CAPABILITY;\r | |
594 | \r | |
595 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID 0x000B\r | |
596 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_VER1 0x1\r | |
597 | \r | |
598 | typedef struct {\r | |
599 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
600 | UINT32 VendorSpecificHeader;\r | |
601 | UINT8 VendorSpecific[1];\r | |
602 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC;\r | |
603 | \r | |
604 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(VENDOR) (UINT16)(((VENDOR->VendorSpecificHeader)&0xFFF00000)>>20)\r | |
605 | \r | |
606 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID 0x000A\r | |
607 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_VER1 0x1\r | |
608 | \r | |
609 | typedef struct {\r | |
610 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
611 | UINT16 VendorId;\r | |
612 | UINT16 DeviceId;\r | |
613 | UINT32 RcrbCapabilities;\r | |
614 | UINT32 RcrbControl;\r | |
615 | UINT32 Reserved;\r | |
616 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER;\r | |
617 | \r | |
618 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID 0x0012\r | |
619 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_VER1 0x1\r | |
620 | \r | |
621 | typedef struct {\r | |
622 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
623 | UINT16 MultiCastCapability;\r | |
624 | UINT16 MulticastControl;\r | |
625 | UINT64 McBaseAddress;\r | |
626 | UINT64 McReceiveAddress;\r | |
627 | UINT64 McBlockAll;\r | |
628 | UINT64 McBlockUntranslated;\r | |
629 | UINT64 McOverlayBar;\r | |
630 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST;\r | |
631 | \r | |
632 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID 0x0015\r | |
633 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_VER1 0x1\r | |
634 | \r | |
635 | typedef struct {\r | |
636 | UINT32 ResizableBarCapability;\r | |
637 | UINT16 ResizableBarControl;\r | |
638 | UINT16 Reserved;\r | |
639 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY;\r | |
640 | \r | |
641 | typedef struct {\r | |
642 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
643 | PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY Capability[1];\r | |
644 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR;\r | |
645 | \r | |
e1c9edd6 JC |
646 | #define GET_NUMBER_RESIZABLE_BARS(x) (((x->Capability[0].ResizableBarControl) & 0xE0) >> 5)\r |
647 | \r | |
a1d20250 JC |
648 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID 0x000E\r |
649 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_VER1 0x1\r | |
650 | \r | |
651 | typedef struct {\r | |
652 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
653 | UINT16 AriCapability;\r | |
654 | UINT16 AriControl;\r | |
655 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY;\r | |
656 | \r | |
657 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID 0x0016\r | |
658 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_VER1 0x1\r | |
659 | \r | |
660 | typedef struct {\r | |
661 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
662 | UINT32 DpaCapability;\r | |
663 | UINT32 DpaLatencyIndicator;\r | |
664 | UINT16 DpaStatus;\r | |
665 | UINT16 DpaControl;\r | |
666 | UINT8 DpaPowerAllocationArray[1];\r | |
667 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION;\r | |
668 | \r | |
669 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(POWER) (UINT16)(((POWER->DpaCapability)&0x0000000F))\r | |
670 | \r | |
671 | \r | |
672 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID 0x0018\r | |
673 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_VER1 0x1\r | |
674 | \r | |
675 | typedef struct {\r | |
676 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
677 | UINT16 MaxSnoopLatency;\r | |
678 | UINT16 MaxNoSnoopLatency;\r | |
679 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING;\r | |
680 | \r | |
681 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID 0x0017\r | |
682 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_VER1 0x1\r | |
683 | \r | |
684 | typedef struct {\r | |
685 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
686 | UINT32 TphRequesterCapability;\r | |
687 | UINT32 TphRequesterControl;\r | |
688 | UINT16 TphStTable[1];\r | |
689 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH;\r | |
690 | \r | |
e1c9edd6 JC |
691 | #define GET_TPH_TABLE_SIZE(x) ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)\r |
692 | \r | |
cbedba86 RN |
693 | #pragma pack()\r |
694 | \r | |
533403e6 | 695 | #endif\r |