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533403e6 | 1 | /** @file\r |
2 | Support for the latest PCI standard.\r | |
3 | \r | |
9df063a0 HT |
4 | Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r |
5 | This program and the accompanying materials \r | |
533403e6 | 6 | are licensed and made available under the terms and conditions of the BSD License \r |
7 | which accompanies this distribution. The full text of the license may be found at \r | |
8 | http://opensource.org/licenses/bsd-license.php \r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #ifndef _PCIEXPRESS21_H_\r | |
16 | #define _PCIEXPRESS21_H_\r | |
17 | \r | |
18 | #define EFI_PCIE_CAPABILITY_BASE_OFFSET 0x100\r | |
19 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY 0x10\r | |
20 | #define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET 0x24\r | |
21 | #define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING 0x20\r | |
22 | #define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET 0x28\r | |
23 | #define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING 0x20\r | |
24 | \r | |
25 | //\r | |
26 | // for SR-IOV\r | |
27 | //\r | |
28 | #define EFI_PCIE_CAPABILITY_ID_ARI 0x0E\r | |
29 | #define EFI_PCIE_CAPABILITY_ID_ATS 0x0F\r | |
30 | #define EFI_PCIE_CAPABILITY_ID_SRIOV 0x10\r | |
31 | #define EFI_PCIE_CAPABILITY_ID_MRIOV 0x11\r | |
32 | \r | |
33 | typedef struct {\r | |
34 | UINT32 CapabilityHeader;\r | |
35 | UINT32 Capability;\r | |
36 | UINT16 Control;\r | |
37 | UINT16 Status;\r | |
38 | UINT16 InitialVFs;\r | |
39 | UINT16 TotalVFs;\r | |
40 | UINT16 NumVFs;\r | |
41 | UINT8 FunctionDependencyLink;\r | |
42 | UINT8 Reserved0;\r | |
43 | UINT16 FirstVFOffset;\r | |
44 | UINT16 VFStride;\r | |
45 | UINT16 Reserved1;\r | |
46 | UINT16 VFDeviceID;\r | |
47 | UINT32 SupportedPageSize;\r | |
48 | UINT32 SystemPageSize;\r | |
49 | UINT32 VFBar[6];\r | |
50 | UINT32 VFMigrationStateArrayOffset;\r | |
51 | } SR_IOV_CAPABILITY_REGISTER;\r | |
52 | \r | |
53 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_CAPABILITIES 0x04\r | |
54 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL 0x08\r | |
55 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_STATUS 0x0A\r | |
56 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS 0x0C\r | |
57 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_TOTALVFS 0x0E\r | |
58 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_NUMVFS 0x10\r | |
59 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_FUNCTION_DEPENDENCY_LINK 0x12\r | |
60 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF 0x14\r | |
61 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE 0x16\r | |
62 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_VFDEVICEID 0x1A\r | |
63 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE 0x1C\r | |
64 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE 0x20\r | |
65 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0 0x24\r | |
66 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR1 0x28\r | |
67 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR2 0x2C\r | |
68 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR3 0x30\r | |
69 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR4 0x34\r | |
70 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5 0x38\r | |
71 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_VF_MIGRATION_STATE 0x3C\r | |
72 | \r | |
73 | #endif\r |