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fb3df220 | 1 | /** @file\r |
50a64e5b | 2 | Provides services to maintain instruction and data caches.\r |
9095d37b | 3 | \r |
d80b2f71 | 4 | The Cache Maintenance Library provides abstractions for basic processor cache operations.\r |
5 | It removes the need to use assembly in C code.\r | |
9095d37b LG |
6 | \r |
7 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r | |
9df063a0 | 8 | This program and the accompanying materials\r |
50a64e5b | 9 | are licensed and made available under the terms and conditions of the BSD License\r |
10 | which accompanies this distribution. The full text of the license may be found at\r | |
11 | http://opensource.org/licenses/bsd-license.php\r | |
fb3df220 | 12 | \r |
50a64e5b | 13 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
14 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
fb3df220 | 15 | \r |
fb3df220 | 16 | **/\r |
17 | \r | |
18 | #ifndef __CACHE_MAINTENANCE_LIB__\r | |
19 | #define __CACHE_MAINTENANCE_LIB__\r | |
20 | \r | |
21 | /**\r | |
22 | Invalidates the entire instruction cache in cache coherency domain of the\r | |
23 | calling CPU.\r | |
24 | \r | |
fb3df220 | 25 | **/\r |
26 | VOID\r | |
27 | EFIAPI\r | |
28 | InvalidateInstructionCache (\r | |
29 | VOID\r | |
30 | );\r | |
31 | \r | |
32 | /**\r | |
33 | Invalidates a range of instruction cache lines in the cache coherency domain\r | |
34 | of the calling CPU.\r | |
35 | \r | |
36 | Invalidates the instruction cache lines specified by Address and Length. If\r | |
37 | Address is not aligned on a cache line boundary, then entire instruction\r | |
38 | cache line containing Address is invalidated. If Address + Length is not\r | |
39 | aligned on a cache line boundary, then the entire instruction cache line\r | |
40 | containing Address + Length -1 is invalidated. This function may choose to\r | |
41 | invalidate the entire instruction cache if that is more efficient than\r | |
1a2f870c | 42 | invalidating the specified range. If Length is 0, then no instruction cache\r |
fb3df220 | 43 | lines are invalidated. Address is returned.\r |
44 | \r | |
45 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
46 | \r | |
47 | @param Address The base address of the instruction cache lines to\r | |
48 | invalidate. If the CPU is in a physical addressing mode, then\r | |
49 | Address is a physical address. If the CPU is in a virtual\r | |
50 | addressing mode, then Address is a virtual address.\r | |
51 | \r | |
52 | @param Length The number of bytes to invalidate from the instruction cache.\r | |
53 | \r | |
eb1c78db | 54 | @return Address.\r |
fb3df220 | 55 | \r |
56 | **/\r | |
57 | VOID *\r | |
58 | EFIAPI\r | |
59 | InvalidateInstructionCacheRange (\r | |
60 | IN VOID *Address,\r | |
61 | IN UINTN Length\r | |
62 | );\r | |
63 | \r | |
64 | /**\r | |
65 | Writes Back and Invalidates the entire data cache in cache coherency domain\r | |
66 | of the calling CPU.\r | |
67 | \r | |
68 | Writes Back and Invalidates the entire data cache in cache coherency domain\r | |
69 | of the calling CPU. This function guarantees that all dirty cache lines are\r | |
70 | written back to system memory, and also invalidates all the data cache lines\r | |
71 | in the cache coherency domain of the calling CPU.\r | |
72 | \r | |
73 | **/\r | |
74 | VOID\r | |
75 | EFIAPI\r | |
76 | WriteBackInvalidateDataCache (\r | |
77 | VOID\r | |
78 | );\r | |
79 | \r | |
80 | /**\r | |
81 | Writes Back and Invalidates a range of data cache lines in the cache\r | |
82 | coherency domain of the calling CPU.\r | |
83 | \r | |
84 | Writes Back and Invalidate the data cache lines specified by Address and\r | |
85 | Length. If Address is not aligned on a cache line boundary, then entire data\r | |
86 | cache line containing Address is written back and invalidated. If Address +\r | |
87 | Length is not aligned on a cache line boundary, then the entire data cache\r | |
88 | line containing Address + Length -1 is written back and invalidated. This\r | |
89 | function may choose to write back and invalidate the entire data cache if\r | |
90 | that is more efficient than writing back and invalidating the specified\r | |
1a2f870c | 91 | range. If Length is 0, then no data cache lines are written back and\r |
fb3df220 | 92 | invalidated. Address is returned.\r |
93 | \r | |
94 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
95 | \r | |
96 | @param Address The base address of the data cache lines to write back and\r | |
97 | invalidate. If the CPU is in a physical addressing mode, then\r | |
98 | Address is a physical address. If the CPU is in a virtual\r | |
99 | addressing mode, then Address is a virtual address.\r | |
100 | @param Length The number of bytes to write back and invalidate from the\r | |
101 | data cache.\r | |
102 | \r | |
eb1c78db | 103 | @return Address of cache invalidation.\r |
fb3df220 | 104 | \r |
105 | **/\r | |
106 | VOID *\r | |
107 | EFIAPI\r | |
108 | WriteBackInvalidateDataCacheRange (\r | |
109 | IN VOID *Address,\r | |
110 | IN UINTN Length\r | |
111 | );\r | |
112 | \r | |
113 | /**\r | |
114 | Writes Back the entire data cache in cache coherency domain of the calling\r | |
115 | CPU.\r | |
116 | \r | |
117 | Writes Back the entire data cache in cache coherency domain of the calling\r | |
118 | CPU. This function guarantees that all dirty cache lines are written back to\r | |
119 | system memory. This function may also invalidate all the data cache lines in\r | |
120 | the cache coherency domain of the calling CPU.\r | |
121 | \r | |
122 | **/\r | |
123 | VOID\r | |
124 | EFIAPI\r | |
125 | WriteBackDataCache (\r | |
126 | VOID\r | |
127 | );\r | |
128 | \r | |
129 | /**\r | |
130 | Writes Back a range of data cache lines in the cache coherency domain of the\r | |
131 | calling CPU.\r | |
132 | \r | |
133 | Writes Back the data cache lines specified by Address and Length. If Address\r | |
134 | is not aligned on a cache line boundary, then entire data cache line\r | |
135 | containing Address is written back. If Address + Length is not aligned on a\r | |
136 | cache line boundary, then the entire data cache line containing Address +\r | |
137 | Length -1 is written back. This function may choose to write back the entire\r | |
138 | data cache if that is more efficient than writing back the specified range.\r | |
1a2f870c | 139 | If Length is 0, then no data cache lines are written back. This function may\r |
fb3df220 | 140 | also invalidate all the data cache lines in the specified range of the cache\r |
141 | coherency domain of the calling CPU. Address is returned.\r | |
142 | \r | |
143 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
144 | \r | |
145 | @param Address The base address of the data cache lines to write back. If\r | |
146 | the CPU is in a physical addressing mode, then Address is a\r | |
147 | physical address. If the CPU is in a virtual addressing\r | |
148 | mode, then Address is a virtual address.\r | |
149 | @param Length The number of bytes to write back from the data cache.\r | |
150 | \r | |
eb1c78db | 151 | @return Address of cache written in main memory.\r |
fb3df220 | 152 | \r |
153 | **/\r | |
154 | VOID *\r | |
155 | EFIAPI\r | |
156 | WriteBackDataCacheRange (\r | |
157 | IN VOID *Address,\r | |
158 | IN UINTN Length\r | |
159 | );\r | |
160 | \r | |
161 | /**\r | |
162 | Invalidates the entire data cache in cache coherency domain of the calling\r | |
163 | CPU.\r | |
164 | \r | |
165 | Invalidates the entire data cache in cache coherency domain of the calling\r | |
166 | CPU. This function must be used with care because dirty cache lines are not\r | |
167 | written back to system memory. It is typically used for cache diagnostics. If\r | |
168 | the CPU does not support invalidation of the entire data cache, then a write\r | |
169 | back and invalidate operation should be performed on the entire data cache.\r | |
170 | \r | |
171 | **/\r | |
172 | VOID\r | |
173 | EFIAPI\r | |
174 | InvalidateDataCache (\r | |
175 | VOID\r | |
176 | );\r | |
177 | \r | |
178 | /**\r | |
179 | Invalidates a range of data cache lines in the cache coherency domain of the\r | |
180 | calling CPU.\r | |
181 | \r | |
182 | Invalidates the data cache lines specified by Address and Length. If Address\r | |
183 | is not aligned on a cache line boundary, then entire data cache line\r | |
184 | containing Address is invalidated. If Address + Length is not aligned on a\r | |
185 | cache line boundary, then the entire data cache line containing Address +\r | |
186 | Length -1 is invalidated. This function must never invalidate any cache lines\r | |
187 | outside the specified range. If Length is 0, the no data cache lines are\r | |
188 | invalidated. Address is returned. This function must be used with care\r | |
189 | because dirty cache lines are not written back to system memory. It is\r | |
190 | typically used for cache diagnostics. If the CPU does not support\r | |
191 | invalidation of a data cache range, then a write back and invalidate\r | |
192 | operation should be performed on the data cache range.\r | |
193 | \r | |
194 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
195 | \r | |
196 | @param Address The base address of the data cache lines to invalidate. If\r | |
197 | the CPU is in a physical addressing mode, then Address is a\r | |
198 | physical address. If the CPU is in a virtual addressing mode,\r | |
199 | then Address is a virtual address.\r | |
200 | @param Length The number of bytes to invalidate from the data cache.\r | |
201 | \r | |
eb1c78db | 202 | @return Address.\r |
fb3df220 | 203 | \r |
204 | **/\r | |
205 | VOID *\r | |
206 | EFIAPI\r | |
207 | InvalidateDataCacheRange (\r | |
208 | IN VOID *Address,\r | |
209 | IN UINTN Length\r | |
210 | );\r | |
211 | \r | |
212 | #endif\r |