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fb3df220 | 1 | /** @file\r |
50a64e5b | 2 | Provides services to access PCI Configuration Space.\r |
badcbfb2 | 3 | \r |
4 | These functions perform PCI configuration cycles using the default PCI configuration \r | |
5 | access method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, \r | |
6 | or it may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some \r | |
7 | alternate access method. Modules will typically use the PCI Library for its PCI configuration \r | |
8 | accesses. However, if a module requires a mix of PCI access methods, the PCI CF8 Library or \r | |
9 | PCI Express Library may be used in conjunction with the PCI Library. The functionality of \r | |
10 | these three libraries is identical. The PCI CF8 Library and PCI Express Library simply use \r | |
11 | explicit access methods.\r | |
fb3df220 | 12 | \r |
9638ba6d | 13 | Copyright (c) 2006 - 2008, Intel Corporation<BR>\r |
50a64e5b | 14 | All rights reserved. This program and the accompanying materials\r |
15 | are licensed and made available under the terms and conditions of the BSD License\r | |
16 | which accompanies this distribution. The full text of the license may be found at\r | |
17 | http://opensource.org/licenses/bsd-license.php\r | |
fb3df220 | 18 | \r |
50a64e5b | 19 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
20 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
fb3df220 | 21 | \r |
fb3df220 | 22 | **/\r |
23 | \r | |
24 | #ifndef __PCI_LIB_H__\r | |
25 | #define __PCI_LIB_H__\r | |
26 | \r | |
27 | /**\r | |
28 | Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an\r | |
29 | address that can be passed to the PCI Library functions.\r | |
30 | \r | |
31 | @param Bus PCI Bus number. Range 0..255.\r | |
32 | @param Device PCI Device number. Range 0..31.\r | |
33 | @param Function PCI Function number. Range 0..7.\r | |
34 | @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095\r | |
35 | for PCI Express.\r | |
36 | \r | |
37 | @return The encoded PCI address.\r | |
38 | \r | |
39 | **/\r | |
40 | #define PCI_LIB_ADDRESS(Bus,Device,Function,Offset) \\r | |
41 | (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r | |
42 | \r | |
f926e538 | 43 | /**\r |
d11195a3 | 44 | Registers a PCI device so PCI configuration registers may be accessed after \r |
f926e538 | 45 | SetVirtualAddressMap().\r |
46 | \r | |
d11195a3 | 47 | Registers the PCI device specified by Address so all the PCI configuration registers \r |
48 | associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r | |
49 | \r | |
f926e538 | 50 | If Address > 0x0FFFFFFF, then ASSERT().\r |
51 | \r | |
52 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
53 | Register.\r | |
54 | \r | |
55 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r | |
56 | @retval RETURN_UNSUPPORTED An attempt was made to call this function \r | |
57 | after ExitBootServices().\r | |
58 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
59 | at runtime could not be mapped.\r | |
60 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
61 | complete the registration.\r | |
62 | \r | |
63 | **/\r | |
64 | RETURN_STATUS\r | |
65 | EFIAPI\r | |
66 | PciRegisterForRuntimeAccess (\r | |
67 | IN UINTN Address\r | |
68 | );\r | |
69 | \r | |
fb3df220 | 70 | /**\r |
71 | Reads an 8-bit PCI configuration register.\r | |
72 | \r | |
73 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
74 | This function must guarantee that all PCI read and write operations are\r | |
75 | serialized.\r | |
76 | \r | |
77 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
78 | \r | |
79 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
80 | Register.\r | |
81 | \r | |
82 | @return The read value from the PCI configuration register.\r | |
83 | \r | |
84 | **/\r | |
85 | UINT8\r | |
86 | EFIAPI\r | |
87 | PciRead8 (\r | |
88 | IN UINTN Address\r | |
89 | );\r | |
90 | \r | |
91 | /**\r | |
92 | Writes an 8-bit PCI configuration register.\r | |
93 | \r | |
94 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
95 | value specified by Value. Value is returned. This function must guarantee\r | |
96 | that all PCI read and write operations are serialized.\r | |
97 | \r | |
98 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
99 | \r | |
100 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
101 | Register.\r | |
102 | @param Value The value to write.\r | |
103 | \r | |
104 | @return The value written to the PCI configuration register.\r | |
105 | \r | |
106 | **/\r | |
107 | UINT8\r | |
108 | EFIAPI\r | |
109 | PciWrite8 (\r | |
110 | IN UINTN Address,\r | |
94646ec0 | 111 | IN UINT8 Value\r |
fb3df220 | 112 | );\r |
113 | \r | |
114 | /**\r | |
62991af2 | 115 | Performs a bitwise OR of an 8-bit PCI configuration register with\r |
fb3df220 | 116 | an 8-bit value.\r |
117 | \r | |
118 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 119 | bitwise OR between the read result and the value specified by\r |
fb3df220 | 120 | OrData, and writes the result to the 8-bit PCI configuration register\r |
121 | specified by Address. The value written to the PCI configuration register is\r | |
122 | returned. This function must guarantee that all PCI read and write operations\r | |
123 | are serialized.\r | |
124 | \r | |
125 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
126 | \r | |
127 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
128 | Register.\r | |
129 | @param OrData The value to OR with the PCI configuration register.\r | |
130 | \r | |
131 | @return The value written back to the PCI configuration register.\r | |
132 | \r | |
133 | **/\r | |
134 | UINT8\r | |
135 | EFIAPI\r | |
136 | PciOr8 (\r | |
137 | IN UINTN Address,\r | |
138 | IN UINT8 OrData\r | |
139 | );\r | |
140 | \r | |
141 | /**\r | |
142 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
143 | value.\r | |
144 | \r | |
145 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
146 | bitwise AND between the read result and the value specified by AndData, and\r | |
147 | writes the result to the 8-bit PCI configuration register specified by\r | |
148 | Address. The value written to the PCI configuration register is returned.\r | |
149 | This function must guarantee that all PCI read and write operations are\r | |
150 | serialized.\r | |
151 | \r | |
152 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
153 | \r | |
154 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
155 | Register.\r | |
156 | @param AndData The value to AND with the PCI configuration register.\r | |
157 | \r | |
158 | @return The value written back to the PCI configuration register.\r | |
159 | \r | |
160 | **/\r | |
161 | UINT8\r | |
162 | EFIAPI\r | |
163 | PciAnd8 (\r | |
164 | IN UINTN Address,\r | |
165 | IN UINT8 AndData\r | |
166 | );\r | |
167 | \r | |
168 | /**\r | |
169 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
62991af2 | 170 | value, followed a bitwise OR with another 8-bit value.\r |
fb3df220 | 171 | \r |
172 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
173 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 174 | performs a bitwise OR between the result of the AND operation and\r |
fb3df220 | 175 | the value specified by OrData, and writes the result to the 8-bit PCI\r |
176 | configuration register specified by Address. The value written to the PCI\r | |
177 | configuration register is returned. This function must guarantee that all PCI\r | |
178 | read and write operations are serialized.\r | |
179 | \r | |
180 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
181 | \r | |
182 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
183 | Register.\r | |
184 | @param AndData The value to AND with the PCI configuration register.\r | |
185 | @param OrData The value to OR with the result of the AND operation.\r | |
186 | \r | |
187 | @return The value written back to the PCI configuration register.\r | |
188 | \r | |
189 | **/\r | |
190 | UINT8\r | |
191 | EFIAPI\r | |
192 | PciAndThenOr8 (\r | |
193 | IN UINTN Address,\r | |
194 | IN UINT8 AndData,\r | |
195 | IN UINT8 OrData\r | |
196 | );\r | |
197 | \r | |
198 | /**\r | |
199 | Reads a bit field of a PCI configuration register.\r | |
200 | \r | |
201 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
202 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
203 | returned.\r | |
204 | \r | |
205 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
206 | If StartBit is greater than 7, then ASSERT().\r | |
207 | If EndBit is greater than 7, then ASSERT().\r | |
208 | If EndBit is less than StartBit, then ASSERT().\r | |
209 | \r | |
210 | @param Address PCI configuration register to read.\r | |
211 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
212 | Range 0..7.\r | |
213 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
214 | Range 0..7.\r | |
215 | \r | |
216 | @return The value of the bit field read from the PCI configuration register.\r | |
217 | \r | |
218 | **/\r | |
219 | UINT8\r | |
220 | EFIAPI\r | |
221 | PciBitFieldRead8 (\r | |
222 | IN UINTN Address,\r | |
223 | IN UINTN StartBit,\r | |
224 | IN UINTN EndBit\r | |
225 | );\r | |
226 | \r | |
227 | /**\r | |
228 | Writes a bit field to a PCI configuration register.\r | |
229 | \r | |
230 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
231 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
232 | destination PCI configuration register are preserved. The new value of the\r | |
233 | 8-bit register is returned.\r | |
234 | \r | |
235 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
236 | If StartBit is greater than 7, then ASSERT().\r | |
237 | If EndBit is greater than 7, then ASSERT().\r | |
238 | If EndBit is less than StartBit, then ASSERT().\r | |
239 | \r | |
240 | @param Address PCI configuration register to write.\r | |
241 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
242 | Range 0..7.\r | |
243 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
244 | Range 0..7.\r | |
245 | @param Value New value of the bit field.\r | |
246 | \r | |
247 | @return The value written back to the PCI configuration register.\r | |
248 | \r | |
249 | **/\r | |
250 | UINT8\r | |
251 | EFIAPI\r | |
252 | PciBitFieldWrite8 (\r | |
253 | IN UINTN Address,\r | |
254 | IN UINTN StartBit,\r | |
255 | IN UINTN EndBit,\r | |
256 | IN UINT8 Value\r | |
257 | );\r | |
258 | \r | |
259 | /**\r | |
260 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
261 | writes the result back to the bit field in the 8-bit port.\r | |
262 | \r | |
263 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 264 | bitwise OR between the read result and the value specified by\r |
fb3df220 | 265 | OrData, and writes the result to the 8-bit PCI configuration register\r |
266 | specified by Address. The value written to the PCI configuration register is\r | |
267 | returned. This function must guarantee that all PCI read and write operations\r | |
268 | are serialized. Extra left bits in OrData are stripped.\r | |
269 | \r | |
270 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
271 | If StartBit is greater than 7, then ASSERT().\r | |
272 | If EndBit is greater than 7, then ASSERT().\r | |
273 | If EndBit is less than StartBit, then ASSERT().\r | |
274 | \r | |
275 | @param Address PCI configuration register to write.\r | |
276 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
277 | Range 0..7.\r | |
278 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
279 | Range 0..7.\r | |
280 | @param OrData The value to OR with the PCI configuration register.\r | |
281 | \r | |
282 | @return The value written back to the PCI configuration register.\r | |
283 | \r | |
284 | **/\r | |
285 | UINT8\r | |
286 | EFIAPI\r | |
287 | PciBitFieldOr8 (\r | |
288 | IN UINTN Address,\r | |
289 | IN UINTN StartBit,\r | |
290 | IN UINTN EndBit,\r | |
291 | IN UINT8 OrData\r | |
292 | );\r | |
293 | \r | |
294 | /**\r | |
295 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
296 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
297 | \r | |
298 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
299 | bitwise AND between the read result and the value specified by AndData, and\r | |
300 | writes the result to the 8-bit PCI configuration register specified by\r | |
301 | Address. The value written to the PCI configuration register is returned.\r | |
302 | This function must guarantee that all PCI read and write operations are\r | |
303 | serialized. Extra left bits in AndData are stripped.\r | |
304 | \r | |
305 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
306 | If StartBit is greater than 7, then ASSERT().\r | |
307 | If EndBit is greater than 7, then ASSERT().\r | |
308 | If EndBit is less than StartBit, then ASSERT().\r | |
309 | \r | |
310 | @param Address PCI configuration register to write.\r | |
311 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
312 | Range 0..7.\r | |
313 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
314 | Range 0..7.\r | |
315 | @param AndData The value to AND with the PCI configuration register.\r | |
316 | \r | |
317 | @return The value written back to the PCI configuration register.\r | |
318 | \r | |
319 | **/\r | |
320 | UINT8\r | |
321 | EFIAPI\r | |
322 | PciBitFieldAnd8 (\r | |
323 | IN UINTN Address,\r | |
324 | IN UINTN StartBit,\r | |
325 | IN UINTN EndBit,\r | |
326 | IN UINT8 AndData\r | |
327 | );\r | |
328 | \r | |
329 | /**\r | |
330 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 331 | bitwise OR, and writes the result back to the bit field in the\r |
fb3df220 | 332 | 8-bit port.\r |
333 | \r | |
334 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 335 | bitwise AND followed by a bitwise OR between the read result and\r |
fb3df220 | 336 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
337 | configuration register specified by Address. The value written to the PCI\r | |
338 | configuration register is returned. This function must guarantee that all PCI\r | |
339 | read and write operations are serialized. Extra left bits in both AndData and\r | |
340 | OrData are stripped.\r | |
341 | \r | |
342 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
343 | If StartBit is greater than 7, then ASSERT().\r | |
344 | If EndBit is greater than 7, then ASSERT().\r | |
345 | If EndBit is less than StartBit, then ASSERT().\r | |
346 | \r | |
347 | @param Address PCI configuration register to write.\r | |
348 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
349 | Range 0..7.\r | |
350 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
351 | Range 0..7.\r | |
352 | @param AndData The value to AND with the PCI configuration register.\r | |
353 | @param OrData The value to OR with the result of the AND operation.\r | |
354 | \r | |
355 | @return The value written back to the PCI configuration register.\r | |
356 | \r | |
357 | **/\r | |
358 | UINT8\r | |
359 | EFIAPI\r | |
360 | PciBitFieldAndThenOr8 (\r | |
361 | IN UINTN Address,\r | |
362 | IN UINTN StartBit,\r | |
363 | IN UINTN EndBit,\r | |
364 | IN UINT8 AndData,\r | |
365 | IN UINT8 OrData\r | |
366 | );\r | |
367 | \r | |
368 | /**\r | |
369 | Reads a 16-bit PCI configuration register.\r | |
370 | \r | |
371 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
372 | This function must guarantee that all PCI read and write operations are\r | |
373 | serialized.\r | |
374 | \r | |
375 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
376 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
377 | \r | |
378 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
379 | Register.\r | |
380 | \r | |
381 | @return The read value from the PCI configuration register.\r | |
382 | \r | |
383 | **/\r | |
384 | UINT16\r | |
385 | EFIAPI\r | |
386 | PciRead16 (\r | |
387 | IN UINTN Address\r | |
388 | );\r | |
389 | \r | |
390 | /**\r | |
391 | Writes a 16-bit PCI configuration register.\r | |
392 | \r | |
393 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
394 | value specified by Value. Value is returned. This function must guarantee\r | |
395 | that all PCI read and write operations are serialized.\r | |
396 | \r | |
397 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
398 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
399 | \r | |
400 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
401 | Register.\r | |
402 | @param Value The value to write.\r | |
403 | \r | |
404 | @return The value written to the PCI configuration register.\r | |
405 | \r | |
406 | **/\r | |
407 | UINT16\r | |
408 | EFIAPI\r | |
409 | PciWrite16 (\r | |
410 | IN UINTN Address,\r | |
94646ec0 | 411 | IN UINT16 Value\r |
fb3df220 | 412 | );\r |
413 | \r | |
414 | /**\r | |
62991af2 | 415 | Performs a bitwise OR of a 16-bit PCI configuration register with\r |
fb3df220 | 416 | a 16-bit value.\r |
417 | \r | |
418 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 419 | bitwise OR between the read result and the value specified by\r |
fb3df220 | 420 | OrData, and writes the result to the 16-bit PCI configuration register\r |
421 | specified by Address. The value written to the PCI configuration register is\r | |
422 | returned. This function must guarantee that all PCI read and write operations\r | |
423 | are serialized.\r | |
424 | \r | |
425 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
426 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
427 | \r | |
428 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
429 | Register.\r | |
430 | @param OrData The value to OR with the PCI configuration register.\r | |
431 | \r | |
432 | @return The value written back to the PCI configuration register.\r | |
433 | \r | |
434 | **/\r | |
435 | UINT16\r | |
436 | EFIAPI\r | |
437 | PciOr16 (\r | |
438 | IN UINTN Address,\r | |
439 | IN UINT16 OrData\r | |
440 | );\r | |
441 | \r | |
442 | /**\r | |
443 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
444 | value.\r | |
445 | \r | |
446 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
447 | bitwise AND between the read result and the value specified by AndData, and\r | |
448 | writes the result to the 16-bit PCI configuration register specified by\r | |
449 | Address. The value written to the PCI configuration register is returned.\r | |
450 | This function must guarantee that all PCI read and write operations are\r | |
451 | serialized.\r | |
452 | \r | |
453 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
454 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
455 | \r | |
456 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
457 | Register.\r | |
458 | @param AndData The value to AND with the PCI configuration register.\r | |
459 | \r | |
460 | @return The value written back to the PCI configuration register.\r | |
461 | \r | |
462 | **/\r | |
463 | UINT16\r | |
464 | EFIAPI\r | |
465 | PciAnd16 (\r | |
466 | IN UINTN Address,\r | |
467 | IN UINT16 AndData\r | |
468 | );\r | |
469 | \r | |
470 | /**\r | |
471 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
62991af2 | 472 | value, followed a bitwise OR with another 16-bit value.\r |
fb3df220 | 473 | \r |
474 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
475 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 476 | performs a bitwise OR between the result of the AND operation and\r |
fb3df220 | 477 | the value specified by OrData, and writes the result to the 16-bit PCI\r |
478 | configuration register specified by Address. The value written to the PCI\r | |
479 | configuration register is returned. This function must guarantee that all PCI\r | |
480 | read and write operations are serialized.\r | |
481 | \r | |
482 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
483 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
484 | \r | |
485 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
486 | Register.\r | |
487 | @param AndData The value to AND with the PCI configuration register.\r | |
488 | @param OrData The value to OR with the result of the AND operation.\r | |
489 | \r | |
490 | @return The value written back to the PCI configuration register.\r | |
491 | \r | |
492 | **/\r | |
493 | UINT16\r | |
494 | EFIAPI\r | |
495 | PciAndThenOr16 (\r | |
496 | IN UINTN Address,\r | |
497 | IN UINT16 AndData,\r | |
498 | IN UINT16 OrData\r | |
499 | );\r | |
500 | \r | |
501 | /**\r | |
502 | Reads a bit field of a PCI configuration register.\r | |
503 | \r | |
504 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
505 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
506 | returned.\r | |
507 | \r | |
508 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
509 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
510 | If StartBit is greater than 15, then ASSERT().\r | |
511 | If EndBit is greater than 15, then ASSERT().\r | |
512 | If EndBit is less than StartBit, then ASSERT().\r | |
513 | \r | |
514 | @param Address PCI configuration register to read.\r | |
515 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
516 | Range 0..15.\r | |
517 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
518 | Range 0..15.\r | |
519 | \r | |
520 | @return The value of the bit field read from the PCI configuration register.\r | |
521 | \r | |
522 | **/\r | |
523 | UINT16\r | |
524 | EFIAPI\r | |
525 | PciBitFieldRead16 (\r | |
526 | IN UINTN Address,\r | |
527 | IN UINTN StartBit,\r | |
528 | IN UINTN EndBit\r | |
529 | );\r | |
530 | \r | |
531 | /**\r | |
532 | Writes a bit field to a PCI configuration register.\r | |
533 | \r | |
534 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
535 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
536 | destination PCI configuration register are preserved. The new value of the\r | |
537 | 16-bit register is returned.\r | |
538 | \r | |
539 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
540 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
541 | If StartBit is greater than 15, then ASSERT().\r | |
542 | If EndBit is greater than 15, then ASSERT().\r | |
543 | If EndBit is less than StartBit, then ASSERT().\r | |
544 | \r | |
545 | @param Address PCI configuration register to write.\r | |
546 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
547 | Range 0..15.\r | |
548 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
549 | Range 0..15.\r | |
550 | @param Value New value of the bit field.\r | |
551 | \r | |
552 | @return The value written back to the PCI configuration register.\r | |
553 | \r | |
554 | **/\r | |
555 | UINT16\r | |
556 | EFIAPI\r | |
557 | PciBitFieldWrite16 (\r | |
558 | IN UINTN Address,\r | |
559 | IN UINTN StartBit,\r | |
560 | IN UINTN EndBit,\r | |
561 | IN UINT16 Value\r | |
562 | );\r | |
563 | \r | |
564 | /**\r | |
565 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
566 | writes the result back to the bit field in the 16-bit port.\r | |
567 | \r | |
568 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 569 | bitwise OR between the read result and the value specified by\r |
fb3df220 | 570 | OrData, and writes the result to the 16-bit PCI configuration register\r |
571 | specified by Address. The value written to the PCI configuration register is\r | |
572 | returned. This function must guarantee that all PCI read and write operations\r | |
573 | are serialized. Extra left bits in OrData are stripped.\r | |
574 | \r | |
575 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
576 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
577 | If StartBit is greater than 15, then ASSERT().\r | |
578 | If EndBit is greater than 15, then ASSERT().\r | |
579 | If EndBit is less than StartBit, then ASSERT().\r | |
580 | \r | |
581 | @param Address PCI configuration register to write.\r | |
582 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
583 | Range 0..15.\r | |
584 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
585 | Range 0..15.\r | |
586 | @param OrData The value to OR with the PCI configuration register.\r | |
587 | \r | |
588 | @return The value written back to the PCI configuration register.\r | |
589 | \r | |
590 | **/\r | |
591 | UINT16\r | |
592 | EFIAPI\r | |
593 | PciBitFieldOr16 (\r | |
594 | IN UINTN Address,\r | |
595 | IN UINTN StartBit,\r | |
596 | IN UINTN EndBit,\r | |
597 | IN UINT16 OrData\r | |
598 | );\r | |
599 | \r | |
600 | /**\r | |
601 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
602 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
603 | \r | |
604 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
605 | bitwise AND between the read result and the value specified by AndData, and\r | |
606 | writes the result to the 16-bit PCI configuration register specified by\r | |
607 | Address. The value written to the PCI configuration register is returned.\r | |
608 | This function must guarantee that all PCI read and write operations are\r | |
609 | serialized. Extra left bits in AndData are stripped.\r | |
610 | \r | |
611 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
612 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
613 | If StartBit is greater than 15, then ASSERT().\r | |
614 | If EndBit is greater than 15, then ASSERT().\r | |
615 | If EndBit is less than StartBit, then ASSERT().\r | |
616 | \r | |
617 | @param Address PCI configuration register to write.\r | |
618 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
619 | Range 0..15.\r | |
620 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
621 | Range 0..15.\r | |
622 | @param AndData The value to AND with the PCI configuration register.\r | |
623 | \r | |
624 | @return The value written back to the PCI configuration register.\r | |
625 | \r | |
626 | **/\r | |
627 | UINT16\r | |
628 | EFIAPI\r | |
629 | PciBitFieldAnd16 (\r | |
630 | IN UINTN Address,\r | |
631 | IN UINTN StartBit,\r | |
632 | IN UINTN EndBit,\r | |
633 | IN UINT16 AndData\r | |
634 | );\r | |
635 | \r | |
636 | /**\r | |
637 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 638 | bitwise OR, and writes the result back to the bit field in the\r |
fb3df220 | 639 | 16-bit port.\r |
640 | \r | |
641 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 642 | bitwise AND followed by a bitwise OR between the read result and\r |
fb3df220 | 643 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
644 | configuration register specified by Address. The value written to the PCI\r | |
645 | configuration register is returned. This function must guarantee that all PCI\r | |
646 | read and write operations are serialized. Extra left bits in both AndData and\r | |
647 | OrData are stripped.\r | |
648 | \r | |
649 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
650 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
651 | If StartBit is greater than 15, then ASSERT().\r | |
652 | If EndBit is greater than 15, then ASSERT().\r | |
653 | If EndBit is less than StartBit, then ASSERT().\r | |
654 | \r | |
655 | @param Address PCI configuration register to write.\r | |
656 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
657 | Range 0..15.\r | |
658 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
659 | Range 0..15.\r | |
660 | @param AndData The value to AND with the PCI configuration register.\r | |
661 | @param OrData The value to OR with the result of the AND operation.\r | |
662 | \r | |
663 | @return The value written back to the PCI configuration register.\r | |
664 | \r | |
665 | **/\r | |
666 | UINT16\r | |
667 | EFIAPI\r | |
668 | PciBitFieldAndThenOr16 (\r | |
669 | IN UINTN Address,\r | |
670 | IN UINTN StartBit,\r | |
671 | IN UINTN EndBit,\r | |
672 | IN UINT16 AndData,\r | |
673 | IN UINT16 OrData\r | |
674 | );\r | |
675 | \r | |
676 | /**\r | |
677 | Reads a 32-bit PCI configuration register.\r | |
678 | \r | |
679 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
680 | This function must guarantee that all PCI read and write operations are\r | |
681 | serialized.\r | |
682 | \r | |
683 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
684 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
685 | \r | |
686 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
687 | Register.\r | |
688 | \r | |
689 | @return The read value from the PCI configuration register.\r | |
690 | \r | |
691 | **/\r | |
692 | UINT32\r | |
693 | EFIAPI\r | |
694 | PciRead32 (\r | |
695 | IN UINTN Address\r | |
696 | );\r | |
697 | \r | |
698 | /**\r | |
699 | Writes a 32-bit PCI configuration register.\r | |
700 | \r | |
701 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
702 | value specified by Value. Value is returned. This function must guarantee\r | |
703 | that all PCI read and write operations are serialized.\r | |
704 | \r | |
705 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
706 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
707 | \r | |
708 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
709 | Register.\r | |
710 | @param Value The value to write.\r | |
711 | \r | |
712 | @return The value written to the PCI configuration register.\r | |
713 | \r | |
714 | **/\r | |
715 | UINT32\r | |
716 | EFIAPI\r | |
717 | PciWrite32 (\r | |
718 | IN UINTN Address,\r | |
94646ec0 | 719 | IN UINT32 Value\r |
fb3df220 | 720 | );\r |
721 | \r | |
722 | /**\r | |
62991af2 | 723 | Performs a bitwise OR of a 32-bit PCI configuration register with\r |
fb3df220 | 724 | a 32-bit value.\r |
725 | \r | |
726 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 727 | bitwise OR between the read result and the value specified by\r |
fb3df220 | 728 | OrData, and writes the result to the 32-bit PCI configuration register\r |
729 | specified by Address. The value written to the PCI configuration register is\r | |
730 | returned. This function must guarantee that all PCI read and write operations\r | |
731 | are serialized.\r | |
732 | \r | |
733 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
734 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
735 | \r | |
736 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
737 | Register.\r | |
738 | @param OrData The value to OR with the PCI configuration register.\r | |
739 | \r | |
740 | @return The value written back to the PCI configuration register.\r | |
741 | \r | |
742 | **/\r | |
743 | UINT32\r | |
744 | EFIAPI\r | |
745 | PciOr32 (\r | |
746 | IN UINTN Address,\r | |
747 | IN UINT32 OrData\r | |
748 | );\r | |
749 | \r | |
750 | /**\r | |
751 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
752 | value.\r | |
753 | \r | |
754 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
755 | bitwise AND between the read result and the value specified by AndData, and\r | |
756 | writes the result to the 32-bit PCI configuration register specified by\r | |
757 | Address. The value written to the PCI configuration register is returned.\r | |
758 | This function must guarantee that all PCI read and write operations are\r | |
759 | serialized.\r | |
760 | \r | |
761 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
762 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
763 | \r | |
764 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
765 | Register.\r | |
766 | @param AndData The value to AND with the PCI configuration register.\r | |
767 | \r | |
768 | @return The value written back to the PCI configuration register.\r | |
769 | \r | |
770 | **/\r | |
771 | UINT32\r | |
772 | EFIAPI\r | |
773 | PciAnd32 (\r | |
774 | IN UINTN Address,\r | |
775 | IN UINT32 AndData\r | |
776 | );\r | |
777 | \r | |
778 | /**\r | |
779 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
62991af2 | 780 | value, followed a bitwise OR with another 32-bit value.\r |
fb3df220 | 781 | \r |
782 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
783 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 784 | performs a bitwise OR between the result of the AND operation and\r |
fb3df220 | 785 | the value specified by OrData, and writes the result to the 32-bit PCI\r |
786 | configuration register specified by Address. The value written to the PCI\r | |
787 | configuration register is returned. This function must guarantee that all PCI\r | |
788 | read and write operations are serialized.\r | |
789 | \r | |
790 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
791 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
792 | \r | |
793 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
794 | Register.\r | |
795 | @param AndData The value to AND with the PCI configuration register.\r | |
796 | @param OrData The value to OR with the result of the AND operation.\r | |
797 | \r | |
798 | @return The value written back to the PCI configuration register.\r | |
799 | \r | |
800 | **/\r | |
801 | UINT32\r | |
802 | EFIAPI\r | |
803 | PciAndThenOr32 (\r | |
804 | IN UINTN Address,\r | |
805 | IN UINT32 AndData,\r | |
806 | IN UINT32 OrData\r | |
807 | );\r | |
808 | \r | |
809 | /**\r | |
810 | Reads a bit field of a PCI configuration register.\r | |
811 | \r | |
812 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
813 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
814 | returned.\r | |
815 | \r | |
816 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
817 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
818 | If StartBit is greater than 31, then ASSERT().\r | |
819 | If EndBit is greater than 31, then ASSERT().\r | |
820 | If EndBit is less than StartBit, then ASSERT().\r | |
821 | \r | |
822 | @param Address PCI configuration register to read.\r | |
823 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
824 | Range 0..31.\r | |
825 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
826 | Range 0..31.\r | |
827 | \r | |
828 | @return The value of the bit field read from the PCI configuration register.\r | |
829 | \r | |
830 | **/\r | |
831 | UINT32\r | |
832 | EFIAPI\r | |
833 | PciBitFieldRead32 (\r | |
834 | IN UINTN Address,\r | |
835 | IN UINTN StartBit,\r | |
836 | IN UINTN EndBit\r | |
837 | );\r | |
838 | \r | |
839 | /**\r | |
840 | Writes a bit field to a PCI configuration register.\r | |
841 | \r | |
842 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
843 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
844 | destination PCI configuration register are preserved. The new value of the\r | |
845 | 32-bit register is returned.\r | |
846 | \r | |
847 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
848 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
849 | If StartBit is greater than 31, then ASSERT().\r | |
850 | If EndBit is greater than 31, then ASSERT().\r | |
851 | If EndBit is less than StartBit, then ASSERT().\r | |
852 | \r | |
853 | @param Address PCI configuration register to write.\r | |
854 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
855 | Range 0..31.\r | |
856 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
857 | Range 0..31.\r | |
858 | @param Value New value of the bit field.\r | |
859 | \r | |
860 | @return The value written back to the PCI configuration register.\r | |
861 | \r | |
862 | **/\r | |
863 | UINT32\r | |
864 | EFIAPI\r | |
865 | PciBitFieldWrite32 (\r | |
866 | IN UINTN Address,\r | |
867 | IN UINTN StartBit,\r | |
868 | IN UINTN EndBit,\r | |
869 | IN UINT32 Value\r | |
870 | );\r | |
871 | \r | |
872 | /**\r | |
873 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
874 | writes the result back to the bit field in the 32-bit port.\r | |
875 | \r | |
876 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 877 | bitwise OR between the read result and the value specified by\r |
fb3df220 | 878 | OrData, and writes the result to the 32-bit PCI configuration register\r |
879 | specified by Address. The value written to the PCI configuration register is\r | |
880 | returned. This function must guarantee that all PCI read and write operations\r | |
881 | are serialized. Extra left bits in OrData are stripped.\r | |
882 | \r | |
883 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
884 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
885 | If StartBit is greater than 31, then ASSERT().\r | |
886 | If EndBit is greater than 31, then ASSERT().\r | |
887 | If EndBit is less than StartBit, then ASSERT().\r | |
888 | \r | |
889 | @param Address PCI configuration register to write.\r | |
890 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
891 | Range 0..31.\r | |
892 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
893 | Range 0..31.\r | |
894 | @param OrData The value to OR with the PCI configuration register.\r | |
895 | \r | |
896 | @return The value written back to the PCI configuration register.\r | |
897 | \r | |
898 | **/\r | |
899 | UINT32\r | |
900 | EFIAPI\r | |
901 | PciBitFieldOr32 (\r | |
902 | IN UINTN Address,\r | |
903 | IN UINTN StartBit,\r | |
904 | IN UINTN EndBit,\r | |
905 | IN UINT32 OrData\r | |
906 | );\r | |
907 | \r | |
908 | /**\r | |
909 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
910 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
911 | \r | |
912 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
913 | bitwise AND between the read result and the value specified by AndData, and\r | |
914 | writes the result to the 32-bit PCI configuration register specified by\r | |
915 | Address. The value written to the PCI configuration register is returned.\r | |
916 | This function must guarantee that all PCI read and write operations are\r | |
917 | serialized. Extra left bits in AndData are stripped.\r | |
918 | \r | |
919 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
920 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
921 | If StartBit is greater than 31, then ASSERT().\r | |
922 | If EndBit is greater than 31, then ASSERT().\r | |
923 | If EndBit is less than StartBit, then ASSERT().\r | |
924 | \r | |
925 | @param Address PCI configuration register to write.\r | |
926 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
927 | Range 0..31.\r | |
928 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
929 | Range 0..31.\r | |
930 | @param AndData The value to AND with the PCI configuration register.\r | |
931 | \r | |
932 | @return The value written back to the PCI configuration register.\r | |
933 | \r | |
934 | **/\r | |
935 | UINT32\r | |
936 | EFIAPI\r | |
937 | PciBitFieldAnd32 (\r | |
938 | IN UINTN Address,\r | |
939 | IN UINTN StartBit,\r | |
940 | IN UINTN EndBit,\r | |
941 | IN UINT32 AndData\r | |
942 | );\r | |
943 | \r | |
944 | /**\r | |
945 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 946 | bitwise OR, and writes the result back to the bit field in the\r |
fb3df220 | 947 | 32-bit port.\r |
948 | \r | |
949 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 950 | bitwise AND followed by a bitwise OR between the read result and\r |
fb3df220 | 951 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
952 | configuration register specified by Address. The value written to the PCI\r | |
953 | configuration register is returned. This function must guarantee that all PCI\r | |
954 | read and write operations are serialized. Extra left bits in both AndData and\r | |
955 | OrData are stripped.\r | |
956 | \r | |
957 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
958 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
959 | If StartBit is greater than 31, then ASSERT().\r | |
960 | If EndBit is greater than 31, then ASSERT().\r | |
961 | If EndBit is less than StartBit, then ASSERT().\r | |
962 | \r | |
963 | @param Address PCI configuration register to write.\r | |
964 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
965 | Range 0..31.\r | |
966 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
967 | Range 0..31.\r | |
968 | @param AndData The value to AND with the PCI configuration register.\r | |
969 | @param OrData The value to OR with the result of the AND operation.\r | |
970 | \r | |
971 | @return The value written back to the PCI configuration register.\r | |
972 | \r | |
973 | **/\r | |
974 | UINT32\r | |
975 | EFIAPI\r | |
976 | PciBitFieldAndThenOr32 (\r | |
977 | IN UINTN Address,\r | |
978 | IN UINTN StartBit,\r | |
979 | IN UINTN EndBit,\r | |
980 | IN UINT32 AndData,\r | |
981 | IN UINT32 OrData\r | |
982 | );\r | |
983 | \r | |
984 | /**\r | |
985 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
986 | \r | |
987 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
988 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
989 | configuration registers from a single PCI function to be read. Size is\r | |
990 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
991 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
992 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
993 | end of the range.\r | |
994 | \r | |
995 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
996 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
997 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
998 | \r | |
999 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1000 | Function and Register.\r | |
1001 | @param Size Size in bytes of the transfer.\r | |
1002 | @param Buffer Pointer to a buffer receiving the data read.\r | |
1003 | \r | |
1004 | @return Size\r | |
1005 | \r | |
1006 | **/\r | |
1007 | UINTN\r | |
1008 | EFIAPI\r | |
1009 | PciReadBuffer (\r | |
1010 | IN UINTN StartAddress,\r | |
1011 | IN UINTN Size,\r | |
1012 | OUT VOID *Buffer\r | |
1013 | );\r | |
1014 | \r | |
1015 | /**\r | |
1016 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1017 | configuration space.\r | |
1018 | \r | |
1019 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1020 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1021 | configuration registers from a single PCI function to be written. Size is\r | |
1022 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1023 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1024 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1025 | and the end of the range.\r | |
1026 | \r | |
1027 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1028 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1029 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1030 | \r | |
1031 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1032 | Function and Register.\r | |
1033 | @param Size Size in bytes of the transfer.\r | |
1034 | @param Buffer Pointer to a buffer containing the data to write.\r | |
1035 | \r | |
9199040c | 1036 | @return Size written to StartAddress.\r |
fb3df220 | 1037 | \r |
1038 | **/\r | |
1039 | UINTN\r | |
1040 | EFIAPI\r | |
1041 | PciWriteBuffer (\r | |
1042 | IN UINTN StartAddress,\r | |
1043 | IN UINTN Size,\r | |
1044 | IN VOID *Buffer\r | |
1045 | );\r | |
1046 | \r | |
1047 | #endif\r |