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d1f95000 | 1 | /** @file\r |
2 | DebugSupport protocol and supporting definitions as defined in the UEFI2.0\r | |
3 | specification.\r | |
4 | \r | |
5 | The DebugSupport protocol is used by source level debuggers to abstract the\r | |
6 | processor and handle context save and restore operations.\r | |
7 | \r | |
4ca9b6c4 | 8 | Copyright (c) 2006 - 2008, Intel Corporation \r |
d1f95000 | 9 | All rights reserved. This program and the accompanying materials \r |
10 | are licensed and made available under the terms and conditions of the BSD License \r | |
11 | which accompanies this distribution. The full text of the license may be found at \r | |
12 | http://opensource.org/licenses/bsd-license.php \r | |
13 | \r | |
14 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
15 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
16 | \r | |
d1f95000 | 17 | **/\r |
18 | \r | |
19 | #ifndef __DEBUG_SUPPORT_H__\r | |
20 | #define __DEBUG_SUPPORT_H__\r | |
21 | \r | |
3f748e52 | 22 | #include <ProcessorBind.h>\r |
d1f95000 | 23 | #include <IndustryStandard/PeImage.h>\r |
24 | \r | |
25 | typedef struct _EFI_DEBUG_SUPPORT_PROTOCOL EFI_DEBUG_SUPPORT_PROTOCOL;\r | |
26 | \r | |
99e8ed21 | 27 | ///\r |
28 | /// Debug Support protocol {2755590C-6F3C-42FA-9EA4-A3BA543CDA25}\r | |
29 | ///\r | |
d1f95000 | 30 | #define EFI_DEBUG_SUPPORT_PROTOCOL_GUID \\r |
31 | { \\r | |
32 | 0x2755590C, 0x6F3C, 0x42FA, {0x9E, 0xA4, 0xA3, 0xBA, 0x54, 0x3C, 0xDA, 0x25 } \\r | |
33 | }\r | |
34 | \r | |
99e8ed21 | 35 | ///\r |
9319d2c2 LG |
36 | /// Processor exception to be hooked.\r |
37 | /// All exception types for IA32, X64, Itanium and EBC processors are defined.\r | |
99e8ed21 | 38 | ///\r |
d1f95000 | 39 | typedef INTN EFI_EXCEPTION_TYPE;\r |
40 | \r | |
9319d2c2 LG |
41 | ///\r |
42 | /// IA-32 processor exception types\r | |
43 | ///\r | |
d1f95000 | 44 | #define EXCEPT_IA32_DIVIDE_ERROR 0\r |
45 | #define EXCEPT_IA32_DEBUG 1\r | |
46 | #define EXCEPT_IA32_NMI 2\r | |
47 | #define EXCEPT_IA32_BREAKPOINT 3\r | |
48 | #define EXCEPT_IA32_OVERFLOW 4\r | |
49 | #define EXCEPT_IA32_BOUND 5\r | |
50 | #define EXCEPT_IA32_INVALID_OPCODE 6\r | |
51 | #define EXCEPT_IA32_DOUBLE_FAULT 8\r | |
52 | #define EXCEPT_IA32_INVALID_TSS 10\r | |
53 | #define EXCEPT_IA32_SEG_NOT_PRESENT 11\r | |
54 | #define EXCEPT_IA32_STACK_FAULT 12\r | |
55 | #define EXCEPT_IA32_GP_FAULT 13\r | |
56 | #define EXCEPT_IA32_PAGE_FAULT 14\r | |
57 | #define EXCEPT_IA32_FP_ERROR 16\r | |
58 | #define EXCEPT_IA32_ALIGNMENT_CHECK 17\r | |
59 | #define EXCEPT_IA32_MACHINE_CHECK 18\r | |
60 | #define EXCEPT_IA32_SIMD 19\r | |
61 | \r | |
8b6c989b | 62 | ///\r |
63 | /// FXSAVE_STATE\r | |
64 | /// FP / MMX / XMM registers (see fxrstor instruction definition)\r | |
65 | ///\r | |
d1f95000 | 66 | typedef struct {\r |
67 | UINT16 Fcw;\r | |
68 | UINT16 Fsw;\r | |
69 | UINT16 Ftw;\r | |
70 | UINT16 Opcode;\r | |
71 | UINT32 Eip;\r | |
72 | UINT16 Cs;\r | |
73 | UINT16 Reserved1;\r | |
74 | UINT32 DataOffset;\r | |
75 | UINT16 Ds;\r | |
76 | UINT8 Reserved2[10];\r | |
d1f95000 | 77 | UINT8 St0Mm0[10], Reserved3[6];\r |
78 | UINT8 St1Mm1[10], Reserved4[6];\r | |
79 | UINT8 St2Mm2[10], Reserved5[6];\r | |
80 | UINT8 St3Mm3[10], Reserved6[6];\r | |
81 | UINT8 St4Mm4[10], Reserved7[6];\r | |
82 | UINT8 St5Mm5[10], Reserved8[6];\r | |
83 | UINT8 St6Mm6[10], Reserved9[6];\r | |
84 | UINT8 St7Mm7[10], Reserved10[6];\r | |
85 | UINT8 Xmm0[16];\r | |
86 | UINT8 Xmm1[16];\r | |
87 | UINT8 Xmm2[16];\r | |
88 | UINT8 Xmm3[16];\r | |
89 | UINT8 Xmm4[16];\r | |
90 | UINT8 Xmm5[16];\r | |
91 | UINT8 Xmm6[16];\r | |
92 | UINT8 Xmm7[16];\r | |
93 | UINT8 Reserved11[14 * 16];\r | |
94 | } EFI_FX_SAVE_STATE_IA32;\r | |
d1f95000 | 95 | \r |
9319d2c2 LG |
96 | ///\r |
97 | /// IA-32 processor context definition\r | |
98 | ///\r | |
d1f95000 | 99 | typedef struct {\r |
100 | UINT32 ExceptionData;\r | |
d1f95000 | 101 | EFI_FX_SAVE_STATE_IA32 FxSaveState;\r |
d1f95000 | 102 | UINT32 Dr0;\r |
103 | UINT32 Dr1;\r | |
104 | UINT32 Dr2;\r | |
105 | UINT32 Dr3;\r | |
106 | UINT32 Dr6;\r | |
107 | UINT32 Dr7;\r | |
108 | UINT32 Cr0;\r | |
109 | UINT32 Cr1; /* Reserved */\r | |
110 | UINT32 Cr2;\r | |
111 | UINT32 Cr3;\r | |
112 | UINT32 Cr4;\r | |
113 | UINT32 Eflags;\r | |
114 | UINT32 Ldtr;\r | |
115 | UINT32 Tr;\r | |
116 | UINT32 Gdtr[2];\r | |
117 | UINT32 Idtr[2];\r | |
118 | UINT32 Eip;\r | |
119 | UINT32 Gs;\r | |
120 | UINT32 Fs;\r | |
121 | UINT32 Es;\r | |
122 | UINT32 Ds;\r | |
123 | UINT32 Cs;\r | |
124 | UINT32 Ss;\r | |
125 | UINT32 Edi;\r | |
126 | UINT32 Esi;\r | |
127 | UINT32 Ebp;\r | |
128 | UINT32 Esp;\r | |
129 | UINT32 Ebx;\r | |
130 | UINT32 Edx;\r | |
131 | UINT32 Ecx;\r | |
132 | UINT32 Eax;\r | |
133 | } EFI_SYSTEM_CONTEXT_IA32;\r | |
134 | \r | |
9319d2c2 LG |
135 | ///\r |
136 | /// x64 processor exception types\r | |
137 | ///\r | |
d1f95000 | 138 | #define EXCEPT_X64_DIVIDE_ERROR 0\r |
139 | #define EXCEPT_X64_DEBUG 1\r | |
140 | #define EXCEPT_X64_NMI 2\r | |
141 | #define EXCEPT_X64_BREAKPOINT 3\r | |
142 | #define EXCEPT_X64_OVERFLOW 4\r | |
143 | #define EXCEPT_X64_BOUND 5\r | |
144 | #define EXCEPT_X64_INVALID_OPCODE 6\r | |
145 | #define EXCEPT_X64_DOUBLE_FAULT 8\r | |
146 | #define EXCEPT_X64_INVALID_TSS 10\r | |
147 | #define EXCEPT_X64_SEG_NOT_PRESENT 11\r | |
148 | #define EXCEPT_X64_STACK_FAULT 12\r | |
149 | #define EXCEPT_X64_GP_FAULT 13\r | |
150 | #define EXCEPT_X64_PAGE_FAULT 14\r | |
151 | #define EXCEPT_X64_FP_ERROR 16\r | |
152 | #define EXCEPT_X64_ALIGNMENT_CHECK 17\r | |
153 | #define EXCEPT_X64_MACHINE_CHECK 18\r | |
154 | #define EXCEPT_X64_SIMD 19\r | |
155 | \r | |
8b6c989b | 156 | ///\r |
157 | /// FXSAVE_STATE\r | |
158 | /// FP / MMX / XMM registers (see fxrstor instruction definition)\r | |
159 | ///\r | |
d1f95000 | 160 | typedef struct {\r |
161 | UINT16 Fcw;\r | |
162 | UINT16 Fsw;\r | |
163 | UINT16 Ftw;\r | |
164 | UINT16 Opcode;\r | |
165 | UINT64 Rip;\r | |
166 | UINT64 DataOffset;\r | |
167 | UINT8 Reserved1[8];\r | |
168 | UINT8 St0Mm0[10], Reserved2[6];\r | |
169 | UINT8 St1Mm1[10], Reserved3[6];\r | |
170 | UINT8 St2Mm2[10], Reserved4[6];\r | |
171 | UINT8 St3Mm3[10], Reserved5[6];\r | |
172 | UINT8 St4Mm4[10], Reserved6[6];\r | |
173 | UINT8 St5Mm5[10], Reserved7[6];\r | |
174 | UINT8 St6Mm6[10], Reserved8[6];\r | |
175 | UINT8 St7Mm7[10], Reserved9[6];\r | |
176 | UINT8 Xmm0[16];\r | |
177 | UINT8 Xmm1[16];\r | |
178 | UINT8 Xmm2[16];\r | |
179 | UINT8 Xmm3[16];\r | |
180 | UINT8 Xmm4[16];\r | |
181 | UINT8 Xmm5[16];\r | |
182 | UINT8 Xmm6[16];\r | |
183 | UINT8 Xmm7[16];\r | |
d1f95000 | 184 | //\r |
19bee90c | 185 | // NOTE: UEFI 2.0 spec definition as follows. \r |
d1f95000 | 186 | //\r |
187 | UINT8 Reserved11[14 * 16];\r | |
d1f95000 | 188 | } EFI_FX_SAVE_STATE_X64;\r |
189 | \r | |
9319d2c2 LG |
190 | ///\r |
191 | /// x64 processor context definition\r | |
192 | ///\r | |
d1f95000 | 193 | typedef struct {\r |
194 | UINT64 ExceptionData;\r | |
195 | EFI_FX_SAVE_STATE_X64 FxSaveState;\r | |
196 | UINT64 Dr0;\r | |
197 | UINT64 Dr1;\r | |
198 | UINT64 Dr2;\r | |
199 | UINT64 Dr3;\r | |
200 | UINT64 Dr6;\r | |
201 | UINT64 Dr7;\r | |
202 | UINT64 Cr0;\r | |
203 | UINT64 Cr1; /* Reserved */\r | |
204 | UINT64 Cr2;\r | |
205 | UINT64 Cr3;\r | |
206 | UINT64 Cr4;\r | |
207 | UINT64 Cr8;\r | |
208 | UINT64 Rflags;\r | |
209 | UINT64 Ldtr;\r | |
210 | UINT64 Tr;\r | |
211 | UINT64 Gdtr[2];\r | |
212 | UINT64 Idtr[2];\r | |
213 | UINT64 Rip;\r | |
214 | UINT64 Gs;\r | |
215 | UINT64 Fs;\r | |
216 | UINT64 Es;\r | |
217 | UINT64 Ds;\r | |
218 | UINT64 Cs;\r | |
219 | UINT64 Ss;\r | |
220 | UINT64 Rdi;\r | |
221 | UINT64 Rsi;\r | |
222 | UINT64 Rbp;\r | |
223 | UINT64 Rsp;\r | |
224 | UINT64 Rbx;\r | |
225 | UINT64 Rdx;\r | |
226 | UINT64 Rcx;\r | |
227 | UINT64 Rax;\r | |
228 | UINT64 R8;\r | |
229 | UINT64 R9;\r | |
230 | UINT64 R10;\r | |
231 | UINT64 R11;\r | |
232 | UINT64 R12;\r | |
233 | UINT64 R13;\r | |
234 | UINT64 R14;\r | |
235 | UINT64 R15;\r | |
236 | } EFI_SYSTEM_CONTEXT_X64;\r | |
237 | \r | |
9319d2c2 LG |
238 | ///\r |
239 | /// Itanium Processor Family Exception types\r | |
240 | ///\r | |
d1f95000 | 241 | #define EXCEPT_IPF_VHTP_TRANSLATION 0\r |
242 | #define EXCEPT_IPF_INSTRUCTION_TLB 1\r | |
243 | #define EXCEPT_IPF_DATA_TLB 2\r | |
244 | #define EXCEPT_IPF_ALT_INSTRUCTION_TLB 3\r | |
245 | #define EXCEPT_IPF_ALT_DATA_TLB 4\r | |
246 | #define EXCEPT_IPF_DATA_NESTED_TLB 5\r | |
247 | #define EXCEPT_IPF_INSTRUCTION_KEY_MISSED 6\r | |
248 | #define EXCEPT_IPF_DATA_KEY_MISSED 7\r | |
249 | #define EXCEPT_IPF_DIRTY_BIT 8\r | |
250 | #define EXCEPT_IPF_INSTRUCTION_ACCESS_BIT 9\r | |
251 | #define EXCEPT_IPF_DATA_ACCESS_BIT 10\r | |
252 | #define EXCEPT_IPF_BREAKPOINT 11\r | |
253 | #define EXCEPT_IPF_EXTERNAL_INTERRUPT 12\r | |
254 | //\r | |
255 | // 13 - 19 reserved\r | |
256 | //\r | |
257 | #define EXCEPT_IPF_PAGE_NOT_PRESENT 20\r | |
258 | #define EXCEPT_IPF_KEY_PERMISSION 21\r | |
259 | #define EXCEPT_IPF_INSTRUCTION_ACCESS_RIGHTS 22\r | |
260 | #define EXCEPT_IPF_DATA_ACCESS_RIGHTS 23\r | |
261 | #define EXCEPT_IPF_GENERAL_EXCEPTION 24\r | |
262 | #define EXCEPT_IPF_DISABLED_FP_REGISTER 25\r | |
263 | #define EXCEPT_IPF_NAT_CONSUMPTION 26\r | |
264 | #define EXCEPT_IPF_SPECULATION 27\r | |
265 | //\r | |
266 | // 28 reserved\r | |
267 | //\r | |
268 | #define EXCEPT_IPF_DEBUG 29\r | |
269 | #define EXCEPT_IPF_UNALIGNED_REFERENCE 30\r | |
270 | #define EXCEPT_IPF_UNSUPPORTED_DATA_REFERENCE 31\r | |
271 | #define EXCEPT_IPF_FP_FAULT 32\r | |
272 | #define EXCEPT_IPF_FP_TRAP 33\r | |
273 | #define EXCEPT_IPF_LOWER_PRIVILEGE_TRANSFER_TRAP 34\r | |
274 | #define EXCEPT_IPF_TAKEN_BRANCH 35\r | |
275 | #define EXCEPT_IPF_SINGLE_STEP 36\r | |
276 | //\r | |
277 | // 37 - 44 reserved\r | |
278 | //\r | |
279 | #define EXCEPT_IPF_IA32_EXCEPTION 45\r | |
280 | #define EXCEPT_IPF_IA32_INTERCEPT 46\r | |
281 | #define EXCEPT_IPF_IA32_INTERRUPT 47\r | |
282 | \r | |
8b6c989b | 283 | ///\r |
284 | /// IPF processor context definition\r | |
285 | ///\r | |
d1f95000 | 286 | typedef struct {\r |
287 | //\r | |
288 | // The first reserved field is necessary to preserve alignment for the correct\r | |
289 | // bits in UNAT and to insure F2 is 16 byte aligned..\r | |
290 | //\r | |
291 | UINT64 Reserved;\r | |
292 | UINT64 R1;\r | |
293 | UINT64 R2;\r | |
294 | UINT64 R3;\r | |
295 | UINT64 R4;\r | |
296 | UINT64 R5;\r | |
297 | UINT64 R6;\r | |
298 | UINT64 R7;\r | |
299 | UINT64 R8;\r | |
300 | UINT64 R9;\r | |
301 | UINT64 R10;\r | |
302 | UINT64 R11;\r | |
303 | UINT64 R12;\r | |
304 | UINT64 R13;\r | |
305 | UINT64 R14;\r | |
306 | UINT64 R15;\r | |
307 | UINT64 R16;\r | |
308 | UINT64 R17;\r | |
309 | UINT64 R18;\r | |
310 | UINT64 R19;\r | |
311 | UINT64 R20;\r | |
312 | UINT64 R21;\r | |
313 | UINT64 R22;\r | |
314 | UINT64 R23;\r | |
315 | UINT64 R24;\r | |
316 | UINT64 R25;\r | |
317 | UINT64 R26;\r | |
318 | UINT64 R27;\r | |
319 | UINT64 R28;\r | |
320 | UINT64 R29;\r | |
321 | UINT64 R30;\r | |
322 | UINT64 R31;\r | |
323 | \r | |
324 | UINT64 F2[2];\r | |
325 | UINT64 F3[2];\r | |
326 | UINT64 F4[2];\r | |
327 | UINT64 F5[2];\r | |
328 | UINT64 F6[2];\r | |
329 | UINT64 F7[2];\r | |
330 | UINT64 F8[2];\r | |
331 | UINT64 F9[2];\r | |
332 | UINT64 F10[2];\r | |
333 | UINT64 F11[2];\r | |
334 | UINT64 F12[2];\r | |
335 | UINT64 F13[2];\r | |
336 | UINT64 F14[2];\r | |
337 | UINT64 F15[2];\r | |
338 | UINT64 F16[2];\r | |
339 | UINT64 F17[2];\r | |
340 | UINT64 F18[2];\r | |
341 | UINT64 F19[2];\r | |
342 | UINT64 F20[2];\r | |
343 | UINT64 F21[2];\r | |
344 | UINT64 F22[2];\r | |
345 | UINT64 F23[2];\r | |
346 | UINT64 F24[2];\r | |
347 | UINT64 F25[2];\r | |
348 | UINT64 F26[2];\r | |
349 | UINT64 F27[2];\r | |
350 | UINT64 F28[2];\r | |
351 | UINT64 F29[2];\r | |
352 | UINT64 F30[2];\r | |
353 | UINT64 F31[2];\r | |
354 | \r | |
355 | UINT64 Pr;\r | |
356 | \r | |
357 | UINT64 B0;\r | |
358 | UINT64 B1;\r | |
359 | UINT64 B2;\r | |
360 | UINT64 B3;\r | |
361 | UINT64 B4;\r | |
362 | UINT64 B5;\r | |
363 | UINT64 B6;\r | |
364 | UINT64 B7;\r | |
365 | \r | |
366 | //\r | |
367 | // application registers\r | |
368 | //\r | |
369 | UINT64 ArRsc;\r | |
370 | UINT64 ArBsp;\r | |
371 | UINT64 ArBspstore;\r | |
372 | UINT64 ArRnat;\r | |
373 | \r | |
374 | UINT64 ArFcr;\r | |
375 | \r | |
376 | UINT64 ArEflag;\r | |
377 | UINT64 ArCsd;\r | |
378 | UINT64 ArSsd;\r | |
379 | UINT64 ArCflg;\r | |
380 | UINT64 ArFsr;\r | |
381 | UINT64 ArFir;\r | |
382 | UINT64 ArFdr;\r | |
383 | \r | |
384 | UINT64 ArCcv;\r | |
385 | \r | |
386 | UINT64 ArUnat;\r | |
387 | \r | |
388 | UINT64 ArFpsr;\r | |
389 | \r | |
390 | UINT64 ArPfs;\r | |
391 | UINT64 ArLc;\r | |
392 | UINT64 ArEc;\r | |
393 | \r | |
394 | //\r | |
395 | // control registers\r | |
396 | //\r | |
397 | UINT64 CrDcr;\r | |
398 | UINT64 CrItm;\r | |
399 | UINT64 CrIva;\r | |
400 | UINT64 CrPta;\r | |
401 | UINT64 CrIpsr;\r | |
402 | UINT64 CrIsr;\r | |
403 | UINT64 CrIip;\r | |
404 | UINT64 CrIfa;\r | |
405 | UINT64 CrItir;\r | |
406 | UINT64 CrIipa;\r | |
407 | UINT64 CrIfs;\r | |
408 | UINT64 CrIim;\r | |
409 | UINT64 CrIha;\r | |
410 | \r | |
411 | //\r | |
412 | // debug registers\r | |
413 | //\r | |
414 | UINT64 Dbr0;\r | |
415 | UINT64 Dbr1;\r | |
416 | UINT64 Dbr2;\r | |
417 | UINT64 Dbr3;\r | |
418 | UINT64 Dbr4;\r | |
419 | UINT64 Dbr5;\r | |
420 | UINT64 Dbr6;\r | |
421 | UINT64 Dbr7;\r | |
422 | \r | |
423 | UINT64 Ibr0;\r | |
424 | UINT64 Ibr1;\r | |
425 | UINT64 Ibr2;\r | |
426 | UINT64 Ibr3;\r | |
427 | UINT64 Ibr4;\r | |
428 | UINT64 Ibr5;\r | |
429 | UINT64 Ibr6;\r | |
430 | UINT64 Ibr7;\r | |
431 | \r | |
432 | //\r | |
433 | // virtual registers - nat bits for R1-R31\r | |
434 | //\r | |
435 | UINT64 IntNat;\r | |
436 | \r | |
437 | } EFI_SYSTEM_CONTEXT_IPF;\r | |
438 | \r | |
9319d2c2 LG |
439 | ///\r |
440 | /// EBC processor exception types\r | |
441 | ///\r | |
d1f95000 | 442 | #define EXCEPT_EBC_UNDEFINED 0\r |
443 | #define EXCEPT_EBC_DIVIDE_ERROR 1\r | |
444 | #define EXCEPT_EBC_DEBUG 2\r | |
445 | #define EXCEPT_EBC_BREAKPOINT 3\r | |
446 | #define EXCEPT_EBC_OVERFLOW 4\r | |
992f22b9 | 447 | #define EXCEPT_EBC_INVALID_OPCODE 5 ///< opcode out of range\r |
d1f95000 | 448 | #define EXCEPT_EBC_STACK_FAULT 6\r |
449 | #define EXCEPT_EBC_ALIGNMENT_CHECK 7\r | |
992f22b9 LG |
450 | #define EXCEPT_EBC_INSTRUCTION_ENCODING 8 ///< malformed instruction\r |
451 | #define EXCEPT_EBC_BAD_BREAK 9 ///< BREAK 0 or undefined BREAK\r | |
452 | #define EXCEPT_EBC_STEP 10 ///< to support debug stepping\r | |
99e8ed21 | 453 | ///\r |
454 | /// For coding convenience, define the maximum valid EBC exception.\r | |
455 | ///\r | |
d1f95000 | 456 | #define MAX_EBC_EXCEPTION EXCEPT_EBC_STEP\r |
457 | \r | |
99e8ed21 | 458 | ///\r |
459 | /// EBC processor context definition\r | |
460 | ///\r | |
d1f95000 | 461 | typedef struct {\r |
462 | UINT64 R0;\r | |
463 | UINT64 R1;\r | |
464 | UINT64 R2;\r | |
465 | UINT64 R3;\r | |
466 | UINT64 R4;\r | |
467 | UINT64 R5;\r | |
468 | UINT64 R6;\r | |
469 | UINT64 R7;\r | |
470 | UINT64 Flags;\r | |
471 | UINT64 ControlFlags;\r | |
472 | UINT64 Ip;\r | |
473 | } EFI_SYSTEM_CONTEXT_EBC;\r | |
474 | \r | |
99e8ed21 | 475 | ///\r |
476 | /// Universal EFI_SYSTEM_CONTEXT definition\r | |
477 | ///\r | |
d1f95000 | 478 | typedef union {\r |
479 | EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;\r | |
480 | EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;\r | |
481 | EFI_SYSTEM_CONTEXT_X64 *SystemContextX64;\r | |
482 | EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;\r | |
483 | } EFI_SYSTEM_CONTEXT;\r | |
484 | \r | |
485 | //\r | |
486 | // DebugSupport callback function prototypes\r | |
487 | //\r | |
488 | \r | |
489 | /** \r | |
490 | Registers and enables an exception callback function for the specified exception.\r | |
491 | \r | |
030cd1a2 | 492 | @param ExceptionType Exception types in EBC, IA-32, x64, or IPF\r |
d1f95000 | 493 | @param SystemContext Exception content.\r |
494 | \r | |
495 | **/\r | |
496 | typedef\r | |
497 | VOID\r | |
8b13229b | 498 | (*EFI_EXCEPTION_CALLBACK)(\r |
d1f95000 | 499 | IN EFI_EXCEPTION_TYPE ExceptionType,\r |
500 | IN OUT EFI_SYSTEM_CONTEXT SystemContext\r | |
501 | );\r | |
502 | \r | |
503 | /** \r | |
504 | Registers and enables the on-target debug agent's periodic entry point.\r | |
505 | \r | |
506 | @param SystemContext Exception content.\r | |
507 | \r | |
508 | **/\r | |
509 | typedef\r | |
510 | VOID\r | |
8b13229b | 511 | (*EFI_PERIODIC_CALLBACK)(\r |
d1f95000 | 512 | IN OUT EFI_SYSTEM_CONTEXT SystemContext\r |
513 | );\r | |
514 | \r | |
8b6c989b | 515 | ///\r |
516 | /// Machine type definition\r | |
517 | ///\r | |
d1f95000 | 518 | typedef enum {\r |
8b6c989b | 519 | IsaIa32 = IMAGE_FILE_MACHINE_I386, ///< 0x014C\r |
520 | IsaX64 = IMAGE_FILE_MACHINE_X64, ///< 0x8664\r | |
521 | IsaIpf = IMAGE_FILE_MACHINE_IA64, ///< 0x0200\r | |
522 | IsaEbc = IMAGE_FILE_MACHINE_EBC ///< 0x0EBC\r | |
d1f95000 | 523 | } EFI_INSTRUCTION_SET_ARCHITECTURE;\r |
524 | \r | |
525 | \r | |
526 | //\r | |
527 | // DebugSupport member function definitions\r | |
528 | //\r | |
529 | \r | |
530 | /** \r | |
531 | Returns the maximum value that may be used for the ProcessorIndex parameter in\r | |
532 | RegisterPeriodicCallback() and RegisterExceptionCallback(). \r | |
533 | \r | |
534 | @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r | |
535 | @param MaxProcessorIndex Pointer to a caller-allocated UINTN in which the maximum supported\r | |
536 | processor index is returned. \r | |
537 | \r | |
538 | @retval EFI_SUCCESS The function completed successfully. \r | |
539 | \r | |
540 | **/\r | |
541 | typedef\r | |
542 | EFI_STATUS\r | |
8b13229b | 543 | (EFIAPI *EFI_GET_MAXIMUM_PROCESSOR_INDEX)(\r |
d1f95000 | 544 | IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r |
545 | OUT UINTN *MaxProcessorIndex\r | |
546 | );\r | |
547 | \r | |
548 | /** \r | |
549 | Registers a function to be called back periodically in interrupt context.\r | |
550 | \r | |
551 | @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r | |
552 | @param ProcessorIndex Specifies which processor the callback function applies to.\r | |
553 | @param PeriodicCallback A pointer to a function of type PERIODIC_CALLBACK that is the main\r | |
554 | periodic entry point of the debug agent.\r | |
555 | \r | |
556 | @retval EFI_SUCCESS The function completed successfully. \r | |
557 | @retval EFI_ALREADY_STARTED Non-NULL PeriodicCallback parameter when a callback\r | |
558 | function was previously registered. \r | |
559 | @retval EFI_OUT_OF_RESOURCES System has insufficient memory resources to register new callback \r | |
560 | function. \r | |
561 | \r | |
562 | **/\r | |
563 | typedef\r | |
564 | EFI_STATUS\r | |
8b13229b | 565 | (EFIAPI *EFI_REGISTER_PERIODIC_CALLBACK)(\r |
d1f95000 | 566 | IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r |
567 | IN UINTN ProcessorIndex,\r | |
568 | IN EFI_PERIODIC_CALLBACK PeriodicCallback\r | |
569 | );\r | |
570 | \r | |
571 | /** \r | |
572 | Registers a function to be called when a given processor exception occurs.\r | |
573 | \r | |
574 | @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r | |
575 | @param ProcessorIndex Specifies which processor the callback function applies to.\r | |
89df7f9d | 576 | @param ExceptionCallback A pointer to a function of type EXCEPTION_CALLBACK that is called\r |
d1f95000 | 577 | when the processor exception specified by ExceptionType occurs. \r |
578 | @param ExceptionType Specifies which processor exception to hook. \r | |
579 | \r | |
580 | @retval EFI_SUCCESS The function completed successfully. \r | |
581 | @retval EFI_ALREADY_STARTED Non-NULL PeriodicCallback parameter when a callback\r | |
582 | function was previously registered. \r | |
583 | @retval EFI_OUT_OF_RESOURCES System has insufficient memory resources to register new callback \r | |
584 | function. \r | |
585 | \r | |
586 | **/\r | |
587 | typedef\r | |
588 | EFI_STATUS\r | |
8b13229b | 589 | (EFIAPI *EFI_REGISTER_EXCEPTION_CALLBACK)(\r |
d1f95000 | 590 | IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r |
591 | IN UINTN ProcessorIndex,\r | |
592 | IN EFI_EXCEPTION_CALLBACK ExceptionCallback,\r | |
593 | IN EFI_EXCEPTION_TYPE ExceptionType\r | |
594 | );\r | |
595 | \r | |
596 | /** \r | |
597 | Invalidates processor instruction cache for a memory range. Subsequent execution in this range\r | |
598 | causes a fresh memory fetch to retrieve code to be executed. \r | |
599 | \r | |
600 | @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r | |
601 | @param ProcessorIndex Specifies which processor's instruction cache is to be invalidated.\r | |
602 | @param Start Specifies the physical base of the memory range to be invalidated. \r | |
603 | @param Length Specifies the minimum number of bytes in the processor's instruction\r | |
604 | cache to invalidate. \r | |
605 | \r | |
606 | @retval EFI_SUCCESS The function completed successfully. \r | |
607 | \r | |
608 | **/\r | |
609 | typedef\r | |
610 | EFI_STATUS\r | |
8b13229b | 611 | (EFIAPI *EFI_INVALIDATE_INSTRUCTION_CACHE)(\r |
d1f95000 | 612 | IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r |
613 | IN UINTN ProcessorIndex,\r | |
614 | IN VOID *Start,\r | |
615 | IN UINT64 Length\r | |
616 | );\r | |
617 | \r | |
44717a39 | 618 | ///\r |
619 | /// This protocol provides the services to allow the debug agent to register \r | |
620 | /// callback functions that are called either periodically or when specific \r | |
621 | /// processor exceptions occur.\r | |
622 | ///\r | |
d1f95000 | 623 | struct _EFI_DEBUG_SUPPORT_PROTOCOL {\r |
44717a39 | 624 | ///\r |
625 | /// Declares the processor architecture for this instance of the EFI Debug Support protocol.\r | |
626 | ///\r | |
d1f95000 | 627 | EFI_INSTRUCTION_SET_ARCHITECTURE Isa;\r |
628 | EFI_GET_MAXIMUM_PROCESSOR_INDEX GetMaximumProcessorIndex;\r | |
629 | EFI_REGISTER_PERIODIC_CALLBACK RegisterPeriodicCallback;\r | |
630 | EFI_REGISTER_EXCEPTION_CALLBACK RegisterExceptionCallback;\r | |
631 | EFI_INVALIDATE_INSTRUCTION_CACHE InvalidateInstructionCache;\r | |
632 | };\r | |
633 | \r | |
634 | extern EFI_GUID gEfiDebugSupportProtocolGuid;\r | |
635 | \r | |
636 | #endif \r |