]>
Commit | Line | Data |
---|---|---|
07c6a47e ED |
1 | /** @file\r |
2 | MM CPU I/O 2 protocol as defined in the PI 1.5 specification.\r | |
3 | \r | |
4 | This protocol provides CPU I/O and memory access within MM.\r | |
5 | \r | |
6 | Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r | |
9344f092 | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
07c6a47e ED |
8 | \r |
9 | **/\r | |
10 | \r | |
11 | #ifndef _MM_CPU_IO_H_\r | |
12 | #define _MM_CPU_IO_H_\r | |
13 | \r | |
14 | #define EFI_MM_CPU_IO_PROTOCOL_GUID \\r | |
15 | { \\r | |
16 | 0x3242A9D8, 0xCE70, 0x4AA0, { 0x95, 0x5D, 0x5E, 0x7B, 0x14, 0x0D, 0xE4, 0xD2 } \\r | |
17 | }\r | |
18 | \r | |
19 | typedef struct _EFI_MM_CPU_IO_PROTOCOL EFI_MM_CPU_IO_PROTOCOL;\r | |
20 | \r | |
21 | ///\r | |
22 | /// Width of the MM CPU I/O operations\r | |
23 | ///\r | |
24 | typedef enum {\r | |
25 | MM_IO_UINT8 = 0,\r | |
26 | MM_IO_UINT16 = 1,\r | |
27 | MM_IO_UINT32 = 2,\r | |
28 | MM_IO_UINT64 = 3\r | |
29 | } EFI_MM_IO_WIDTH;\r | |
30 | \r | |
31 | /**\r | |
32 | Provides the basic memory and I/O interfaces used toabstract accesses to devices.\r | |
33 | \r | |
34 | The I/O operations are carried out exactly as requested. The caller is\r | |
35 | responsible for any alignment and I/O width issues that the bus, device,\r | |
36 | platform, or type of I/O might require.\r | |
37 | \r | |
38 | @param[in] This The EFI_MM_CPU_IO_PROTOCOL instance.\r | |
39 | @param[in] Width Signifies the width of the I/O operations.\r | |
40 | @param[in] Address The base address of the I/O operations. The caller is\r | |
41 | responsible for aligning the Address if required.\r | |
42 | @param[in] Count The number of I/O operations to perform.\r | |
43 | @param[in,out] Buffer For read operations, the destination buffer to store\r | |
44 | the results. For write operations, the source buffer\r | |
45 | from which to write data.\r | |
46 | \r | |
47 | @retval EFI_SUCCESS The data was read from or written to the device.\r | |
48 | @retval EFI_UNSUPPORTED The Address is not valid for this system.\r | |
49 | @retval EFI_INVALID_PARAMETER Width or Count, or both, were invalid.\r | |
50 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack\r | |
51 | of resources.\r | |
52 | **/\r | |
53 | typedef\r | |
54 | EFI_STATUS\r | |
55 | (EFIAPI *EFI_MM_CPU_IO)(\r | |
56 | IN CONST EFI_MM_CPU_IO_PROTOCOL *This,\r | |
57 | IN EFI_MM_IO_WIDTH Width,\r | |
58 | IN UINT64 Address,\r | |
59 | IN UINTN Count,\r | |
60 | IN OUT VOID *Buffer\r | |
61 | );\r | |
62 | \r | |
63 | typedef struct {\r | |
64 | ///\r | |
65 | /// This service provides the various modalities of memory and I/O read.\r | |
66 | ///\r | |
67 | EFI_MM_CPU_IO Read;\r | |
68 | ///\r | |
69 | /// This service provides the various modalities of memory and I/O write.\r | |
70 | ///\r | |
71 | EFI_MM_CPU_IO Write;\r | |
72 | } EFI_MM_IO_ACCESS;\r | |
73 | \r | |
74 | ///\r | |
75 | /// MM CPU I/O Protocol provides CPU I/O and memory access within MM.\r | |
76 | ///\r | |
77 | struct _EFI_MM_CPU_IO_PROTOCOL {\r | |
78 | ///\r | |
79 | /// Allows reads and writes to memory-mapped I/O space.\r | |
80 | ///\r | |
81 | EFI_MM_IO_ACCESS Mem;\r | |
82 | ///\r | |
83 | /// Allows reads and writes to I/O space.\r | |
84 | ///\r | |
85 | EFI_MM_IO_ACCESS Io;\r | |
86 | };\r | |
87 | \r | |
88 | extern EFI_GUID gEfiMmCpuIoProtocolGuid;\r | |
89 | \r | |
90 | #endif\r |