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73c31a3d | 1 | /** @file\r |
9095d37b LG |
2 | This file declares PlatfromOpRom protocols that provide the interface between\r |
3 | the PCI bus driver/PCI Host Bridge Resource Allocation driver and a platform-specific\r | |
4 | driver to describe the unique features of a platform.\r | |
a3ebc85e | 5 | This protocol is optional.\r |
9095d37b LG |
6 | \r |
7 | Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r | |
9344f092 | 8 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
73c31a3d | 9 | \r |
10 | @par Revision Reference:\r | |
9095d37b | 11 | This Protocol is defined in UEFI Platform Initialization Specification 1.2\r |
73c31a3d | 12 | Volume 5: Standards\r |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #ifndef _PCI_PLATFORM_H_\r | |
17 | #define _PCI_PLATFORM_H_\r | |
18 | \r | |
19 | ///\r | |
20 | /// This file must be included because the EFI_PCI_PLATFORM_PROTOCOL uses\r | |
af2dc6a7 | 21 | /// EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE.\r |
73c31a3d | 22 | ///\r |
23 | #include <Protocol/PciHostBridgeResourceAllocation.h>\r | |
24 | \r | |
25 | ///\r | |
af2dc6a7 | 26 | /// Global ID for the EFI_PCI_PLATFORM_PROTOCOL.\r |
73c31a3d | 27 | ///\r |
28 | #define EFI_PCI_PLATFORM_PROTOCOL_GUID \\r | |
29 | { \\r | |
30 | 0x7d75280, 0x27d4, 0x4d69, {0x90, 0xd0, 0x56, 0x43, 0xe2, 0x38, 0xb3, 0x41} \\r | |
31 | }\r | |
32 | \r | |
33 | ///\r | |
af2dc6a7 | 34 | /// Forward declaration for EFI_PCI_PLATFORM_PROTOCOL.\r |
73c31a3d | 35 | ///\r |
36 | typedef struct _EFI_PCI_PLATFORM_PROTOCOL EFI_PCI_PLATFORM_PROTOCOL;\r | |
37 | \r | |
38 | ///\r | |
a3ebc85e | 39 | /// EFI_PCI_PLATFORM_POLICY that is a bitmask with the following legal combinations:\r |
73c31a3d | 40 | /// - EFI_RESERVE_NONE_IO_ALIAS:<BR>\r |
41 | /// Does not set aside either ISA or VGA I/O resources during PCI\r | |
42 | /// enumeration. By using this selection, the platform indicates that it does\r | |
43 | /// not want to support a PCI device that requires ISA or legacy VGA\r | |
44 | /// resources. If a PCI device driver asks for these resources, the request\r | |
45 | /// will be turned down.\r | |
46 | /// - EFI_RESERVE_ISA_IO_ALIAS | EFI_RESERVE_VGA_IO_ALIAS:<BR>\r | |
47 | /// Sets aside the ISA I/O range and all the aliases during PCI\r | |
48 | /// enumeration. VGA I/O ranges and aliases are included in ISA alias\r | |
af2dc6a7 | 49 | /// ranges. In this scheme, seventy-five percent of the I/O space remains unused.\r |
73c31a3d | 50 | /// By using this selection, the platform indicates that it wants to support\r |
51 | /// PCI devices that require the following, at the cost of wasted I/O space:\r | |
52 | /// ISA range and its aliases\r | |
53 | /// Legacy VGA range and its aliases\r | |
54 | /// The PCI bus driver will not allocate I/O addresses out of the ISA I/O\r | |
55 | /// range and its aliases. The following are the ISA I/O ranges:\r | |
56 | /// - n100..n3FF\r | |
57 | /// - n500..n7FF\r | |
58 | /// - n900..nBFF\r | |
59 | /// - nD00..nFFF\r | |
60 | ///\r | |
61 | /// In this case, the PCI bus driver will ask the PCI host bridge driver for\r | |
62 | /// larger I/O ranges. The PCI host bridge driver is not aware of the ISA\r | |
63 | /// aliasing policy and merely attempts to allocate the requested ranges.\r | |
64 | /// The first device that requests the legacy VGA range will get all the\r | |
65 | /// legacy VGA range plus its aliased addresses forwarded to it. The first\r | |
66 | /// device that requests the legacy ISA range will get all the legacy ISA\r | |
af2dc6a7 | 67 | /// range, plus its aliased addresses, forwarded to it.\r |
73c31a3d | 68 | /// - EFI_RESERVE_ISA_IO_NO_ALIAS | EFI_RESERVE_VGA_IO_ALIAS:<BR>\r |
a025815c | 69 | /// Sets aside the ISA I/O range (0x100 - 0x3FF) during PCI enumeration\r |
73c31a3d | 70 | /// and the aliases of the VGA I/O ranges. By using this selection, the\r |
71 | /// platform indicates that it will support VGA devices that require VGA\r | |
72 | /// ranges, including those that require VGA aliases. The platform further\r | |
e8b9799c | 73 | /// wants to support non-VGA devices that ask for the ISA range (0x100 -\r |
73c31a3d | 74 | /// 3FF), but not if it also asks for the ISA aliases. The PCI bus driver will\r |
e8b9799c | 75 | /// not allocate I/O addresses out of the legacy ISA I/O range (0x100 -\r |
73c31a3d | 76 | /// 0x3FF) range or the aliases of the VGA I/O range. If a PCI device\r |
77 | /// driver asks for the ISA I/O ranges, including aliases, the request will be\r | |
78 | /// turned down. The first device that requests the legacy VGA range will\r | |
79 | /// get all the legacy VGA range plus its aliased addresses forwarded to\r | |
80 | /// it. When the legacy VGA device asks for legacy VGA ranges and its\r | |
81 | /// aliases, all the upstream PCI-to-PCI bridges must be set up to perform\r | |
82 | /// 10-bit decode on legacy VGA ranges. To prevent two bridges from\r | |
83 | /// positively decoding the same address, all PCI-to-PCI bridges that are\r | |
84 | /// peers to this bridge will have to be set up to not decode ISA aliased\r | |
85 | /// ranges. In that case, all the devices behind the peer bridges can\r | |
86 | /// occupy only I/O addresses that are not ISA aliases. This is a limitation\r | |
87 | /// of PCI-to-PCI bridges and is described in the white paper PCI-to-PCI\r | |
88 | /// Bridges and Card Bus Controllers on Windows 2000, Windows XP,\r | |
89 | /// and Windows Server 2003. The PCI enumeration process must be\r | |
90 | /// cognizant of this restriction.\r | |
91 | /// - EFI_RESERVE_ISA_IO_NO_ALIAS | EFI_RESERVE_VGA_IO_NO_ALIAS:<BR>\r | |
a025815c | 92 | /// Sets aside the ISA I/O range (0x100 - 0x3FF) during PCI enumeration.\r |
73c31a3d | 93 | /// VGA I/O ranges are included in the ISA range. By using this selection,\r |
94 | /// the platform indicates that it wants to support PCI devices that require\r | |
95 | /// the ISA range and legacy VGA range, but it does not want to support\r | |
96 | /// devices that require ISA alias ranges or VGA alias ranges. The PCI\r | |
97 | /// bus driver will not allocate I/O addresses out of the legacy ISA I/O\r | |
a025815c | 98 | /// range (0x100-0x3FF). If a PCI device driver asks for the ISA I/O\r |
73c31a3d | 99 | /// ranges, including aliases, the request will be turned down. By using\r |
100 | /// this selection, the platform indicates that it will support VGA devices\r | |
101 | /// that require VGA ranges, but it will not support VGA devices that\r | |
102 | /// require VGA aliases. To truly support 16-bit VGA decode, all the PCIto-\r | |
103 | /// PCI bridges that are upstream to a VGA device, as well as\r | |
104 | /// upstream to the parent PCI root bridge, must support 16-bit VGA I/O\r | |
105 | /// decode. See the PCI-to-PCI Bridge Architecture Specification for\r | |
106 | /// information regarding the 16-bit VGA decode support. This\r | |
107 | /// requirement must hold true for every VGA device in the system. If any\r | |
108 | /// of these bridges does not support 16-bit VGA decode, it will positively\r | |
109 | /// decode all the aliases of the VGA I/O ranges and this selection must\r | |
110 | /// be treated like EFI_RESERVE_ISA_IO_NO_ALIAS |\r | |
111 | /// EFI_RESERVE_VGA_IO_ALIAS.\r | |
112 | ///\r | |
113 | typedef UINT32 EFI_PCI_PLATFORM_POLICY;\r | |
114 | \r | |
115 | ///\r | |
116 | /// Does not set aside either ISA or VGA I/O resources during PCI\r | |
117 | /// enumeration.\r | |
118 | ///\r | |
119 | #define EFI_RESERVE_NONE_IO_ALIAS 0x0000\r | |
120 | \r | |
121 | ///\r | |
af2dc6a7 | 122 | /// Sets aside ISA I/O range and all aliases:\r |
73c31a3d | 123 | /// - n100..n3FF\r |
124 | /// - n500..n7FF\r | |
125 | /// - n900..nBFF\r | |
af2dc6a7 | 126 | /// - nD00..nFFF.\r |
73c31a3d | 127 | ///\r |
128 | #define EFI_RESERVE_ISA_IO_ALIAS 0x0001\r | |
129 | \r | |
130 | ///\r | |
af2dc6a7 | 131 | /// Sets aside ISA I/O range 0x100-0x3FF.\r |
73c31a3d | 132 | ///\r |
133 | #define EFI_RESERVE_ISA_IO_NO_ALIAS 0x0002\r | |
134 | \r | |
135 | ///\r | |
af2dc6a7 | 136 | /// Sets aside VGA I/O ranges and all aliases.\r |
73c31a3d | 137 | ///\r |
138 | #define EFI_RESERVE_VGA_IO_ALIAS 0x0004\r | |
139 | \r | |
140 | ///\r | |
af2dc6a7 | 141 | /// Sets aside VGA I/O ranges\r |
73c31a3d | 142 | ///\r |
143 | #define EFI_RESERVE_VGA_IO_NO_ALIAS 0x0008\r | |
144 | \r | |
145 | ///\r | |
146 | /// EFI_PCI_EXECUTION_PHASE is used to call a platform protocol and execute\r | |
147 | /// platform-specific code.\r | |
148 | ///\r | |
149 | typedef enum {\r | |
150 | ///\r | |
151 | /// The phase that indicates the entry point to the PCI Bus Notify phase. This\r | |
152 | /// platform hook is called before the PCI bus driver calls the\r | |
153 | /// EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL driver.\r | |
154 | ///\r | |
155 | BeforePciHostBridge = 0,\r | |
156 | ///\r | |
157 | /// The phase that indicates the entry point to the PCI Bus Notify phase. This\r | |
158 | /// platform hook is called before the PCI bus driver calls the\r | |
159 | /// EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL driver.\r | |
160 | ///\r | |
161 | ChipsetEntry = 0,\r | |
162 | ///\r | |
163 | /// The phase that indicates the exit point to the Chipset Notify phase before\r | |
164 | /// returning to the PCI Bus Driver Notify phase. This platform hook is called after\r | |
165 | /// the PCI bus driver calls the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r | |
166 | /// driver.\r | |
167 | ///\r | |
168 | AfterPciHostBridge = 1,\r | |
169 | ///\r | |
170 | /// The phase that indicates the exit point to the Chipset Notify phase before\r | |
171 | /// returning to the PCI Bus Driver Notify phase. This platform hook is called after\r | |
172 | /// the PCI bus driver calls the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r | |
173 | /// driver.\r | |
174 | ///\r | |
175 | ChipsetExit = 1,\r | |
176 | MaximumChipsetPhase\r | |
177 | } EFI_PCI_EXECUTION_PHASE;\r | |
178 | \r | |
179 | typedef EFI_PCI_EXECUTION_PHASE EFI_PCI_CHIPSET_EXECUTION_PHASE;\r | |
180 | \r | |
181 | /**\r | |
182 | The notification from the PCI bus enumerator to the platform that it is\r | |
183 | about to enter a certain phase during the enumeration process.\r | |
184 | \r | |
185 | The PlatformNotify() function can be used to notify the platform driver so that\r | |
186 | it can perform platform-specific actions. No specific actions are required.\r | |
187 | Eight notification points are defined at this time. More synchronization points\r | |
188 | may be added as required in the future. The PCI bus driver calls the platform driver\r | |
189 | twice for every Phase-once before the PCI Host Bridge Resource Allocation Protocol\r | |
190 | driver is notified, and once after the PCI Host Bridge Resource Allocation Protocol\r | |
191 | driver has been notified.\r | |
192 | This member function may not perform any error checking on the input parameters. It\r | |
193 | also does not return any error codes. If this member function detects any error condition,\r | |
194 | it needs to handle those errors on its own because there is no way to surface any\r | |
195 | errors to the caller.\r | |
196 | \r | |
af2dc6a7 | 197 | @param[in] This The pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.\r |
73c31a3d | 198 | @param[in] HostBridge The handle of the host bridge controller.\r |
199 | @param[in] Phase The phase of the PCI bus enumeration.\r | |
1522219f | 200 | @param[in] ExecPhase Defines the execution phase of the PCI chipset driver.\r |
73c31a3d | 201 | \r |
202 | @retval EFI_SUCCESS The function completed successfully.\r | |
203 | \r | |
204 | **/\r | |
205 | typedef\r | |
206 | EFI_STATUS\r | |
207 | (EFIAPI *EFI_PCI_PLATFORM_PHASE_NOTIFY)(\r | |
208 | IN EFI_PCI_PLATFORM_PROTOCOL *This,\r | |
209 | IN EFI_HANDLE HostBridge,\r | |
210 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase,\r | |
1522219f | 211 | IN EFI_PCI_EXECUTION_PHASE ExecPhase\r |
73c31a3d | 212 | );\r |
213 | \r | |
214 | /**\r | |
215 | The notification from the PCI bus enumerator to the platform for each PCI\r | |
216 | controller at several predefined points during PCI controller initialization.\r | |
217 | \r | |
218 | The PlatformPrepController() function can be used to notify the platform driver so that\r | |
219 | it can perform platform-specific actions. No specific actions are required.\r | |
220 | Several notification points are defined at this time. More synchronization points may be\r | |
221 | added as required in the future. The PCI bus driver calls the platform driver twice for\r | |
222 | every PCI controller-once before the PCI Host Bridge Resource Allocation Protocol driver\r | |
223 | is notified, and once after the PCI Host Bridge Resource Allocation Protocol driver has\r | |
224 | been notified.\r | |
225 | This member function may not perform any error checking on the input parameters. It also\r | |
226 | does not return any error codes. If this member function detects any error condition, it\r | |
227 | needs to handle those errors on its own because there is no way to surface any errors to\r | |
228 | the caller.\r | |
229 | \r | |
af2dc6a7 | 230 | @param[in] This The pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.\r |
73c31a3d | 231 | @param[in] HostBridge The associated PCI host bridge handle.\r |
232 | @param[in] RootBridge The associated PCI root bridge handle.\r | |
233 | @param[in] PciAddress The address of the PCI device on the PCI bus.\r | |
234 | @param[in] Phase The phase of the PCI controller enumeration.\r | |
1522219f | 235 | @param[in] ExecPhase Defines the execution phase of the PCI chipset driver.\r |
73c31a3d | 236 | \r |
237 | @retval EFI_SUCCESS The function completed successfully.\r | |
238 | \r | |
239 | **/\r | |
240 | typedef\r | |
241 | EFI_STATUS\r | |
242 | (EFIAPI *EFI_PCI_PLATFORM_PREPROCESS_CONTROLLER)(\r | |
243 | IN EFI_PCI_PLATFORM_PROTOCOL *This,\r | |
244 | IN EFI_HANDLE HostBridge,\r | |
245 | IN EFI_HANDLE RootBridge,\r | |
246 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,\r | |
247 | IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase,\r | |
1522219f | 248 | IN EFI_PCI_EXECUTION_PHASE ExecPhase\r |
73c31a3d | 249 | );\r |
250 | \r | |
251 | /**\r | |
252 | Retrieves the platform policy regarding enumeration.\r | |
253 | \r | |
254 | The GetPlatformPolicy() function retrieves the platform policy regarding PCI\r | |
255 | enumeration. The PCI bus driver and the PCI Host Bridge Resource Allocation Protocol\r | |
256 | driver can call this member function to retrieve the policy.\r | |
257 | \r | |
af2dc6a7 | 258 | @param[in] This The pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.\r |
73c31a3d | 259 | @param[out] PciPolicy The platform policy with respect to VGA and ISA aliasing.\r |
260 | \r | |
261 | @retval EFI_SUCCESS The function completed successfully.\r | |
262 | @retval EFI_INVALID_PARAMETER PciPolicy is NULL.\r | |
263 | \r | |
264 | **/\r | |
265 | typedef\r | |
266 | EFI_STATUS\r | |
267 | (EFIAPI *EFI_PCI_PLATFORM_GET_PLATFORM_POLICY)(\r | |
1522219f | 268 | IN CONST EFI_PCI_PLATFORM_PROTOCOL *This,\r |
269 | OUT EFI_PCI_PLATFORM_POLICY *PciPolicy\r | |
73c31a3d | 270 | );\r |
271 | \r | |
272 | /**\r | |
273 | Gets the PCI device's option ROM from a platform-specific location.\r | |
274 | \r | |
275 | The GetPciRom() function gets the PCI device's option ROM from a platform-specific location.\r | |
276 | The option ROM will be loaded into memory. This member function is used to return an image\r | |
277 | that is packaged as a PCI 2.2 option ROM. The image may contain both legacy and EFI option\r | |
278 | ROMs. See the UEFI 2.0 Specification for details. This member function can be used to return\r | |
279 | option ROM images for embedded controllers. Option ROMs for embedded controllers are typically\r | |
280 | stored in platform-specific storage, and this member function can retrieve it from that storage\r | |
281 | and return it to the PCI bus driver. The PCI bus driver will call this member function before\r | |
282 | scanning the ROM that is attached to any controller, which allows a platform to specify a ROM\r | |
283 | image that is different from the ROM image on a PCI card.\r | |
284 | \r | |
af2dc6a7 | 285 | @param[in] This The pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.\r |
73c31a3d | 286 | @param[in] PciHandle The handle of the PCI device.\r |
287 | @param[out] RomImage If the call succeeds, the pointer to the pointer to the option ROM image.\r | |
288 | Otherwise, this field is undefined. The memory for RomImage is allocated\r | |
289 | by EFI_PCI_PLATFORM_PROTOCOL.GetPciRom() using the EFI Boot Service AllocatePool().\r | |
290 | It is the caller's responsibility to free the memory using the EFI Boot Service\r | |
291 | FreePool(), when the caller is done with the option ROM.\r | |
292 | @param[out] RomSize If the call succeeds, a pointer to the size of the option ROM size. Otherwise,\r | |
293 | this field is undefined.\r | |
294 | \r | |
295 | @retval EFI_SUCCESS The option ROM was available for this device and loaded into memory.\r | |
296 | @retval EFI_NOT_FOUND No option ROM was available for this device.\r | |
297 | @retval EFI_OUT_OF_RESOURCES No memory was available to load the option ROM.\r | |
af2dc6a7 | 298 | @retval EFI_DEVICE_ERROR An error occurred in obtaining the option ROM.\r |
73c31a3d | 299 | \r |
300 | **/\r | |
301 | typedef\r | |
302 | EFI_STATUS\r | |
303 | (EFIAPI *EFI_PCI_PLATFORM_GET_PCI_ROM)(\r | |
1522219f | 304 | IN CONST EFI_PCI_PLATFORM_PROTOCOL *This,\r |
305 | IN EFI_HANDLE PciHandle,\r | |
306 | OUT VOID **RomImage,\r | |
307 | OUT UINTN *RomSize\r | |
73c31a3d | 308 | );\r |
309 | \r | |
310 | ///\r | |
311 | /// This protocol provides the interface between the PCI bus driver/PCI Host\r | |
312 | /// Bridge Resource Allocation driver and a platform-specific driver to describe\r | |
313 | /// the unique features of a platform.\r | |
314 | ///\r | |
315 | struct _EFI_PCI_PLATFORM_PROTOCOL {\r | |
316 | ///\r | |
9095d37b | 317 | /// The notification from the PCI bus enumerator to the platform that it is about to\r |
73c31a3d | 318 | /// enter a certain phase during the enumeration process.\r |
319 | ///\r | |
320 | EFI_PCI_PLATFORM_PHASE_NOTIFY PlatformNotify;\r | |
321 | ///\r | |
9095d37b | 322 | /// The notification from the PCI bus enumerator to the platform for each PCI\r |
73c31a3d | 323 | /// controller at several predefined points during PCI controller initialization.\r |
9095d37b | 324 | ///\r |
73c31a3d | 325 | EFI_PCI_PLATFORM_PREPROCESS_CONTROLLER PlatformPrepController;\r |
9095d37b | 326 | ///\r |
73c31a3d | 327 | /// Retrieves the platform policy regarding enumeration.\r |
328 | ///\r | |
329 | EFI_PCI_PLATFORM_GET_PLATFORM_POLICY GetPlatformPolicy;\r | |
330 | ///\r | |
e8b9799c | 331 | /// Gets the PCI device's option ROM from a platform-specific location.\r |
73c31a3d | 332 | ///\r |
333 | EFI_PCI_PLATFORM_GET_PCI_ROM GetPciRom;\r | |
334 | };\r | |
335 | \r | |
336 | extern EFI_GUID gEfiPciPlatformProtocolGuid;\r | |
337 | \r | |
338 | #endif\r |