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959ccb23 | 1 | /** @file\r |
2 | This header file contains all of the PXE type definitions,\r | |
3 | structure prototypes, global variables and constants that\r | |
4 | are needed for porting PXE to EFI.\r | |
4ccd9566 | 5 | \r |
9095d37b | 6 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r |
9344f092 | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
4ccd9566 | 8 | \r |
959ccb23 | 9 | @par Revision Reference:\r |
10 | 32/64-bit PXE specification:\r | |
af2dc6a7 | 11 | alpha-4, 99-Dec-17.\r |
993702aa | 12 | \r |
959ccb23 | 13 | **/\r |
14 | \r | |
15 | #ifndef __EFI_PXE_H__\r | |
16 | #define __EFI_PXE_H__\r | |
17 | \r | |
18 | #pragma pack(1)\r | |
19 | \r | |
959ccb23 | 20 | #define PXE_BUSTYPE(a, b, c, d) \\r |
21 | ( \\r | |
22 | (((PXE_UINT32) (d) & 0xFF) << 24) | (((PXE_UINT32) (c) & 0xFF) << 16) | (((PXE_UINT32) (b) & 0xFF) << 8) | \\r | |
23 | ((PXE_UINT32) (a) & 0xFF) \\r | |
24 | )\r | |
25 | \r | |
8b13229b | 26 | ///\r |
af2dc6a7 | 27 | /// UNDI ROM ID and devive ID signature.\r |
8b13229b | 28 | ///\r |
959ccb23 | 29 | #define PXE_BUSTYPE_PXE PXE_BUSTYPE ('!', 'P', 'X', 'E')\r |
30 | \r | |
8b13229b | 31 | ///\r |
af2dc6a7 | 32 | /// BUS ROM ID signatures.\r |
8b13229b | 33 | ///\r |
959ccb23 | 34 | #define PXE_BUSTYPE_PCI PXE_BUSTYPE ('P', 'C', 'I', 'R')\r |
35 | #define PXE_BUSTYPE_PC_CARD PXE_BUSTYPE ('P', 'C', 'C', 'R')\r | |
36 | #define PXE_BUSTYPE_USB PXE_BUSTYPE ('U', 'S', 'B', 'R')\r | |
37 | #define PXE_BUSTYPE_1394 PXE_BUSTYPE ('1', '3', '9', '4')\r | |
38 | \r | |
39 | #define PXE_SWAP_UINT16(n) ((((PXE_UINT16) (n) & 0x00FF) << 8) | (((PXE_UINT16) (n) & 0xFF00) >> 8))\r | |
40 | \r | |
41 | #define PXE_SWAP_UINT32(n) \\r | |
42 | ((((PXE_UINT32)(n) & 0x000000FF) << 24) | \\r | |
43 | (((PXE_UINT32)(n) & 0x0000FF00) << 8) | \\r | |
44 | (((PXE_UINT32)(n) & 0x00FF0000) >> 8) | \\r | |
45 | (((PXE_UINT32)(n) & 0xFF000000) >> 24))\r | |
46 | \r | |
47 | #define PXE_SWAP_UINT64(n) \\r | |
48 | ((((PXE_UINT64)(n) & 0x00000000000000FFULL) << 56) | \\r | |
49 | (((PXE_UINT64)(n) & 0x000000000000FF00ULL) << 40) | \\r | |
50 | (((PXE_UINT64)(n) & 0x0000000000FF0000ULL) << 24) | \\r | |
51 | (((PXE_UINT64)(n) & 0x00000000FF000000ULL) << 8) | \\r | |
52 | (((PXE_UINT64)(n) & 0x000000FF00000000ULL) >> 8) | \\r | |
53 | (((PXE_UINT64)(n) & 0x0000FF0000000000ULL) >> 24) | \\r | |
54 | (((PXE_UINT64)(n) & 0x00FF000000000000ULL) >> 40) | \\r | |
55 | (((PXE_UINT64)(n) & 0xFF00000000000000ULL) >> 56))\r | |
56 | \r | |
57 | \r | |
3ed785e9 | 58 | #define PXE_CPBSIZE_NOT_USED 0 ///< zero\r |
59 | #define PXE_DBSIZE_NOT_USED 0 ///< zero\r | |
60 | #define PXE_CPBADDR_NOT_USED (PXE_UINT64) 0 ///< zero\r | |
61 | #define PXE_DBADDR_NOT_USED (PXE_UINT64) 0 ///< zero\r | |
62 | #define PXE_CONST CONST\r | |
959ccb23 | 63 | \r |
64 | #define PXE_VOLATILE volatile\r | |
65 | \r | |
66 | typedef VOID PXE_VOID;\r | |
67 | typedef UINT8 PXE_UINT8;\r | |
68 | typedef UINT16 PXE_UINT16;\r | |
69 | typedef UINT32 PXE_UINT32;\r | |
70 | typedef UINTN PXE_UINTN;\r | |
4ccd9566 | 71 | \r |
8b13229b | 72 | ///\r |
af2dc6a7 | 73 | /// Typedef unsigned long PXE_UINT64.\r |
8b13229b | 74 | ///\r |
959ccb23 | 75 | typedef UINT64 PXE_UINT64;\r |
76 | \r | |
77 | typedef PXE_UINT8 PXE_BOOL;\r | |
3ed785e9 | 78 | #define PXE_FALSE 0 ///< zero\r |
959ccb23 | 79 | #define PXE_TRUE (!PXE_FALSE)\r |
80 | \r | |
81 | typedef PXE_UINT16 PXE_OPCODE;\r | |
82 | \r | |
8b13229b | 83 | ///\r |
84 | /// Return UNDI operational state.\r | |
85 | ///\r | |
959ccb23 | 86 | #define PXE_OPCODE_GET_STATE 0x0000\r |
87 | \r | |
8b13229b | 88 | ///\r |
89 | /// Change UNDI operational state from Stopped to Started.\r | |
90 | ///\r | |
959ccb23 | 91 | #define PXE_OPCODE_START 0x0001\r |
92 | \r | |
8b13229b | 93 | ///\r |
94 | /// Change UNDI operational state from Started to Stopped.\r | |
95 | ///\r | |
959ccb23 | 96 | #define PXE_OPCODE_STOP 0x0002\r |
97 | \r | |
8b13229b | 98 | ///\r |
99 | /// Get UNDI initialization information.\r | |
100 | ///\r | |
959ccb23 | 101 | #define PXE_OPCODE_GET_INIT_INFO 0x0003\r |
102 | \r | |
8b13229b | 103 | ///\r |
104 | /// Get NIC configuration information.\r | |
105 | ///\r | |
959ccb23 | 106 | #define PXE_OPCODE_GET_CONFIG_INFO 0x0004\r |
107 | \r | |
8b13229b | 108 | ///\r |
109 | /// Changed UNDI operational state from Started to Initialized.\r | |
110 | ///\r | |
959ccb23 | 111 | #define PXE_OPCODE_INITIALIZE 0x0005\r |
112 | \r | |
8b13229b | 113 | ///\r |
114 | /// Re-initialize the NIC H/W.\r | |
115 | ///\r | |
959ccb23 | 116 | #define PXE_OPCODE_RESET 0x0006\r |
117 | \r | |
8b13229b | 118 | ///\r |
119 | /// Change the UNDI operational state from Initialized to Started.\r | |
120 | ///\r | |
959ccb23 | 121 | #define PXE_OPCODE_SHUTDOWN 0x0007\r |
122 | \r | |
8b13229b | 123 | ///\r |
124 | /// Read & change state of external interrupt enables.\r | |
125 | ///\r | |
959ccb23 | 126 | #define PXE_OPCODE_INTERRUPT_ENABLES 0x0008\r |
127 | \r | |
8b13229b | 128 | ///\r |
129 | /// Read & change state of packet receive filters.\r | |
130 | ///\r | |
959ccb23 | 131 | #define PXE_OPCODE_RECEIVE_FILTERS 0x0009\r |
132 | \r | |
8b13229b | 133 | ///\r |
134 | /// Read & change station MAC address.\r | |
135 | ///\r | |
959ccb23 | 136 | #define PXE_OPCODE_STATION_ADDRESS 0x000A\r |
137 | \r | |
8b13229b | 138 | ///\r |
139 | /// Read traffic statistics.\r | |
140 | ///\r | |
959ccb23 | 141 | #define PXE_OPCODE_STATISTICS 0x000B\r |
142 | \r | |
8b13229b | 143 | ///\r |
144 | /// Convert multicast IP address to multicast MAC address.\r | |
145 | ///\r | |
959ccb23 | 146 | #define PXE_OPCODE_MCAST_IP_TO_MAC 0x000C\r |
147 | \r | |
8b13229b | 148 | ///\r |
149 | /// Read or change non-volatile storage on the NIC.\r | |
150 | ///\r | |
959ccb23 | 151 | #define PXE_OPCODE_NVDATA 0x000D\r |
152 | \r | |
8b13229b | 153 | ///\r |
154 | /// Get & clear interrupt status.\r | |
155 | ///\r | |
959ccb23 | 156 | #define PXE_OPCODE_GET_STATUS 0x000E\r |
157 | \r | |
8b13229b | 158 | ///\r |
159 | /// Fill media header in packet for transmit.\r | |
160 | ///\r | |
959ccb23 | 161 | #define PXE_OPCODE_FILL_HEADER 0x000F\r |
162 | \r | |
8b13229b | 163 | ///\r |
164 | /// Transmit packet(s).\r | |
165 | ///\r | |
959ccb23 | 166 | #define PXE_OPCODE_TRANSMIT 0x0010\r |
167 | \r | |
8b13229b | 168 | ///\r |
169 | /// Receive packet.\r | |
170 | ///\r | |
959ccb23 | 171 | #define PXE_OPCODE_RECEIVE 0x0011\r |
172 | \r | |
8b13229b | 173 | ///\r |
174 | /// Last valid PXE UNDI OpCode number.\r | |
175 | ///\r | |
959ccb23 | 176 | #define PXE_OPCODE_LAST_VALID 0x0011\r |
177 | \r | |
178 | typedef PXE_UINT16 PXE_OPFLAGS;\r | |
179 | \r | |
180 | #define PXE_OPFLAGS_NOT_USED 0x0000\r | |
181 | \r | |
182 | //\r | |
183 | // //////////////////////////////////////\r | |
184 | // UNDI Get State\r | |
185 | //\r | |
186 | // No OpFlags\r | |
187 | \r | |
188 | ////////////////////////////////////////\r | |
189 | // UNDI Start\r | |
190 | //\r | |
191 | // No OpFlags\r | |
192 | \r | |
193 | ////////////////////////////////////////\r | |
194 | // UNDI Stop\r | |
195 | //\r | |
196 | // No OpFlags\r | |
197 | \r | |
198 | ////////////////////////////////////////\r | |
199 | // UNDI Get Init Info\r | |
200 | //\r | |
201 | // No Opflags\r | |
202 | \r | |
203 | ////////////////////////////////////////\r | |
204 | // UNDI Get Config Info\r | |
205 | //\r | |
206 | // No Opflags\r | |
207 | \r | |
3ed785e9 | 208 | ///\r |
209 | /// UNDI Initialize\r | |
210 | ///\r | |
959ccb23 | 211 | #define PXE_OPFLAGS_INITIALIZE_CABLE_DETECT_MASK 0x0001\r |
212 | #define PXE_OPFLAGS_INITIALIZE_DETECT_CABLE 0x0000\r | |
213 | #define PXE_OPFLAGS_INITIALIZE_DO_NOT_DETECT_CABLE 0x0001\r | |
214 | \r | |
3ed785e9 | 215 | ///\r |
216 | ///\r | |
217 | /// UNDI Reset\r | |
218 | ///\r | |
959ccb23 | 219 | #define PXE_OPFLAGS_RESET_DISABLE_INTERRUPTS 0x0001\r |
220 | #define PXE_OPFLAGS_RESET_DISABLE_FILTERS 0x0002\r | |
221 | \r | |
3ed785e9 | 222 | ///\r |
af2dc6a7 | 223 | /// UNDI Shutdown.\r |
3ed785e9 | 224 | ///\r |
af2dc6a7 | 225 | /// No OpFlags.\r |
959ccb23 | 226 | \r |
3ed785e9 | 227 | ///\r |
af2dc6a7 | 228 | /// UNDI Interrupt Enables.\r |
3ed785e9 | 229 | ///\r |
230 | ///\r | |
231 | /// Select whether to enable or disable external interrupt signals.\r | |
232 | /// Setting both enable and disable will return PXE_STATCODE_INVALID_OPFLAGS.\r | |
233 | ///\r | |
959ccb23 | 234 | #define PXE_OPFLAGS_INTERRUPT_OPMASK 0xC000\r |
235 | #define PXE_OPFLAGS_INTERRUPT_ENABLE 0x8000\r | |
236 | #define PXE_OPFLAGS_INTERRUPT_DISABLE 0x4000\r | |
237 | #define PXE_OPFLAGS_INTERRUPT_READ 0x0000\r | |
238 | \r | |
8b13229b | 239 | ///\r |
240 | /// Enable receive interrupts. An external interrupt will be generated\r | |
241 | /// after a complete non-error packet has been received.\r | |
242 | ///\r | |
959ccb23 | 243 | #define PXE_OPFLAGS_INTERRUPT_RECEIVE 0x0001\r |
244 | \r | |
8b13229b | 245 | ///\r |
246 | /// Enable transmit interrupts. An external interrupt will be generated\r | |
247 | /// after a complete non-error packet has been transmitted.\r | |
248 | ///\r | |
959ccb23 | 249 | #define PXE_OPFLAGS_INTERRUPT_TRANSMIT 0x0002\r |
250 | \r | |
8b13229b | 251 | ///\r |
252 | /// Enable command interrupts. An external interrupt will be generated\r | |
253 | /// when command execution stops.\r | |
254 | ///\r | |
959ccb23 | 255 | #define PXE_OPFLAGS_INTERRUPT_COMMAND 0x0004\r |
256 | \r | |
8b13229b | 257 | ///\r |
258 | /// Generate software interrupt. Setting this bit generates an external\r | |
259 | /// interrupt, if it is supported by the hardware.\r | |
260 | ///\r | |
959ccb23 | 261 | #define PXE_OPFLAGS_INTERRUPT_SOFTWARE 0x0008\r |
262 | \r | |
4ccd9566 | 263 | ///\r |
af2dc6a7 | 264 | /// UNDI Receive Filters.\r |
3ed785e9 | 265 | ///\r |
266 | ///\r | |
267 | /// Select whether to enable or disable receive filters.\r | |
268 | /// Setting both enable and disable will return PXE_STATCODE_INVALID_OPCODE.\r | |
269 | ///\r | |
959ccb23 | 270 | #define PXE_OPFLAGS_RECEIVE_FILTER_OPMASK 0xC000\r |
271 | #define PXE_OPFLAGS_RECEIVE_FILTER_ENABLE 0x8000\r | |
272 | #define PXE_OPFLAGS_RECEIVE_FILTER_DISABLE 0x4000\r | |
273 | #define PXE_OPFLAGS_RECEIVE_FILTER_READ 0x0000\r | |
274 | \r | |
8b13229b | 275 | ///\r |
276 | /// To reset the contents of the multicast MAC address filter list,\r | |
277 | /// set this OpFlag:\r | |
278 | ///\r | |
959ccb23 | 279 | #define PXE_OPFLAGS_RECEIVE_FILTER_RESET_MCAST_LIST 0x2000\r |
280 | \r | |
8b13229b | 281 | ///\r |
282 | /// Enable unicast packet receiving. Packets sent to the current station\r | |
283 | /// MAC address will be received.\r | |
284 | ///\r | |
959ccb23 | 285 | #define PXE_OPFLAGS_RECEIVE_FILTER_UNICAST 0x0001\r |
286 | \r | |
8b13229b | 287 | ///\r |
288 | /// Enable broadcast packet receiving. Packets sent to the broadcast\r | |
289 | /// MAC address will be received.\r | |
290 | ///\r | |
959ccb23 | 291 | #define PXE_OPFLAGS_RECEIVE_FILTER_BROADCAST 0x0002\r |
292 | \r | |
8b13229b | 293 | ///\r |
294 | /// Enable filtered multicast packet receiving. Packets sent to any\r | |
295 | /// of the multicast MAC addresses in the multicast MAC address filter\r | |
296 | /// list will be received. If the filter list is empty, no multicast\r | |
297 | ///\r | |
959ccb23 | 298 | #define PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004\r |
299 | \r | |
8b13229b | 300 | ///\r |
301 | /// Enable promiscuous packet receiving. All packets will be received.\r | |
302 | ///\r | |
959ccb23 | 303 | #define PXE_OPFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008\r |
304 | \r | |
8b13229b | 305 | ///\r |
306 | /// Enable promiscuous multicast packet receiving. All multicast\r | |
307 | /// packets will be received.\r | |
308 | ///\r | |
959ccb23 | 309 | #define PXE_OPFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010\r |
310 | \r | |
4ccd9566 | 311 | ///\r |
af2dc6a7 | 312 | /// UNDI Station Address.\r |
3ed785e9 | 313 | ///\r |
959ccb23 | 314 | #define PXE_OPFLAGS_STATION_ADDRESS_READ 0x0000\r |
315 | #define PXE_OPFLAGS_STATION_ADDRESS_WRITE 0x0000\r | |
316 | #define PXE_OPFLAGS_STATION_ADDRESS_RESET 0x0001\r | |
317 | \r | |
3ed785e9 | 318 | ///\r |
af2dc6a7 | 319 | /// UNDI Statistics.\r |
3ed785e9 | 320 | ///\r |
959ccb23 | 321 | #define PXE_OPFLAGS_STATISTICS_READ 0x0000\r |
322 | #define PXE_OPFLAGS_STATISTICS_RESET 0x0001\r | |
323 | \r | |
3ed785e9 | 324 | ///\r |
af2dc6a7 | 325 | /// UNDI MCast IP to MAC.\r |
3ed785e9 | 326 | ///\r |
327 | ///\r | |
328 | /// Identify the type of IP address in the CPB.\r | |
329 | ///\r | |
959ccb23 | 330 | #define PXE_OPFLAGS_MCAST_IP_TO_MAC_OPMASK 0x0003\r |
331 | #define PXE_OPFLAGS_MCAST_IPV4_TO_MAC 0x0000\r | |
332 | #define PXE_OPFLAGS_MCAST_IPV6_TO_MAC 0x0001\r | |
333 | \r | |
3ed785e9 | 334 | ///\r |
af2dc6a7 | 335 | /// UNDI NvData.\r |
3ed785e9 | 336 | ///\r |
337 | ///\r | |
338 | /// Select the type of non-volatile data operation.\r | |
339 | ///\r | |
959ccb23 | 340 | #define PXE_OPFLAGS_NVDATA_OPMASK 0x0001\r |
341 | #define PXE_OPFLAGS_NVDATA_READ 0x0000\r | |
342 | #define PXE_OPFLAGS_NVDATA_WRITE 0x0001\r | |
343 | \r | |
3ed785e9 | 344 | ///\r |
af2dc6a7 | 345 | /// UNDI Get Status.\r |
3ed785e9 | 346 | ///\r |
347 | ///\r | |
348 | /// Return current interrupt status. This will also clear any interrupts\r | |
349 | /// that are currently set. This can be used in a polling routine. The\r | |
350 | /// interrupt flags are still set and cleared even when the interrupts\r | |
351 | /// are disabled.\r | |
352 | ///\r | |
959ccb23 | 353 | #define PXE_OPFLAGS_GET_INTERRUPT_STATUS 0x0001\r |
354 | \r | |
3ed785e9 | 355 | ///\r |
356 | /// Return list of transmitted buffers for recycling. Transmit buffers\r | |
357 | /// must not be changed or unallocated until they have recycled. After\r | |
358 | /// issuing a transmit command, wait for a transmit complete interrupt.\r | |
359 | /// When a transmit complete interrupt is received, read the transmitted\r | |
360 | /// buffers. Do not plan on getting one buffer per interrupt. Some\r | |
361 | /// NICs and UNDIs may transmit multiple buffers per interrupt.\r | |
362 | ///\r | |
959ccb23 | 363 | #define PXE_OPFLAGS_GET_TRANSMITTED_BUFFERS 0x0002\r |
364 | \r | |
993702aa | 365 | ///\r |
366 | /// Return current media status.\r | |
367 | ///\r | |
368 | #define PXE_OPFLAGS_GET_MEDIA_STATUS 0x0004\r | |
369 | \r | |
3ed785e9 | 370 | ///\r |
af2dc6a7 | 371 | /// UNDI Fill Header.\r |
3ed785e9 | 372 | ///\r |
959ccb23 | 373 | #define PXE_OPFLAGS_FILL_HEADER_OPMASK 0x0001\r |
374 | #define PXE_OPFLAGS_FILL_HEADER_FRAGMENTED 0x0001\r | |
375 | #define PXE_OPFLAGS_FILL_HEADER_WHOLE 0x0000\r | |
376 | \r | |
3ed785e9 | 377 | ///\r |
af2dc6a7 | 378 | /// UNDI Transmit.\r |
3ed785e9 | 379 | ///\r |
380 | ///\r | |
381 | /// S/W UNDI only. Return after the packet has been transmitted. A\r | |
382 | /// transmit complete interrupt will still be generated and the transmit\r | |
383 | /// buffer will have to be recycled.\r | |
384 | ///\r | |
959ccb23 | 385 | #define PXE_OPFLAGS_SWUNDI_TRANSMIT_OPMASK 0x0001\r |
386 | #define PXE_OPFLAGS_TRANSMIT_BLOCK 0x0001\r | |
387 | #define PXE_OPFLAGS_TRANSMIT_DONT_BLOCK 0x0000\r | |
388 | \r | |
959ccb23 | 389 | #define PXE_OPFLAGS_TRANSMIT_OPMASK 0x0002\r |
390 | #define PXE_OPFLAGS_TRANSMIT_FRAGMENTED 0x0002\r | |
391 | #define PXE_OPFLAGS_TRANSMIT_WHOLE 0x0000\r | |
392 | \r | |
4ccd9566 | 393 | ///\r |
af2dc6a7 | 394 | /// UNDI Receive.\r |
3ed785e9 | 395 | ///\r |
af2dc6a7 | 396 | /// No OpFlags.\r |
3ed785e9 | 397 | ///\r |
398 | \r | |
399 | ///\r | |
af2dc6a7 | 400 | /// PXE STATFLAGS.\r |
3ed785e9 | 401 | ///\r |
959ccb23 | 402 | typedef PXE_UINT16 PXE_STATFLAGS;\r |
403 | \r | |
404 | #define PXE_STATFLAGS_INITIALIZE 0x0000\r | |
405 | \r | |
3ed785e9 | 406 | ///\r |
407 | /// Common StatFlags that can be returned by all commands.\r | |
408 | ///\r | |
409 | ///\r | |
410 | /// The COMMAND_COMPLETE and COMMAND_FAILED status flags must be\r | |
411 | /// implemented by all UNDIs. COMMAND_QUEUED is only needed by UNDIs\r | |
412 | /// that support command queuing.\r | |
413 | ///\r | |
959ccb23 | 414 | #define PXE_STATFLAGS_STATUS_MASK 0xC000\r |
415 | #define PXE_STATFLAGS_COMMAND_COMPLETE 0xC000\r | |
416 | #define PXE_STATFLAGS_COMMAND_FAILED 0x8000\r | |
417 | #define PXE_STATFLAGS_COMMAND_QUEUED 0x4000\r | |
418 | \r | |
3ed785e9 | 419 | ///\r |
af2dc6a7 | 420 | /// UNDI Get State.\r |
3ed785e9 | 421 | ///\r |
959ccb23 | 422 | #define PXE_STATFLAGS_GET_STATE_MASK 0x0003\r |
423 | #define PXE_STATFLAGS_GET_STATE_INITIALIZED 0x0002\r | |
424 | #define PXE_STATFLAGS_GET_STATE_STARTED 0x0001\r | |
425 | #define PXE_STATFLAGS_GET_STATE_STOPPED 0x0000\r | |
426 | \r | |
3ed785e9 | 427 | ///\r |
af2dc6a7 | 428 | /// UNDI Start.\r |
3ed785e9 | 429 | ///\r |
af2dc6a7 | 430 | /// No additional StatFlags.\r |
3ed785e9 | 431 | ///\r |
959ccb23 | 432 | \r |
3ed785e9 | 433 | ///\r |
af2dc6a7 | 434 | /// UNDI Get Init Info.\r |
3ed785e9 | 435 | ///\r |
959ccb23 | 436 | #define PXE_STATFLAGS_CABLE_DETECT_MASK 0x0001\r |
437 | #define PXE_STATFLAGS_CABLE_DETECT_NOT_SUPPORTED 0x0000\r | |
438 | #define PXE_STATFLAGS_CABLE_DETECT_SUPPORTED 0x0001\r | |
439 | \r | |
993702aa | 440 | #define PXE_STATFLAGS_GET_STATUS_NO_MEDIA_MASK 0x0002\r |
441 | #define PXE_STATFLAGS_GET_STATUS_NO_MEDIA_NOT_SUPPORTED 0x0000\r | |
442 | #define PXE_STATFLAGS_GET_STATUS_NO_MEDIA_SUPPORTED 0x0002\r | |
443 | \r | |
3ed785e9 | 444 | ///\r |
af2dc6a7 | 445 | /// UNDI Initialize.\r |
3ed785e9 | 446 | ///\r |
959ccb23 | 447 | #define PXE_STATFLAGS_INITIALIZED_NO_MEDIA 0x0001\r |
448 | \r | |
3ed785e9 | 449 | ///\r |
af2dc6a7 | 450 | /// UNDI Reset.\r |
3ed785e9 | 451 | ///\r |
959ccb23 | 452 | #define PXE_STATFLAGS_RESET_NO_MEDIA 0x0001\r |
453 | \r | |
3ed785e9 | 454 | ///\r |
af2dc6a7 | 455 | /// UNDI Shutdown.\r |
3ed785e9 | 456 | ///\r |
af2dc6a7 | 457 | /// No additional StatFlags.\r |
959ccb23 | 458 | \r |
3ed785e9 | 459 | ///\r |
af2dc6a7 | 460 | /// UNDI Interrupt Enables.\r |
3ed785e9 | 461 | ///\r |
462 | ///\r | |
463 | /// If set, receive interrupts are enabled.\r | |
464 | ///\r | |
959ccb23 | 465 | #define PXE_STATFLAGS_INTERRUPT_RECEIVE 0x0001\r |
466 | \r | |
3ed785e9 | 467 | ///\r |
468 | /// If set, transmit interrupts are enabled.\r | |
469 | ///\r | |
959ccb23 | 470 | #define PXE_STATFLAGS_INTERRUPT_TRANSMIT 0x0002\r |
471 | \r | |
3ed785e9 | 472 | ///\r |
473 | /// If set, command interrupts are enabled.\r | |
474 | ///\r | |
959ccb23 | 475 | #define PXE_STATFLAGS_INTERRUPT_COMMAND 0x0004\r |
476 | \r | |
3ed785e9 | 477 | ///\r |
af2dc6a7 | 478 | /// UNDI Receive Filters.\r |
3ed785e9 | 479 | ///\r |
480 | \r | |
481 | ///\r | |
482 | /// If set, unicast packets will be received.\r | |
483 | ///\r | |
959ccb23 | 484 | #define PXE_STATFLAGS_RECEIVE_FILTER_UNICAST 0x0001\r |
485 | \r | |
3ed785e9 | 486 | ///\r |
487 | /// If set, broadcast packets will be received.\r | |
488 | ///\r | |
959ccb23 | 489 | #define PXE_STATFLAGS_RECEIVE_FILTER_BROADCAST 0x0002\r |
490 | \r | |
3ed785e9 | 491 | ///\r |
492 | /// If set, multicast packets that match up with the multicast address\r | |
493 | /// filter list will be received.\r | |
494 | ///\r | |
959ccb23 | 495 | #define PXE_STATFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004\r |
496 | \r | |
3ed785e9 | 497 | ///\r |
498 | /// If set, all packets will be received.\r | |
499 | ///\r | |
959ccb23 | 500 | #define PXE_STATFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008\r |
501 | \r | |
3ed785e9 | 502 | ///\r |
503 | /// If set, all multicast packets will be received.\r | |
504 | ///\r | |
959ccb23 | 505 | #define PXE_STATFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010\r |
506 | \r | |
3ed785e9 | 507 | ///\r |
af2dc6a7 | 508 | /// UNDI Station Address.\r |
3ed785e9 | 509 | ///\r |
af2dc6a7 | 510 | /// No additional StatFlags.\r |
3ed785e9 | 511 | ///\r |
959ccb23 | 512 | \r |
3ed785e9 | 513 | ///\r |
af2dc6a7 | 514 | /// UNDI Statistics.\r |
3ed785e9 | 515 | ///\r |
af2dc6a7 | 516 | /// No additional StatFlags.\r |
3ed785e9 | 517 | ///\r |
959ccb23 | 518 | \r |
3ed785e9 | 519 | ///\r |
af2dc6a7 | 520 | //// UNDI MCast IP to MAC.\r |
3ed785e9 | 521 | ////\r |
af2dc6a7 | 522 | //// No additional StatFlags.\r |
959ccb23 | 523 | \r |
3ed785e9 | 524 | ///\r |
af2dc6a7 | 525 | /// UNDI NvData.\r |
3ed785e9 | 526 | ///\r |
af2dc6a7 | 527 | /// No additional StatFlags.\r |
3ed785e9 | 528 | ///\r |
959ccb23 | 529 | \r |
3ed785e9 | 530 | ///\r |
af2dc6a7 | 531 | /// UNDI Get Status.\r |
3ed785e9 | 532 | ///\r |
959ccb23 | 533 | \r |
3ed785e9 | 534 | ///\r |
535 | /// Use to determine if an interrupt has occurred.\r | |
536 | ///\r | |
959ccb23 | 537 | #define PXE_STATFLAGS_GET_STATUS_INTERRUPT_MASK 0x000F\r |
538 | #define PXE_STATFLAGS_GET_STATUS_NO_INTERRUPTS 0x0000\r | |
539 | \r | |
3ed785e9 | 540 | ///\r |
541 | /// If set, at least one receive interrupt occurred.\r | |
542 | ///\r | |
959ccb23 | 543 | #define PXE_STATFLAGS_GET_STATUS_RECEIVE 0x0001\r |
544 | \r | |
3ed785e9 | 545 | ///\r |
546 | /// If set, at least one transmit interrupt occurred.\r | |
547 | ///\r | |
959ccb23 | 548 | #define PXE_STATFLAGS_GET_STATUS_TRANSMIT 0x0002\r |
549 | \r | |
3ed785e9 | 550 | ///\r |
551 | /// If set, at least one command interrupt occurred.\r | |
552 | ///\r | |
959ccb23 | 553 | #define PXE_STATFLAGS_GET_STATUS_COMMAND 0x0004\r |
554 | \r | |
3ed785e9 | 555 | ///\r |
556 | /// If set, at least one software interrupt occurred.\r | |
557 | ///\r | |
959ccb23 | 558 | #define PXE_STATFLAGS_GET_STATUS_SOFTWARE 0x0008\r |
559 | \r | |
3ed785e9 | 560 | ///\r |
561 | /// This flag is set if the transmitted buffer queue is empty. This flag\r | |
562 | /// will be set if all transmitted buffer addresses get written into the DB.\r | |
563 | ///\r | |
959ccb23 | 564 | #define PXE_STATFLAGS_GET_STATUS_TXBUF_QUEUE_EMPTY 0x0010\r |
565 | \r | |
3ed785e9 | 566 | ///\r |
567 | /// This flag is set if no transmitted buffer addresses were written\r | |
568 | /// into the DB. (This could be because DBsize was too small.)\r | |
569 | ///\r | |
959ccb23 | 570 | #define PXE_STATFLAGS_GET_STATUS_NO_TXBUFS_WRITTEN 0x0020\r |
571 | \r | |
993702aa | 572 | ///\r |
573 | /// This flag is set if there is no media detected.\r | |
574 | ///\r | |
575 | #define PXE_STATFLAGS_GET_STATUS_NO_MEDIA 0x0040\r | |
576 | \r | |
3ed785e9 | 577 | ///\r |
af2dc6a7 | 578 | /// UNDI Fill Header.\r |
3ed785e9 | 579 | ///\r |
af2dc6a7 | 580 | /// No additional StatFlags.\r |
3ed785e9 | 581 | ///\r |
959ccb23 | 582 | \r |
3ed785e9 | 583 | ///\r |
af2dc6a7 | 584 | /// UNDI Transmit.\r |
3ed785e9 | 585 | ///\r |
586 | /// No additional StatFlags.\r | |
959ccb23 | 587 | \r |
3ed785e9 | 588 | ///\r |
589 | /// UNDI Receive\r | |
af2dc6a7 | 590 | ///.\r |
3ed785e9 | 591 | \r |
592 | ///\r | |
593 | /// No additional StatFlags.\r | |
594 | ///\r | |
959ccb23 | 595 | typedef PXE_UINT16 PXE_STATCODE;\r |
596 | \r | |
597 | #define PXE_STATCODE_INITIALIZE 0x0000\r | |
598 | \r | |
3ed785e9 | 599 | ///\r |
600 | /// Common StatCodes returned by all UNDI commands, UNDI protocol functions\r | |
601 | /// and BC protocol functions.\r | |
602 | ///\r | |
959ccb23 | 603 | #define PXE_STATCODE_SUCCESS 0x0000\r |
604 | \r | |
605 | #define PXE_STATCODE_INVALID_CDB 0x0001\r | |
606 | #define PXE_STATCODE_INVALID_CPB 0x0002\r | |
607 | #define PXE_STATCODE_BUSY 0x0003\r | |
608 | #define PXE_STATCODE_QUEUE_FULL 0x0004\r | |
609 | #define PXE_STATCODE_ALREADY_STARTED 0x0005\r | |
610 | #define PXE_STATCODE_NOT_STARTED 0x0006\r | |
611 | #define PXE_STATCODE_NOT_SHUTDOWN 0x0007\r | |
612 | #define PXE_STATCODE_ALREADY_INITIALIZED 0x0008\r | |
613 | #define PXE_STATCODE_NOT_INITIALIZED 0x0009\r | |
614 | #define PXE_STATCODE_DEVICE_FAILURE 0x000A\r | |
615 | #define PXE_STATCODE_NVDATA_FAILURE 0x000B\r | |
616 | #define PXE_STATCODE_UNSUPPORTED 0x000C\r | |
617 | #define PXE_STATCODE_BUFFER_FULL 0x000D\r | |
618 | #define PXE_STATCODE_INVALID_PARAMETER 0x000E\r | |
619 | #define PXE_STATCODE_INVALID_UNDI 0x000F\r | |
620 | #define PXE_STATCODE_IPV4_NOT_SUPPORTED 0x0010\r | |
621 | #define PXE_STATCODE_IPV6_NOT_SUPPORTED 0x0011\r | |
622 | #define PXE_STATCODE_NOT_ENOUGH_MEMORY 0x0012\r | |
623 | #define PXE_STATCODE_NO_DATA 0x0013\r | |
624 | \r | |
625 | typedef PXE_UINT16 PXE_IFNUM;\r | |
626 | \r | |
3ed785e9 | 627 | ///\r |
628 | /// This interface number must be passed to the S/W UNDI Start command.\r | |
629 | ///\r | |
959ccb23 | 630 | #define PXE_IFNUM_START 0x0000\r |
631 | \r | |
3ed785e9 | 632 | ///\r |
633 | /// This interface number is returned by the S/W UNDI Get State and\r | |
634 | /// Start commands if information in the CDB, CPB or DB is invalid.\r | |
635 | ///\r | |
959ccb23 | 636 | #define PXE_IFNUM_INVALID 0x0000\r |
637 | \r | |
638 | typedef PXE_UINT16 PXE_CONTROL;\r | |
639 | \r | |
3ed785e9 | 640 | ///\r |
641 | /// Setting this flag directs the UNDI to queue this command for later\r | |
642 | /// execution if the UNDI is busy and it supports command queuing.\r | |
643 | /// If queuing is not supported, a PXE_STATCODE_INVALID_CONTROL error\r | |
644 | /// is returned. If the queue is full, a PXE_STATCODE_CDB_QUEUE_FULL\r | |
645 | /// error is returned.\r | |
646 | ///\r | |
959ccb23 | 647 | #define PXE_CONTROL_QUEUE_IF_BUSY 0x0002\r |
648 | \r | |
3ed785e9 | 649 | ///\r |
650 | /// These two bit values are used to determine if there are more UNDI\r | |
651 | /// CDB structures following this one. If the link bit is set, there\r | |
652 | /// must be a CDB structure following this one. Execution will start\r | |
653 | /// on the next CDB structure as soon as this one completes successfully.\r | |
654 | /// If an error is generated by this command, execution will stop.\r | |
655 | ///\r | |
959ccb23 | 656 | #define PXE_CONTROL_LINK 0x0001\r |
657 | #define PXE_CONTROL_LAST_CDB_IN_LIST 0x0000\r | |
658 | \r | |
659 | typedef PXE_UINT8 PXE_FRAME_TYPE;\r | |
660 | \r | |
661 | #define PXE_FRAME_TYPE_NONE 0x00\r | |
662 | #define PXE_FRAME_TYPE_UNICAST 0x01\r | |
663 | #define PXE_FRAME_TYPE_BROADCAST 0x02\r | |
664 | #define PXE_FRAME_TYPE_FILTERED_MULTICAST 0x03\r | |
665 | #define PXE_FRAME_TYPE_PROMISCUOUS 0x04\r | |
666 | #define PXE_FRAME_TYPE_PROMISCUOUS_MULTICAST 0x05\r | |
667 | \r | |
4ccd9566 | 668 | #define PXE_FRAME_TYPE_MULTICAST PXE_FRAME_TYPE_FILTERED_MULTICAST\r |
959ccb23 | 669 | \r |
670 | typedef PXE_UINT32 PXE_IPV4;\r | |
671 | \r | |
672 | typedef PXE_UINT32 PXE_IPV6[4];\r | |
673 | #define PXE_MAC_LENGTH 32\r | |
674 | \r | |
675 | typedef PXE_UINT8 PXE_MAC_ADDR[PXE_MAC_LENGTH];\r | |
676 | \r | |
677 | typedef PXE_UINT8 PXE_IFTYPE;\r | |
678 | typedef UINT16 PXE_MEDIA_PROTOCOL;\r | |
679 | \r | |
3ed785e9 | 680 | ///\r |
681 | /// This information is from the ARP section of RFC 1700.\r | |
682 | ///\r | |
683 | /// 1 Ethernet (10Mb) [JBP]\r | |
684 | /// 2 Experimental Ethernet (3Mb) [JBP]\r | |
685 | /// 3 Amateur Radio AX.25 [PXK]\r | |
686 | /// 4 Proteon ProNET Token Ring [JBP]\r | |
687 | /// 5 Chaos [GXP]\r | |
688 | /// 6 IEEE 802 Networks [JBP]\r | |
689 | /// 7 ARCNET [JBP]\r | |
690 | /// 8 Hyperchannel [JBP]\r | |
691 | /// 9 Lanstar [TU]\r | |
692 | /// 10 Autonet Short Address [MXB1]\r | |
693 | /// 11 LocalTalk [JKR1]\r | |
694 | /// 12 LocalNet (IBM* PCNet or SYTEK* LocalNET) [JXM]\r | |
695 | /// 13 Ultra link [RXD2]\r | |
696 | /// 14 SMDS [GXC1]\r | |
697 | /// 15 Frame Relay [AGM]\r | |
698 | /// 16 Asynchronous Transmission Mode (ATM) [JXB2]\r | |
699 | /// 17 HDLC [JBP]\r | |
700 | /// 18 Fibre Channel [Yakov Rekhter]\r | |
701 | /// 19 Asynchronous Transmission Mode (ATM) [Mark Laubach]\r | |
702 | /// 20 Serial Line [JBP]\r | |
703 | /// 21 Asynchronous Transmission Mode (ATM) [MXB1]\r | |
704 | ///\r | |
705 | /// * Other names and brands may be claimed as the property of others.\r | |
706 | ///\r | |
959ccb23 | 707 | #define PXE_IFTYPE_ETHERNET 0x01\r |
708 | #define PXE_IFTYPE_TOKENRING 0x04\r | |
709 | #define PXE_IFTYPE_FIBRE_CHANNEL 0x12\r | |
710 | \r | |
711 | typedef struct s_pxe_hw_undi {\r | |
af2dc6a7 | 712 | PXE_UINT32 Signature; ///< PXE_ROMID_SIGNATURE.\r |
713 | PXE_UINT8 Len; ///< sizeof(PXE_HW_UNDI).\r | |
714 | PXE_UINT8 Fudge; ///< makes 8-bit cksum equal zero.\r | |
715 | PXE_UINT8 Rev; ///< PXE_ROMID_REV.\r | |
61f2ab90 | 716 | PXE_UINT8 IFcnt; ///< physical connector count lower byte.\r |
af2dc6a7 | 717 | PXE_UINT8 MajorVer; ///< PXE_ROMID_MAJORVER.\r |
718 | PXE_UINT8 MinorVer; ///< PXE_ROMID_MINORVER.\r | |
61f2ab90 QO |
719 | PXE_UINT8 IFcntExt; ///< physical connector count upper byte.\r |
720 | PXE_UINT8 reserved; ///< zero, not used.\r | |
af2dc6a7 | 721 | PXE_UINT32 Implementation; ///< implementation flags.\r |
722 | ///< reserved ///< vendor use.\r | |
723 | ///< UINT32 Status; ///< status port.\r | |
724 | ///< UINT32 Command; ///< command port.\r | |
725 | ///< UINT64 CDBaddr; ///< CDB address port.\r | |
3ed785e9 | 726 | ///<\r |
959ccb23 | 727 | } PXE_HW_UNDI;\r |
728 | \r | |
3ed785e9 | 729 | ///\r |
af2dc6a7 | 730 | /// Status port bit definitions.\r |
3ed785e9 | 731 | ///\r |
732 | \r | |
733 | ///\r | |
af2dc6a7 | 734 | /// UNDI operation state.\r |
3ed785e9 | 735 | ///\r |
959ccb23 | 736 | #define PXE_HWSTAT_STATE_MASK 0xC0000000\r |
737 | #define PXE_HWSTAT_BUSY 0xC0000000\r | |
738 | #define PXE_HWSTAT_INITIALIZED 0x80000000\r | |
739 | #define PXE_HWSTAT_STARTED 0x40000000\r | |
740 | #define PXE_HWSTAT_STOPPED 0x00000000\r | |
741 | \r | |
3ed785e9 | 742 | ///\r |
af2dc6a7 | 743 | /// If set, last command failed.\r |
3ed785e9 | 744 | ///\r |
959ccb23 | 745 | #define PXE_HWSTAT_COMMAND_FAILED 0x20000000\r |
746 | \r | |
3ed785e9 | 747 | ///\r |
af2dc6a7 | 748 | /// If set, identifies enabled receive filters.\r |
3ed785e9 | 749 | ///\r |
959ccb23 | 750 | #define PXE_HWSTAT_PROMISCUOUS_MULTICAST_RX_ENABLED 0x00001000\r |
751 | #define PXE_HWSTAT_PROMISCUOUS_RX_ENABLED 0x00000800\r | |
752 | #define PXE_HWSTAT_BROADCAST_RX_ENABLED 0x00000400\r | |
753 | #define PXE_HWSTAT_MULTICAST_RX_ENABLED 0x00000200\r | |
754 | #define PXE_HWSTAT_UNICAST_RX_ENABLED 0x00000100\r | |
755 | \r | |
3ed785e9 | 756 | ///\r |
af2dc6a7 | 757 | /// If set, identifies enabled external interrupts.\r |
3ed785e9 | 758 | ///\r |
959ccb23 | 759 | #define PXE_HWSTAT_SOFTWARE_INT_ENABLED 0x00000080\r |
760 | #define PXE_HWSTAT_TX_COMPLETE_INT_ENABLED 0x00000040\r | |
761 | #define PXE_HWSTAT_PACKET_RX_INT_ENABLED 0x00000020\r | |
762 | #define PXE_HWSTAT_CMD_COMPLETE_INT_ENABLED 0x00000010\r | |
763 | \r | |
3ed785e9 | 764 | ///\r |
af2dc6a7 | 765 | /// If set, identifies pending interrupts.\r |
3ed785e9 | 766 | ///\r |
959ccb23 | 767 | #define PXE_HWSTAT_SOFTWARE_INT_PENDING 0x00000008\r |
768 | #define PXE_HWSTAT_TX_COMPLETE_INT_PENDING 0x00000004\r | |
769 | #define PXE_HWSTAT_PACKET_RX_INT_PENDING 0x00000002\r | |
770 | #define PXE_HWSTAT_CMD_COMPLETE_INT_PENDING 0x00000001\r | |
771 | \r | |
3ed785e9 | 772 | ///\r |
af2dc6a7 | 773 | /// Command port definitions.\r |
3ed785e9 | 774 | ///\r |
775 | \r | |
776 | ///\r | |
777 | /// If set, CDB identified in CDBaddr port is given to UNDI.\r | |
778 | /// If not set, other bits in this word will be processed.\r | |
779 | ///\r | |
959ccb23 | 780 | #define PXE_HWCMD_ISSUE_COMMAND 0x80000000\r |
781 | #define PXE_HWCMD_INTS_AND_FILTS 0x00000000\r | |
782 | \r | |
3ed785e9 | 783 | ///\r |
784 | /// Use these to enable/disable receive filters.\r | |
785 | ///\r | |
959ccb23 | 786 | #define PXE_HWCMD_PROMISCUOUS_MULTICAST_RX_ENABLE 0x00001000\r |
787 | #define PXE_HWCMD_PROMISCUOUS_RX_ENABLE 0x00000800\r | |
788 | #define PXE_HWCMD_BROADCAST_RX_ENABLE 0x00000400\r | |
789 | #define PXE_HWCMD_MULTICAST_RX_ENABLE 0x00000200\r | |
790 | #define PXE_HWCMD_UNICAST_RX_ENABLE 0x00000100\r | |
791 | \r | |
3ed785e9 | 792 | ///\r |
af2dc6a7 | 793 | /// Use these to enable/disable external interrupts.\r |
3ed785e9 | 794 | ///\r |
959ccb23 | 795 | #define PXE_HWCMD_SOFTWARE_INT_ENABLE 0x00000080\r |
796 | #define PXE_HWCMD_TX_COMPLETE_INT_ENABLE 0x00000040\r | |
797 | #define PXE_HWCMD_PACKET_RX_INT_ENABLE 0x00000020\r | |
798 | #define PXE_HWCMD_CMD_COMPLETE_INT_ENABLE 0x00000010\r | |
799 | \r | |
3ed785e9 | 800 | ///\r |
af2dc6a7 | 801 | /// Use these to clear pending external interrupts.\r |
3ed785e9 | 802 | ///\r |
959ccb23 | 803 | #define PXE_HWCMD_CLEAR_SOFTWARE_INT 0x00000008\r |
804 | #define PXE_HWCMD_CLEAR_TX_COMPLETE_INT 0x00000004\r | |
805 | #define PXE_HWCMD_CLEAR_PACKET_RX_INT 0x00000002\r | |
806 | #define PXE_HWCMD_CLEAR_CMD_COMPLETE_INT 0x00000001\r | |
807 | \r | |
808 | typedef struct s_pxe_sw_undi {\r | |
af2dc6a7 | 809 | PXE_UINT32 Signature; ///< PXE_ROMID_SIGNATURE.\r |
810 | PXE_UINT8 Len; ///< sizeof(PXE_SW_UNDI).\r | |
811 | PXE_UINT8 Fudge; ///< makes 8-bit cksum zero.\r | |
812 | PXE_UINT8 Rev; ///< PXE_ROMID_REV.\r | |
61f2ab90 | 813 | PXE_UINT8 IFcnt; ///< physical connector count lower byte.\r |
af2dc6a7 | 814 | PXE_UINT8 MajorVer; ///< PXE_ROMID_MAJORVER.\r |
815 | PXE_UINT8 MinorVer; ///< PXE_ROMID_MINORVER.\r | |
61f2ab90 QO |
816 | PXE_UINT8 IFcntExt; ///< physical connector count upper byte.\r |
817 | PXE_UINT8 reserved1; ///< zero, not used.\r | |
af2dc6a7 | 818 | PXE_UINT32 Implementation; ///< Implementation flags.\r |
819 | PXE_UINT64 EntryPoint; ///< API entry point.\r | |
820 | PXE_UINT8 reserved2[3]; ///< zero, not used.\r | |
821 | PXE_UINT8 BusCnt; ///< number of bustypes supported.\r | |
822 | PXE_UINT32 BusType[1]; ///< list of supported bustypes.\r | |
959ccb23 | 823 | } PXE_SW_UNDI;\r |
824 | \r | |
825 | typedef union u_pxe_undi {\r | |
826 | PXE_HW_UNDI hw;\r | |
827 | PXE_SW_UNDI sw;\r | |
828 | } PXE_UNDI;\r | |
829 | \r | |
3ed785e9 | 830 | ///\r |
af2dc6a7 | 831 | /// Signature of !PXE structure.\r |
3ed785e9 | 832 | ///\r |
959ccb23 | 833 | #define PXE_ROMID_SIGNATURE PXE_BUSTYPE ('!', 'P', 'X', 'E')\r |
834 | \r | |
3ed785e9 | 835 | ///\r |
836 | /// !PXE structure format revision\r | |
af2dc6a7 | 837 | ///.\r |
959ccb23 | 838 | #define PXE_ROMID_REV 0x02\r |
839 | \r | |
3ed785e9 | 840 | ///\r |
841 | /// UNDI command interface revision. These are the values that get sent\r | |
842 | /// in option 94 (Client Network Interface Identifier) in the DHCP Discover\r | |
843 | /// and PXE Boot Server Request packets.\r | |
844 | ///\r | |
959ccb23 | 845 | #define PXE_ROMID_MAJORVER 0x03\r |
846 | #define PXE_ROMID_MINORVER 0x01\r | |
847 | \r | |
3ed785e9 | 848 | ///\r |
af2dc6a7 | 849 | /// Implementation flags.\r |
3ed785e9 | 850 | ///\r |
959ccb23 | 851 | #define PXE_ROMID_IMP_HW_UNDI 0x80000000\r |
852 | #define PXE_ROMID_IMP_SW_VIRT_ADDR 0x40000000\r | |
853 | #define PXE_ROMID_IMP_64BIT_DEVICE 0x00010000\r | |
854 | #define PXE_ROMID_IMP_FRAG_SUPPORTED 0x00008000\r | |
855 | #define PXE_ROMID_IMP_CMD_LINK_SUPPORTED 0x00004000\r | |
856 | #define PXE_ROMID_IMP_CMD_QUEUE_SUPPORTED 0x00002000\r | |
857 | #define PXE_ROMID_IMP_MULTI_FRAME_SUPPORTED 0x00001000\r | |
858 | #define PXE_ROMID_IMP_NVDATA_SUPPORT_MASK 0x00000C00\r | |
859 | #define PXE_ROMID_IMP_NVDATA_BULK_WRITABLE 0x00000C00\r | |
860 | #define PXE_ROMID_IMP_NVDATA_SPARSE_WRITABLE 0x00000800\r | |
861 | #define PXE_ROMID_IMP_NVDATA_READ_ONLY 0x00000400\r | |
862 | #define PXE_ROMID_IMP_NVDATA_NOT_AVAILABLE 0x00000000\r | |
863 | #define PXE_ROMID_IMP_STATISTICS_SUPPORTED 0x00000200\r | |
864 | #define PXE_ROMID_IMP_STATION_ADDR_SETTABLE 0x00000100\r | |
865 | #define PXE_ROMID_IMP_PROMISCUOUS_MULTICAST_RX_SUPPORTED 0x00000080\r | |
866 | #define PXE_ROMID_IMP_PROMISCUOUS_RX_SUPPORTED 0x00000040\r | |
867 | #define PXE_ROMID_IMP_BROADCAST_RX_SUPPORTED 0x00000020\r | |
868 | #define PXE_ROMID_IMP_FILTERED_MULTICAST_RX_SUPPORTED 0x00000010\r | |
869 | #define PXE_ROMID_IMP_SOFTWARE_INT_SUPPORTED 0x00000008\r | |
870 | #define PXE_ROMID_IMP_TX_COMPLETE_INT_SUPPORTED 0x00000004\r | |
871 | #define PXE_ROMID_IMP_PACKET_RX_INT_SUPPORTED 0x00000002\r | |
872 | #define PXE_ROMID_IMP_CMD_COMPLETE_INT_SUPPORTED 0x00000001\r | |
873 | \r | |
874 | typedef struct s_pxe_cdb {\r | |
875 | PXE_OPCODE OpCode;\r | |
876 | PXE_OPFLAGS OpFlags;\r | |
877 | PXE_UINT16 CPBsize;\r | |
878 | PXE_UINT16 DBsize;\r | |
879 | PXE_UINT64 CPBaddr;\r | |
880 | PXE_UINT64 DBaddr;\r | |
881 | PXE_STATCODE StatCode;\r | |
882 | PXE_STATFLAGS StatFlags;\r | |
883 | PXE_UINT16 IFnum;\r | |
884 | PXE_CONTROL Control;\r | |
885 | } PXE_CDB;\r | |
886 | \r | |
887 | typedef union u_pxe_ip_addr {\r | |
888 | PXE_IPV6 IPv6;\r | |
889 | PXE_IPV4 IPv4;\r | |
890 | } PXE_IP_ADDR;\r | |
891 | \r | |
892 | typedef union pxe_device {\r | |
3ed785e9 | 893 | ///\r |
894 | /// PCI and PC Card NICs are both identified using bus, device\r | |
895 | /// and function numbers. For PC Card, this may require PC\r | |
896 | /// Card services to be loaded in the BIOS or preboot\r | |
897 | /// environment.\r | |
898 | ///\r | |
959ccb23 | 899 | struct {\r |
3ed785e9 | 900 | ///\r |
901 | /// See S/W UNDI ROMID structure definition for PCI and\r | |
902 | /// PCC BusType definitions.\r | |
903 | ///\r | |
959ccb23 | 904 | PXE_UINT32 BusType;\r |
905 | \r | |
3ed785e9 | 906 | ///\r |
907 | /// Bus, device & function numbers that locate this device.\r | |
908 | ///\r | |
959ccb23 | 909 | PXE_UINT16 Bus;\r |
910 | PXE_UINT8 Device;\r | |
911 | PXE_UINT8 Function;\r | |
912 | }\r | |
913 | PCI, PCC;\r | |
914 | \r | |
959ccb23 | 915 | } PXE_DEVICE;\r |
916 | \r | |
3ed785e9 | 917 | ///\r |
918 | /// cpb and db definitions\r | |
919 | ///\r | |
af2dc6a7 | 920 | #define MAX_PCI_CONFIG_LEN 64 ///< # of dwords.\r |
921 | #define MAX_EEPROM_LEN 128 ///< # of dwords.\r | |
922 | #define MAX_XMIT_BUFFERS 32 ///< recycling Q length for xmit_done.\r | |
959ccb23 | 923 | #define MAX_MCAST_ADDRESS_CNT 8\r |
924 | \r | |
925 | typedef struct s_pxe_cpb_start_30 {\r | |
3ed785e9 | 926 | ///\r |
927 | /// PXE_VOID Delay(UINTN microseconds);\r | |
928 | ///\r | |
929 | /// UNDI will never request a delay smaller than 10 microseconds\r | |
930 | /// and will always request delays in increments of 10 microseconds.\r | |
931 | /// The Delay() CallBack routine must delay between n and n + 10\r | |
932 | /// microseconds before returning control to the UNDI.\r | |
933 | ///\r | |
934 | /// This field cannot be set to zero.\r | |
935 | ///\r | |
959ccb23 | 936 | UINT64 Delay;\r |
937 | \r | |
3ed785e9 | 938 | ///\r |
939 | /// PXE_VOID Block(UINT32 enable);\r | |
940 | ///\r | |
941 | /// UNDI may need to block multi-threaded/multi-processor access to\r | |
942 | /// critical code sections when programming or accessing the network\r | |
943 | /// device. To this end, a blocking service is needed by the UNDI.\r | |
944 | /// When UNDI needs a block, it will call Block() passing a non-zero\r | |
945 | /// value. When UNDI no longer needs a block, it will call Block()\r | |
946 | /// with a zero value. When called, if the Block() is already enabled,\r | |
947 | /// do not return control to the UNDI until the previous Block() is\r | |
948 | /// disabled.\r | |
949 | ///\r | |
950 | /// This field cannot be set to zero.\r | |
951 | ///\r | |
959ccb23 | 952 | UINT64 Block;\r |
953 | \r | |
3ed785e9 | 954 | ///\r |
955 | /// PXE_VOID Virt2Phys(UINT64 virtual, UINT64 physical_ptr);\r | |
956 | ///\r | |
957 | /// UNDI will pass the virtual address of a buffer and the virtual\r | |
958 | /// address of a 64-bit physical buffer. Convert the virtual address\r | |
959 | /// to a physical address and write the result to the physical address\r | |
960 | /// buffer. If virtual and physical addresses are the same, just\r | |
961 | /// copy the virtual address to the physical address buffer.\r | |
962 | ///\r | |
963 | /// This field can be set to zero if virtual and physical addresses\r | |
964 | /// are equal.\r | |
965 | ///\r | |
959ccb23 | 966 | UINT64 Virt2Phys;\r |
3ed785e9 | 967 | ///\r |
968 | /// PXE_VOID Mem_IO(UINT8 read_write, UINT8 len, UINT64 port,\r | |
969 | /// UINT64 buf_addr);\r | |
970 | ///\r | |
971 | /// UNDI will read or write the device io space using this call back\r | |
972 | /// function. It passes the number of bytes as the len parameter and it\r | |
973 | /// will be either 1,2,4 or 8.\r | |
974 | ///\r | |
975 | /// This field can not be set to zero.\r | |
976 | ///\r | |
959ccb23 | 977 | UINT64 Mem_IO;\r |
978 | } PXE_CPB_START_30;\r | |
979 | \r | |
980 | typedef struct s_pxe_cpb_start_31 {\r | |
3ed785e9 | 981 | ///\r |
982 | /// PXE_VOID Delay(UINT64 UnqId, UINTN microseconds);\r | |
983 | ///\r | |
984 | /// UNDI will never request a delay smaller than 10 microseconds\r | |
985 | /// and will always request delays in increments of 10 microseconds.\r | |
986 | /// The Delay() CallBack routine must delay between n and n + 10\r | |
987 | /// microseconds before returning control to the UNDI.\r | |
988 | ///\r | |
989 | /// This field cannot be set to zero.\r | |
990 | ///\r | |
959ccb23 | 991 | UINT64 Delay;\r |
992 | \r | |
3ed785e9 | 993 | ///\r |
994 | /// PXE_VOID Block(UINT64 unq_id, UINT32 enable);\r | |
995 | ///\r | |
996 | /// UNDI may need to block multi-threaded/multi-processor access to\r | |
997 | /// critical code sections when programming or accessing the network\r | |
998 | /// device. To this end, a blocking service is needed by the UNDI.\r | |
999 | /// When UNDI needs a block, it will call Block() passing a non-zero\r | |
1000 | /// value. When UNDI no longer needs a block, it will call Block()\r | |
1001 | /// with a zero value. When called, if the Block() is already enabled,\r | |
1002 | /// do not return control to the UNDI until the previous Block() is\r | |
1003 | /// disabled.\r | |
1004 | ///\r | |
1005 | /// This field cannot be set to zero.\r | |
1006 | ///\r | |
959ccb23 | 1007 | UINT64 Block;\r |
1008 | \r | |
3ed785e9 | 1009 | ///\r |
1010 | /// PXE_VOID Virt2Phys(UINT64 UnqId, UINT64 virtual, UINT64 physical_ptr);\r | |
1011 | ///\r | |
1012 | /// UNDI will pass the virtual address of a buffer and the virtual\r | |
1013 | /// address of a 64-bit physical buffer. Convert the virtual address\r | |
1014 | /// to a physical address and write the result to the physical address\r | |
1015 | /// buffer. If virtual and physical addresses are the same, just\r | |
1016 | /// copy the virtual address to the physical address buffer.\r | |
1017 | ///\r | |
1018 | /// This field can be set to zero if virtual and physical addresses\r | |
1019 | /// are equal.\r | |
1020 | ///\r | |
959ccb23 | 1021 | UINT64 Virt2Phys;\r |
3ed785e9 | 1022 | ///\r |
1023 | /// PXE_VOID Mem_IO(UINT64 UnqId, UINT8 read_write, UINT8 len, UINT64 port,\r | |
1024 | /// UINT64 buf_addr);\r | |
1025 | ///\r | |
1026 | /// UNDI will read or write the device io space using this call back\r | |
1027 | /// function. It passes the number of bytes as the len parameter and it\r | |
1028 | /// will be either 1,2,4 or 8.\r | |
1029 | ///\r | |
1030 | /// This field can not be set to zero.\r | |
1031 | ///\r | |
959ccb23 | 1032 | UINT64 Mem_IO;\r |
3ed785e9 | 1033 | ///\r |
1034 | /// PXE_VOID Map_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,\r | |
1035 | /// UINT32 Direction, UINT64 mapped_addr);\r | |
1036 | ///\r | |
1037 | /// UNDI will pass the virtual address of a buffer, direction of the data\r | |
1038 | /// flow from/to the mapped buffer (the constants are defined below)\r | |
1039 | /// and a place holder (pointer) for the mapped address.\r | |
1040 | /// This call will Map the given address to a physical DMA address and write\r | |
1041 | /// the result to the mapped_addr pointer. If there is no need to\r | |
1042 | /// map the given address to a lower address (i.e. the given address is\r | |
1043 | /// associated with a physical address that is already compatible to be\r | |
1044 | /// used with the DMA, it converts the given virtual address to it's\r | |
1045 | /// physical address and write that in the mapped address pointer.\r | |
1046 | ///\r | |
af2dc6a7 | 1047 | /// This field can be set to zero if there is no mapping service available.\r |
3ed785e9 | 1048 | ///\r |
959ccb23 | 1049 | UINT64 Map_Mem;\r |
1050 | \r | |
3ed785e9 | 1051 | ///\r |
1052 | /// PXE_VOID UnMap_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,\r | |
1053 | /// UINT32 Direction, UINT64 mapped_addr);\r | |
1054 | ///\r | |
af2dc6a7 | 1055 | /// UNDI will pass the virtual and mapped addresses of a buffer.\r |
1056 | /// This call will un map the given address.\r | |
3ed785e9 | 1057 | ///\r |
af2dc6a7 | 1058 | /// This field can be set to zero if there is no unmapping service available.\r |
3ed785e9 | 1059 | ///\r |
959ccb23 | 1060 | UINT64 UnMap_Mem;\r |
1061 | \r | |
3ed785e9 | 1062 | ///\r |
1063 | /// PXE_VOID Sync_Mem(UINT64 unq_id, UINT64 virtual,\r | |
1064 | /// UINT32 size, UINT32 Direction, UINT64 mapped_addr);\r | |
1065 | ///\r | |
af2dc6a7 | 1066 | /// UNDI will pass the virtual and mapped addresses of a buffer.\r |
1067 | /// This call will synchronize the contents of both the virtual and mapped.\r | |
3ed785e9 | 1068 | /// buffers for the given Direction.\r |
1069 | ///\r | |
af2dc6a7 | 1070 | /// This field can be set to zero if there is no service available.\r |
3ed785e9 | 1071 | ///\r |
959ccb23 | 1072 | UINT64 Sync_Mem;\r |
1073 | \r | |
3ed785e9 | 1074 | ///\r |
1075 | /// protocol driver can provide anything for this Unique_ID, UNDI remembers\r | |
00b7cc0f | 1076 | /// that as just a 64bit value associated to the interface specified by\r |
3ed785e9 | 1077 | /// the ifnum and gives it back as a parameter to all the call-back routines\r |
1078 | /// when calling for that interface!\r | |
1079 | ///\r | |
959ccb23 | 1080 | UINT64 Unique_ID;\r |
959ccb23 | 1081 | } PXE_CPB_START_31;\r |
1082 | \r | |
1083 | #define TO_AND_FROM_DEVICE 0\r | |
1084 | #define FROM_DEVICE 1\r | |
1085 | #define TO_DEVICE 2\r | |
1086 | \r | |
1087 | #define PXE_DELAY_MILLISECOND 1000\r | |
1088 | #define PXE_DELAY_SECOND 1000000\r | |
1089 | #define PXE_IO_READ 0\r | |
1090 | #define PXE_IO_WRITE 1\r | |
1091 | #define PXE_MEM_READ 2\r | |
1092 | #define PXE_MEM_WRITE 4\r | |
1093 | \r | |
1094 | typedef struct s_pxe_db_get_init_info {\r | |
3ed785e9 | 1095 | ///\r |
1096 | /// Minimum length of locked memory buffer that must be given to\r | |
1097 | /// the Initialize command. Giving UNDI more memory will generally\r | |
1098 | /// give better performance.\r | |
1099 | ///\r | |
1100 | /// If MemoryRequired is zero, the UNDI does not need and will not\r | |
1101 | /// use system memory to receive and transmit packets.\r | |
1102 | ///\r | |
959ccb23 | 1103 | PXE_UINT32 MemoryRequired;\r |
1104 | \r | |
3ed785e9 | 1105 | ///\r |
1106 | /// Maximum frame data length for Tx/Rx excluding the media header.\r | |
1107 | ///\r | |
959ccb23 | 1108 | PXE_UINT32 FrameDataLen;\r |
1109 | \r | |
3ed785e9 | 1110 | ///\r |
1111 | /// Supported link speeds are in units of mega bits. Common ethernet\r | |
1112 | /// values are 10, 100 and 1000. Unused LinkSpeeds[] entries are zero\r | |
1113 | /// filled.\r | |
1114 | ///\r | |
959ccb23 | 1115 | PXE_UINT32 LinkSpeeds[4];\r |
1116 | \r | |
3ed785e9 | 1117 | ///\r |
1118 | /// Number of non-volatile storage items.\r | |
1119 | ///\r | |
959ccb23 | 1120 | PXE_UINT32 NvCount;\r |
1121 | \r | |
3ed785e9 | 1122 | ///\r |
1123 | /// Width of non-volatile storage item in bytes. 0, 1, 2 or 4\r | |
1124 | ///\r | |
959ccb23 | 1125 | PXE_UINT16 NvWidth;\r |
1126 | \r | |
3ed785e9 | 1127 | ///\r |
1128 | /// Media header length. This is the typical media header length for\r | |
1129 | /// this UNDI. This information is needed when allocating receive\r | |
1130 | /// and transmit buffers.\r | |
1131 | ///\r | |
959ccb23 | 1132 | PXE_UINT16 MediaHeaderLen;\r |
1133 | \r | |
3ed785e9 | 1134 | ///\r |
1135 | /// Number of bytes in the NIC hardware (MAC) address.\r | |
1136 | ///\r | |
959ccb23 | 1137 | PXE_UINT16 HWaddrLen;\r |
1138 | \r | |
3ed785e9 | 1139 | ///\r |
1140 | /// Maximum number of multicast MAC addresses in the multicast\r | |
1141 | /// MAC address filter list.\r | |
1142 | ///\r | |
959ccb23 | 1143 | PXE_UINT16 MCastFilterCnt;\r |
1144 | \r | |
3ed785e9 | 1145 | ///\r |
1146 | /// Default number and size of transmit and receive buffers that will\r | |
1147 | /// be allocated by the UNDI. If MemoryRequired is non-zero, this\r | |
1148 | /// allocation will come out of the memory buffer given to the Initialize\r | |
1149 | /// command. If MemoryRequired is zero, this allocation will come out of\r | |
1150 | /// memory on the NIC.\r | |
1151 | ///\r | |
959ccb23 | 1152 | PXE_UINT16 TxBufCnt;\r |
1153 | PXE_UINT16 TxBufSize;\r | |
1154 | PXE_UINT16 RxBufCnt;\r | |
1155 | PXE_UINT16 RxBufSize;\r | |
1156 | \r | |
3ed785e9 | 1157 | ///\r |
1158 | /// Hardware interface types defined in the Assigned Numbers RFC\r | |
1159 | /// and used in DHCP and ARP packets.\r | |
1160 | /// See the PXE_IFTYPE typedef and PXE_IFTYPE_xxx macros.\r | |
1161 | ///\r | |
959ccb23 | 1162 | PXE_UINT8 IFtype;\r |
1163 | \r | |
3ed785e9 | 1164 | ///\r |
1165 | /// Supported duplex. See PXE_DUPLEX_xxxxx #defines below.\r | |
1166 | ///\r | |
959ccb23 | 1167 | PXE_UINT8 SupportedDuplexModes;\r |
1168 | \r | |
3ed785e9 | 1169 | ///\r |
1170 | /// Supported loopback options. See PXE_LOOPBACK_xxxxx #defines below.\r | |
1171 | ///\r | |
959ccb23 | 1172 | PXE_UINT8 SupportedLoopBackModes;\r |
1173 | } PXE_DB_GET_INIT_INFO;\r | |
1174 | \r | |
1175 | #define PXE_MAX_TXRX_UNIT_ETHER 1500\r | |
1176 | \r | |
1177 | #define PXE_HWADDR_LEN_ETHER 0x0006\r | |
1178 | #define PXE_MAC_HEADER_LEN_ETHER 0x000E\r | |
1179 | \r | |
1180 | #define PXE_DUPLEX_ENABLE_FULL_SUPPORTED 1\r | |
1181 | #define PXE_DUPLEX_FORCE_FULL_SUPPORTED 2\r | |
1182 | \r | |
1183 | #define PXE_LOOPBACK_INTERNAL_SUPPORTED 1\r | |
1184 | #define PXE_LOOPBACK_EXTERNAL_SUPPORTED 2\r | |
1185 | \r | |
1186 | typedef struct s_pxe_pci_config_info {\r | |
3ed785e9 | 1187 | ///\r |
1188 | /// This is the flag field for the PXE_DB_GET_CONFIG_INFO union.\r | |
1189 | /// For PCI bus devices, this field is set to PXE_BUSTYPE_PCI.\r | |
1190 | ///\r | |
959ccb23 | 1191 | UINT32 BusType;\r |
1192 | \r | |
3ed785e9 | 1193 | ///\r |
af2dc6a7 | 1194 | /// This identifies the PCI network device that this UNDI interface.\r |
3ed785e9 | 1195 | /// is bound to.\r |
1196 | ///\r | |
959ccb23 | 1197 | UINT16 Bus;\r |
1198 | UINT8 Device;\r | |
1199 | UINT8 Function;\r | |
1200 | \r | |
3ed785e9 | 1201 | ///\r |
1202 | /// This is a copy of the PCI configuration space for this\r | |
1203 | /// network device.\r | |
1204 | ///\r | |
959ccb23 | 1205 | union {\r |
1206 | UINT8 Byte[256];\r | |
1207 | UINT16 Word[128];\r | |
1208 | UINT32 Dword[64];\r | |
1209 | } Config;\r | |
1210 | } PXE_PCI_CONFIG_INFO;\r | |
1211 | \r | |
1212 | typedef struct s_pxe_pcc_config_info {\r | |
3ed785e9 | 1213 | ///\r |
1214 | /// This is the flag field for the PXE_DB_GET_CONFIG_INFO union.\r | |
1215 | /// For PCC bus devices, this field is set to PXE_BUSTYPE_PCC.\r | |
1216 | ///\r | |
959ccb23 | 1217 | PXE_UINT32 BusType;\r |
1218 | \r | |
3ed785e9 | 1219 | ///\r |
1220 | /// This identifies the PCC network device that this UNDI interface\r | |
1221 | /// is bound to.\r | |
1222 | ///\r | |
959ccb23 | 1223 | PXE_UINT16 Bus;\r |
1224 | PXE_UINT8 Device;\r | |
1225 | PXE_UINT8 Function;\r | |
1226 | \r | |
3ed785e9 | 1227 | ///\r |
1228 | /// This is a copy of the PCC configuration space for this\r | |
1229 | /// network device.\r | |
1230 | ///\r | |
959ccb23 | 1231 | union {\r |
1232 | PXE_UINT8 Byte[256];\r | |
1233 | PXE_UINT16 Word[128];\r | |
1234 | PXE_UINT32 Dword[64];\r | |
1235 | } Config;\r | |
1236 | } PXE_PCC_CONFIG_INFO;\r | |
1237 | \r | |
1238 | typedef union u_pxe_db_get_config_info {\r | |
1239 | PXE_PCI_CONFIG_INFO pci;\r | |
1240 | PXE_PCC_CONFIG_INFO pcc;\r | |
1241 | } PXE_DB_GET_CONFIG_INFO;\r | |
1242 | \r | |
1243 | typedef struct s_pxe_cpb_initialize {\r | |
3ed785e9 | 1244 | ///\r |
1245 | /// Address of first (lowest) byte of the memory buffer. This buffer must\r | |
1246 | /// be in contiguous physical memory and cannot be swapped out. The UNDI\r | |
1247 | /// will be using this for transmit and receive buffering.\r | |
1248 | ///\r | |
959ccb23 | 1249 | PXE_UINT64 MemoryAddr;\r |
1250 | \r | |
3ed785e9 | 1251 | ///\r |
1252 | /// MemoryLength must be greater than or equal to MemoryRequired\r | |
1253 | /// returned by the Get Init Info command.\r | |
1254 | ///\r | |
959ccb23 | 1255 | PXE_UINT32 MemoryLength;\r |
1256 | \r | |
3ed785e9 | 1257 | ///\r |
1258 | /// Desired link speed in Mbit/sec. Common ethernet values are 10, 100\r | |
1259 | /// and 1000. Setting a value of zero will auto-detect and/or use the\r | |
1260 | /// default link speed (operation depends on UNDI/NIC functionality).\r | |
1261 | ///\r | |
959ccb23 | 1262 | PXE_UINT32 LinkSpeed;\r |
1263 | \r | |
3ed785e9 | 1264 | ///\r |
1265 | /// Suggested number and size of receive and transmit buffers to\r | |
1266 | /// allocate. If MemoryAddr and MemoryLength are non-zero, this\r | |
1267 | /// allocation comes out of the supplied memory buffer. If MemoryAddr\r | |
1268 | /// and MemoryLength are zero, this allocation comes out of memory\r | |
1269 | /// on the NIC.\r | |
1270 | ///\r | |
1271 | /// If these fields are set to zero, the UNDI will allocate buffer\r | |
1272 | /// counts and sizes as it sees fit.\r | |
1273 | ///\r | |
959ccb23 | 1274 | PXE_UINT16 TxBufCnt;\r |
1275 | PXE_UINT16 TxBufSize;\r | |
1276 | PXE_UINT16 RxBufCnt;\r | |
1277 | PXE_UINT16 RxBufSize;\r | |
1278 | \r | |
3ed785e9 | 1279 | ///\r |
1280 | /// The following configuration parameters are optional and must be zero\r | |
1281 | /// to use the default values.\r | |
1282 | ///\r | |
959ccb23 | 1283 | PXE_UINT8 DuplexMode;\r |
1284 | \r | |
1285 | PXE_UINT8 LoopBackMode;\r | |
1286 | } PXE_CPB_INITIALIZE;\r | |
1287 | \r | |
1288 | #define PXE_DUPLEX_DEFAULT 0x00\r | |
1289 | #define PXE_FORCE_FULL_DUPLEX 0x01\r | |
1290 | #define PXE_ENABLE_FULL_DUPLEX 0x02\r | |
1291 | #define PXE_FORCE_HALF_DUPLEX 0x04\r | |
1292 | #define PXE_DISABLE_FULL_DUPLEX 0x08\r | |
1293 | \r | |
1294 | #define LOOPBACK_NORMAL 0\r | |
1295 | #define LOOPBACK_INTERNAL 1\r | |
1296 | #define LOOPBACK_EXTERNAL 2\r | |
1297 | \r | |
1298 | typedef struct s_pxe_db_initialize {\r | |
3ed785e9 | 1299 | ///\r |
1300 | /// Actual amount of memory used from the supplied memory buffer. This\r | |
1301 | /// may be less that the amount of memory suppllied and may be zero if\r | |
1302 | /// the UNDI and network device do not use external memory buffers.\r | |
1303 | ///\r | |
1304 | /// Memory used by the UNDI and network device is allocated from the\r | |
1305 | /// lowest memory buffer address.\r | |
1306 | ///\r | |
959ccb23 | 1307 | PXE_UINT32 MemoryUsed;\r |
1308 | \r | |
3ed785e9 | 1309 | ///\r |
1310 | /// Actual number and size of receive and transmit buffers that were\r | |
1311 | /// allocated.\r | |
1312 | ///\r | |
959ccb23 | 1313 | PXE_UINT16 TxBufCnt;\r |
1314 | PXE_UINT16 TxBufSize;\r | |
1315 | PXE_UINT16 RxBufCnt;\r | |
1316 | PXE_UINT16 RxBufSize;\r | |
1317 | } PXE_DB_INITIALIZE;\r | |
1318 | \r | |
1319 | typedef struct s_pxe_cpb_receive_filters {\r | |
3ed785e9 | 1320 | ///\r |
1321 | /// List of multicast MAC addresses. This list, if present, will\r | |
1322 | /// replace the existing multicast MAC address filter list.\r | |
1323 | ///\r | |
959ccb23 | 1324 | PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];\r |
1325 | } PXE_CPB_RECEIVE_FILTERS;\r | |
1326 | \r | |
1327 | typedef struct s_pxe_db_receive_filters {\r | |
3ed785e9 | 1328 | ///\r |
1329 | /// Filtered multicast MAC address list.\r | |
1330 | ///\r | |
959ccb23 | 1331 | PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];\r |
1332 | } PXE_DB_RECEIVE_FILTERS;\r | |
1333 | \r | |
1334 | typedef struct s_pxe_cpb_station_address {\r | |
3ed785e9 | 1335 | ///\r |
1336 | /// If supplied and supported, the current station MAC address\r | |
1337 | /// will be changed.\r | |
1338 | ///\r | |
959ccb23 | 1339 | PXE_MAC_ADDR StationAddr;\r |
1340 | } PXE_CPB_STATION_ADDRESS;\r | |
1341 | \r | |
1342 | typedef struct s_pxe_dpb_station_address {\r | |
3ed785e9 | 1343 | ///\r |
1344 | /// Current station MAC address.\r | |
1345 | ///\r | |
959ccb23 | 1346 | PXE_MAC_ADDR StationAddr;\r |
1347 | \r | |
3ed785e9 | 1348 | ///\r |
1349 | /// Station broadcast MAC address.\r | |
1350 | ///\r | |
959ccb23 | 1351 | PXE_MAC_ADDR BroadcastAddr;\r |
1352 | \r | |
3ed785e9 | 1353 | ///\r |
1354 | /// Permanent station MAC address.\r | |
1355 | ///\r | |
959ccb23 | 1356 | PXE_MAC_ADDR PermanentAddr;\r |
1357 | } PXE_DB_STATION_ADDRESS;\r | |
1358 | \r | |
1359 | typedef struct s_pxe_db_statistics {\r | |
3ed785e9 | 1360 | ///\r |
1361 | /// Bit field identifying what statistic data is collected by the\r | |
1362 | /// UNDI/NIC.\r | |
1363 | /// If bit 0x00 is set, Data[0x00] is collected.\r | |
1364 | /// If bit 0x01 is set, Data[0x01] is collected.\r | |
1365 | /// If bit 0x20 is set, Data[0x20] is collected.\r | |
1366 | /// If bit 0x21 is set, Data[0x21] is collected.\r | |
1367 | /// Etc.\r | |
1368 | ///\r | |
959ccb23 | 1369 | PXE_UINT64 Supported;\r |
1370 | \r | |
3ed785e9 | 1371 | ///\r |
1372 | /// Statistic data.\r | |
1373 | ///\r | |
959ccb23 | 1374 | PXE_UINT64 Data[64];\r |
1375 | } PXE_DB_STATISTICS;\r | |
1376 | \r | |
3ed785e9 | 1377 | ///\r |
1378 | /// Total number of frames received. Includes frames with errors and\r | |
1379 | /// dropped frames.\r | |
1380 | ///\r | |
959ccb23 | 1381 | #define PXE_STATISTICS_RX_TOTAL_FRAMES 0x00\r |
1382 | \r | |
3ed785e9 | 1383 | ///\r |
1384 | /// Number of valid frames received and copied into receive buffers.\r | |
1385 | ///\r | |
959ccb23 | 1386 | #define PXE_STATISTICS_RX_GOOD_FRAMES 0x01\r |
1387 | \r | |
3ed785e9 | 1388 | ///\r |
1389 | /// Number of frames below the minimum length for the media.\r | |
1390 | /// This would be <64 for ethernet.\r | |
1391 | ///\r | |
959ccb23 | 1392 | #define PXE_STATISTICS_RX_UNDERSIZE_FRAMES 0x02\r |
1393 | \r | |
3ed785e9 | 1394 | ///\r |
1395 | /// Number of frames longer than the maxminum length for the\r | |
1396 | /// media. This would be >1500 for ethernet.\r | |
1397 | ///\r | |
959ccb23 | 1398 | #define PXE_STATISTICS_RX_OVERSIZE_FRAMES 0x03\r |
1399 | \r | |
3ed785e9 | 1400 | ///\r |
1401 | /// Valid frames that were dropped because receive buffers were full.\r | |
1402 | ///\r | |
959ccb23 | 1403 | #define PXE_STATISTICS_RX_DROPPED_FRAMES 0x04\r |
1404 | \r | |
3ed785e9 | 1405 | ///\r |
1406 | /// Number of valid unicast frames received and not dropped.\r | |
1407 | ///\r | |
959ccb23 | 1408 | #define PXE_STATISTICS_RX_UNICAST_FRAMES 0x05\r |
1409 | \r | |
3ed785e9 | 1410 | ///\r |
1411 | /// Number of valid broadcast frames received and not dropped.\r | |
1412 | ///\r | |
959ccb23 | 1413 | #define PXE_STATISTICS_RX_BROADCAST_FRAMES 0x06\r |
1414 | \r | |
3ed785e9 | 1415 | ///\r |
1416 | /// Number of valid mutlicast frames received and not dropped.\r | |
1417 | ///\r | |
959ccb23 | 1418 | #define PXE_STATISTICS_RX_MULTICAST_FRAMES 0x07\r |
1419 | \r | |
3ed785e9 | 1420 | ///\r |
1421 | /// Number of frames w/ CRC or alignment errors.\r | |
1422 | ///\r | |
959ccb23 | 1423 | #define PXE_STATISTICS_RX_CRC_ERROR_FRAMES 0x08\r |
1424 | \r | |
3ed785e9 | 1425 | ///\r |
1426 | /// Total number of bytes received. Includes frames with errors\r | |
1427 | /// and dropped frames.\r | |
1428 | ///\r | |
959ccb23 | 1429 | #define PXE_STATISTICS_RX_TOTAL_BYTES 0x09\r |
1430 | \r | |
3ed785e9 | 1431 | ///\r |
1432 | /// Transmit statistics.\r | |
1433 | ///\r | |
959ccb23 | 1434 | #define PXE_STATISTICS_TX_TOTAL_FRAMES 0x0A\r |
1435 | #define PXE_STATISTICS_TX_GOOD_FRAMES 0x0B\r | |
1436 | #define PXE_STATISTICS_TX_UNDERSIZE_FRAMES 0x0C\r | |
1437 | #define PXE_STATISTICS_TX_OVERSIZE_FRAMES 0x0D\r | |
1438 | #define PXE_STATISTICS_TX_DROPPED_FRAMES 0x0E\r | |
1439 | #define PXE_STATISTICS_TX_UNICAST_FRAMES 0x0F\r | |
1440 | #define PXE_STATISTICS_TX_BROADCAST_FRAMES 0x10\r | |
1441 | #define PXE_STATISTICS_TX_MULTICAST_FRAMES 0x11\r | |
1442 | #define PXE_STATISTICS_TX_CRC_ERROR_FRAMES 0x12\r | |
1443 | #define PXE_STATISTICS_TX_TOTAL_BYTES 0x13\r | |
1444 | \r | |
3ed785e9 | 1445 | ///\r |
1446 | /// Number of collisions detection on this subnet.\r | |
1447 | ///\r | |
959ccb23 | 1448 | #define PXE_STATISTICS_COLLISIONS 0x14\r |
1449 | \r | |
3ed785e9 | 1450 | ///\r |
1451 | /// Number of frames destined for unsupported protocol.\r | |
1452 | ///\r | |
959ccb23 | 1453 | #define PXE_STATISTICS_UNSUPPORTED_PROTOCOL 0x15\r |
1454 | \r | |
b4bddb6e ZL |
1455 | ///\r |
1456 | /// Number of valid frames received that were duplicated.\r | |
1457 | ///\r | |
1458 | #define PXE_STATISTICS_RX_DUPLICATED_FRAMES 0x16\r | |
1459 | \r | |
1460 | ///\r | |
1461 | /// Number of encrypted frames received that failed to decrypt.\r | |
1462 | ///\r | |
1463 | #define PXE_STATISTICS_RX_DECRYPT_ERROR_FRAMES 0x17\r | |
1464 | \r | |
1465 | ///\r | |
1466 | /// Number of frames that failed to transmit after exceeding the retry limit.\r | |
1467 | ///\r | |
1468 | #define PXE_STATISTICS_TX_ERROR_FRAMES 0x18\r | |
1469 | \r | |
1470 | ///\r | |
1471 | /// Number of frames transmitted successfully after more than one attempt.\r | |
1472 | ///\r | |
1473 | #define PXE_STATISTICS_TX_RETRY_FRAMES 0x19\r | |
1474 | \r | |
959ccb23 | 1475 | typedef struct s_pxe_cpb_mcast_ip_to_mac {\r |
3ed785e9 | 1476 | ///\r |
1477 | /// Multicast IP address to be converted to multicast MAC address.\r | |
1478 | ///\r | |
959ccb23 | 1479 | PXE_IP_ADDR IP;\r |
1480 | } PXE_CPB_MCAST_IP_TO_MAC;\r | |
1481 | \r | |
1482 | typedef struct s_pxe_db_mcast_ip_to_mac {\r | |
3ed785e9 | 1483 | ///\r |
1484 | /// Multicast MAC address.\r | |
1485 | ///\r | |
959ccb23 | 1486 | PXE_MAC_ADDR MAC;\r |
1487 | } PXE_DB_MCAST_IP_TO_MAC;\r | |
1488 | \r | |
1489 | typedef struct s_pxe_cpb_nvdata_sparse {\r | |
3ed785e9 | 1490 | ///\r |
1491 | /// NvData item list. Only items in this list will be updated.\r | |
1492 | ///\r | |
959ccb23 | 1493 | struct {\r |
3ed785e9 | 1494 | ///\r |
1495 | /// Non-volatile storage address to be changed.\r | |
1496 | ///\r | |
959ccb23 | 1497 | PXE_UINT32 Addr;\r |
1498 | \r | |
3ed785e9 | 1499 | ///\r |
1500 | /// Data item to write into above storage address.\r | |
1501 | ///\r | |
959ccb23 | 1502 | union {\r |
1503 | PXE_UINT8 Byte;\r | |
1504 | PXE_UINT16 Word;\r | |
1505 | PXE_UINT32 Dword;\r | |
1506 | } Data;\r | |
1507 | } Item[MAX_EEPROM_LEN];\r | |
3ed785e9 | 1508 | } PXE_CPB_NVDATA_SPARSE;\r |
959ccb23 | 1509 | \r |
3ed785e9 | 1510 | ///\r |
1511 | /// When using bulk update, the size of the CPB structure must be\r | |
1512 | /// the same size as the non-volatile NIC storage.\r | |
1513 | ///\r | |
959ccb23 | 1514 | typedef union u_pxe_cpb_nvdata_bulk {\r |
3ed785e9 | 1515 | ///\r |
1516 | /// Array of byte-wide data items.\r | |
1517 | ///\r | |
959ccb23 | 1518 | PXE_UINT8 Byte[MAX_EEPROM_LEN << 2];\r |
1519 | \r | |
3ed785e9 | 1520 | ///\r |
1521 | /// Array of word-wide data items.\r | |
1522 | ///\r | |
959ccb23 | 1523 | PXE_UINT16 Word[MAX_EEPROM_LEN << 1];\r |
1524 | \r | |
3ed785e9 | 1525 | ///\r |
1526 | /// Array of dword-wide data items.\r | |
1527 | ///\r | |
959ccb23 | 1528 | PXE_UINT32 Dword[MAX_EEPROM_LEN];\r |
1529 | } PXE_CPB_NVDATA_BULK;\r | |
1530 | \r | |
1531 | typedef struct s_pxe_db_nvdata {\r | |
3ed785e9 | 1532 | ///\r |
1533 | /// Arrays of data items from non-volatile storage.\r | |
1534 | ///\r | |
959ccb23 | 1535 | union {\r |
3ed785e9 | 1536 | ///\r |
1537 | /// Array of byte-wide data items.\r | |
1538 | ///\r | |
959ccb23 | 1539 | PXE_UINT8 Byte[MAX_EEPROM_LEN << 2];\r |
1540 | \r | |
3ed785e9 | 1541 | ///\r |
1542 | /// Array of word-wide data items.\r | |
1543 | ///\r | |
959ccb23 | 1544 | PXE_UINT16 Word[MAX_EEPROM_LEN << 1];\r |
1545 | \r | |
3ed785e9 | 1546 | ///\r |
1547 | /// Array of dword-wide data items.\r | |
1548 | ///\r | |
959ccb23 | 1549 | PXE_UINT32 Dword[MAX_EEPROM_LEN];\r |
1550 | } Data;\r | |
1551 | } PXE_DB_NVDATA;\r | |
1552 | \r | |
1553 | typedef struct s_pxe_db_get_status {\r | |
3ed785e9 | 1554 | ///\r |
1555 | /// Length of next receive frame (header + data). If this is zero,\r | |
1556 | /// there is no next receive frame available.\r | |
1557 | ///\r | |
959ccb23 | 1558 | PXE_UINT32 RxFrameLen;\r |
1559 | \r | |
3ed785e9 | 1560 | ///\r |
1561 | /// Reserved, set to zero.\r | |
1562 | ///\r | |
959ccb23 | 1563 | PXE_UINT32 reserved;\r |
1564 | \r | |
3ed785e9 | 1565 | ///\r |
1566 | /// Addresses of transmitted buffers that need to be recycled.\r | |
1567 | ///\r | |
959ccb23 | 1568 | PXE_UINT64 TxBuffer[MAX_XMIT_BUFFERS];\r |
1569 | } PXE_DB_GET_STATUS;\r | |
1570 | \r | |
1571 | typedef struct s_pxe_cpb_fill_header {\r | |
3ed785e9 | 1572 | ///\r |
1573 | /// Source and destination MAC addresses. These will be copied into\r | |
1574 | /// the media header without doing byte swapping.\r | |
1575 | ///\r | |
959ccb23 | 1576 | PXE_MAC_ADDR SrcAddr;\r |
1577 | PXE_MAC_ADDR DestAddr;\r | |
1578 | \r | |
3ed785e9 | 1579 | ///\r |
1580 | /// Address of first byte of media header. The first byte of packet data\r | |
1581 | /// follows the last byte of the media header.\r | |
1582 | ///\r | |
959ccb23 | 1583 | PXE_UINT64 MediaHeader;\r |
1584 | \r | |
3ed785e9 | 1585 | ///\r |
1586 | /// Length of packet data in bytes (not including the media header).\r | |
1587 | ///\r | |
959ccb23 | 1588 | PXE_UINT32 PacketLen;\r |
1589 | \r | |
3ed785e9 | 1590 | ///\r |
1591 | /// Protocol type. This will be copied into the media header without\r | |
1592 | /// doing byte swapping. Protocol type numbers can be obtained from\r | |
1593 | /// the Assigned Numbers RFC 1700.\r | |
1594 | ///\r | |
959ccb23 | 1595 | PXE_UINT16 Protocol;\r |
1596 | \r | |
3ed785e9 | 1597 | ///\r |
1598 | /// Length of the media header in bytes.\r | |
1599 | ///\r | |
959ccb23 | 1600 | PXE_UINT16 MediaHeaderLen;\r |
1601 | } PXE_CPB_FILL_HEADER;\r | |
1602 | \r | |
1603 | #define PXE_PROTOCOL_ETHERNET_IP 0x0800\r | |
1604 | #define PXE_PROTOCOL_ETHERNET_ARP 0x0806\r | |
1605 | #define MAX_XMIT_FRAGMENTS 16\r | |
1606 | \r | |
1607 | typedef struct s_pxe_cpb_fill_header_fragmented {\r | |
3ed785e9 | 1608 | ///\r |
1609 | /// Source and destination MAC addresses. These will be copied into\r | |
1610 | /// the media header without doing byte swapping.\r | |
1611 | ///\r | |
959ccb23 | 1612 | PXE_MAC_ADDR SrcAddr;\r |
1613 | PXE_MAC_ADDR DestAddr;\r | |
1614 | \r | |
3ed785e9 | 1615 | ///\r |
1616 | /// Length of packet data in bytes (not including the media header).\r | |
1617 | ///\r | |
959ccb23 | 1618 | PXE_UINT32 PacketLen;\r |
1619 | \r | |
3ed785e9 | 1620 | ///\r |
1621 | /// Protocol type. This will be copied into the media header without\r | |
1622 | /// doing byte swapping. Protocol type numbers can be obtained from\r | |
1623 | /// the Assigned Numbers RFC 1700.\r | |
1624 | ///\r | |
959ccb23 | 1625 | PXE_MEDIA_PROTOCOL Protocol;\r |
1626 | \r | |
3ed785e9 | 1627 | ///\r |
1628 | /// Length of the media header in bytes.\r | |
1629 | ///\r | |
959ccb23 | 1630 | PXE_UINT16 MediaHeaderLen;\r |
1631 | \r | |
3ed785e9 | 1632 | ///\r |
1633 | /// Number of packet fragment descriptors.\r | |
1634 | ///\r | |
959ccb23 | 1635 | PXE_UINT16 FragCnt;\r |
1636 | \r | |
3ed785e9 | 1637 | ///\r |
1638 | /// Reserved, must be set to zero.\r | |
1639 | ///\r | |
959ccb23 | 1640 | PXE_UINT16 reserved;\r |
1641 | \r | |
3ed785e9 | 1642 | ///\r |
1643 | /// Array of packet fragment descriptors. The first byte of the media\r | |
1644 | /// header is the first byte of the first fragment.\r | |
1645 | ///\r | |
959ccb23 | 1646 | struct {\r |
3ed785e9 | 1647 | ///\r |
1648 | /// Address of this packet fragment.\r | |
1649 | ///\r | |
959ccb23 | 1650 | PXE_UINT64 FragAddr;\r |
1651 | \r | |
3ed785e9 | 1652 | ///\r |
1653 | /// Length of this packet fragment.\r | |
1654 | ///\r | |
959ccb23 | 1655 | PXE_UINT32 FragLen;\r |
1656 | \r | |
3ed785e9 | 1657 | ///\r |
1658 | /// Reserved, must be set to zero.\r | |
1659 | ///\r | |
959ccb23 | 1660 | PXE_UINT32 reserved;\r |
1661 | } FragDesc[MAX_XMIT_FRAGMENTS];\r | |
1662 | }\r | |
1663 | PXE_CPB_FILL_HEADER_FRAGMENTED;\r | |
1664 | \r | |
1665 | typedef struct s_pxe_cpb_transmit {\r | |
3ed785e9 | 1666 | ///\r |
1667 | /// Address of first byte of frame buffer. This is also the first byte\r | |
1668 | /// of the media header.\r | |
1669 | ///\r | |
959ccb23 | 1670 | PXE_UINT64 FrameAddr;\r |
1671 | \r | |
3ed785e9 | 1672 | ///\r |
1673 | /// Length of the data portion of the frame buffer in bytes. Do not\r | |
1674 | /// include the length of the media header.\r | |
1675 | ///\r | |
959ccb23 | 1676 | PXE_UINT32 DataLen;\r |
1677 | \r | |
3ed785e9 | 1678 | ///\r |
1679 | /// Length of the media header in bytes.\r | |
1680 | ///\r | |
959ccb23 | 1681 | PXE_UINT16 MediaheaderLen;\r |
1682 | \r | |
3ed785e9 | 1683 | ///\r |
1684 | /// Reserved, must be zero.\r | |
1685 | ///\r | |
959ccb23 | 1686 | PXE_UINT16 reserved;\r |
1687 | } PXE_CPB_TRANSMIT;\r | |
1688 | \r | |
1689 | typedef struct s_pxe_cpb_transmit_fragments {\r | |
3ed785e9 | 1690 | ///\r |
1691 | /// Length of packet data in bytes (not including the media header).\r | |
1692 | ///\r | |
959ccb23 | 1693 | PXE_UINT32 FrameLen;\r |
1694 | \r | |
3ed785e9 | 1695 | ///\r |
1696 | /// Length of the media header in bytes.\r | |
1697 | ///\r | |
959ccb23 | 1698 | PXE_UINT16 MediaheaderLen;\r |
1699 | \r | |
3ed785e9 | 1700 | ///\r |
1701 | /// Number of packet fragment descriptors.\r | |
1702 | ///\r | |
959ccb23 | 1703 | PXE_UINT16 FragCnt;\r |
1704 | \r | |
3ed785e9 | 1705 | ///\r |
1706 | /// Array of frame fragment descriptors. The first byte of the first\r | |
1707 | /// fragment is also the first byte of the media header.\r | |
1708 | ///\r | |
959ccb23 | 1709 | struct {\r |
3ed785e9 | 1710 | ///\r |
1711 | /// Address of this frame fragment.\r | |
1712 | ///\r | |
959ccb23 | 1713 | PXE_UINT64 FragAddr;\r |
1714 | \r | |
3ed785e9 | 1715 | ///\r |
1716 | /// Length of this frame fragment.\r | |
1717 | ///\r | |
959ccb23 | 1718 | PXE_UINT32 FragLen;\r |
1719 | \r | |
3ed785e9 | 1720 | ///\r |
1721 | /// Reserved, must be set to zero.\r | |
1722 | ///\r | |
959ccb23 | 1723 | PXE_UINT32 reserved;\r |
1724 | } FragDesc[MAX_XMIT_FRAGMENTS];\r | |
1725 | }\r | |
1726 | PXE_CPB_TRANSMIT_FRAGMENTS;\r | |
1727 | \r | |
1728 | typedef struct s_pxe_cpb_receive {\r | |
3ed785e9 | 1729 | ///\r |
1730 | /// Address of first byte of receive buffer. This is also the first byte\r | |
1731 | /// of the frame header.\r | |
1732 | ///\r | |
959ccb23 | 1733 | PXE_UINT64 BufferAddr;\r |
1734 | \r | |
3ed785e9 | 1735 | ///\r |
1736 | /// Length of receive buffer. This must be large enough to hold the\r | |
1737 | /// received frame (media header + data). If the length of smaller than\r | |
1738 | /// the received frame, data will be lost.\r | |
1739 | ///\r | |
959ccb23 | 1740 | PXE_UINT32 BufferLen;\r |
1741 | \r | |
3ed785e9 | 1742 | ///\r |
1743 | /// Reserved, must be set to zero.\r | |
1744 | ///\r | |
959ccb23 | 1745 | PXE_UINT32 reserved;\r |
1746 | } PXE_CPB_RECEIVE;\r | |
1747 | \r | |
1748 | typedef struct s_pxe_db_receive {\r | |
3ed785e9 | 1749 | ///\r |
1750 | /// Source and destination MAC addresses from media header.\r | |
1751 | ///\r | |
959ccb23 | 1752 | PXE_MAC_ADDR SrcAddr;\r |
1753 | PXE_MAC_ADDR DestAddr;\r | |
1754 | \r | |
3ed785e9 | 1755 | ///\r |
1756 | /// Length of received frame. May be larger than receive buffer size.\r | |
1757 | /// The receive buffer will not be overwritten. This is how to tell\r | |
1758 | /// if data was lost because the receive buffer was too small.\r | |
1759 | ///\r | |
959ccb23 | 1760 | PXE_UINT32 FrameLen;\r |
1761 | \r | |
3ed785e9 | 1762 | ///\r |
1763 | /// Protocol type from media header.\r | |
1764 | ///\r | |
959ccb23 | 1765 | PXE_MEDIA_PROTOCOL Protocol;\r |
1766 | \r | |
3ed785e9 | 1767 | ///\r |
1768 | /// Length of media header in received frame.\r | |
1769 | ///\r | |
959ccb23 | 1770 | PXE_UINT16 MediaHeaderLen;\r |
1771 | \r | |
3ed785e9 | 1772 | ///\r |
1773 | /// Type of receive frame.\r | |
1774 | ///\r | |
959ccb23 | 1775 | PXE_FRAME_TYPE Type;\r |
1776 | \r | |
3ed785e9 | 1777 | ///\r |
1778 | /// Reserved, must be zero.\r | |
1779 | ///\r | |
959ccb23 | 1780 | PXE_UINT8 reserved[7];\r |
1781 | \r | |
1782 | } PXE_DB_RECEIVE;\r | |
1783 | \r | |
959ccb23 | 1784 | #pragma pack()\r |
1785 | \r | |
1786 | #endif\r |