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e1f414b6 | 1 | /** @file\r |
2 | Cache Maintenance Functions.\r | |
3 | \r | |
ad400b07 | 4 | Copyright (c) 2006 - 2008, Intel Corporation<BR>\r |
e1f414b6 | 5 | All rights reserved. This program and the accompanying materials\r |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
f734a10a | 15 | #include <Base.h>\r |
a73480f6 | 16 | #include <Library/CacheMaintenanceLib.h>\r |
f734a10a A |
17 | #include <Library/BaseLib.h>\r |
18 | #include <Library/DebugLib.h>\r | |
fa73b3be | 19 | #include <Library/PalLib.h>\r |
e1f414b6 | 20 | \r |
21 | /**\r | |
22 | Invalidates the entire instruction cache in cache coherency domain of the\r | |
23 | calling CPU.\r | |
24 | \r | |
e1f414b6 | 25 | **/\r |
26 | VOID\r | |
27 | EFIAPI\r | |
28 | InvalidateInstructionCache (\r | |
29 | VOID\r | |
30 | )\r | |
31 | {\r | |
ad400b07 | 32 | PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_INSTRUCTION_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);\r |
e1f414b6 | 33 | }\r |
34 | \r | |
35 | /**\r | |
36 | Invalidates a range of instruction cache lines in the cache coherency domain\r | |
37 | of the calling CPU.\r | |
38 | \r | |
39 | Invalidates the instruction cache lines specified by Address and Length. If\r | |
40 | Address is not aligned on a cache line boundary, then entire instruction\r | |
41 | cache line containing Address is invalidated. If Address + Length is not\r | |
42 | aligned on a cache line boundary, then the entire instruction cache line\r | |
43 | containing Address + Length -1 is invalidated. This function may choose to\r | |
44 | invalidate the entire instruction cache if that is more efficient than\r | |
45 | invalidating the specified range. If Length is 0, the no instruction cache\r | |
46 | lines are invalidated. Address is returned.\r | |
47 | \r | |
48 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
49 | \r | |
50 | @param Address The base address of the instruction cache lines to\r | |
51 | invalidate. If the CPU is in a physical addressing mode, then\r | |
52 | Address is a physical address. If the CPU is in a virtual\r | |
53 | addressing mode, then Address is a virtual address.\r | |
54 | \r | |
55 | @param Length The number of bytes to invalidate from the instruction cache.\r | |
56 | \r | |
eb1c78db | 57 | @return Address.\r |
e1f414b6 | 58 | \r |
59 | **/\r | |
60 | VOID *\r | |
61 | EFIAPI\r | |
62 | InvalidateInstructionCacheRange (\r | |
63 | IN VOID *Address,\r | |
64 | IN UINTN Length\r | |
65 | )\r | |
66 | {\r | |
ad400b07 | 67 | ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r |
cc39b88b | 68 | return AsmFlushCacheRange (Address, Length);\r |
e1f414b6 | 69 | }\r |
70 | \r | |
71 | /**\r | |
72 | Writes Back and Invalidates the entire data cache in cache coherency domain\r | |
73 | of the calling CPU.\r | |
74 | \r | |
75 | Writes Back and Invalidates the entire data cache in cache coherency domain\r | |
76 | of the calling CPU. This function guarantees that all dirty cache lines are\r | |
77 | written back to system memory, and also invalidates all the data cache lines\r | |
78 | in the cache coherency domain of the calling CPU.\r | |
79 | \r | |
80 | **/\r | |
81 | VOID\r | |
82 | EFIAPI\r | |
83 | WriteBackInvalidateDataCache (\r | |
84 | VOID\r | |
85 | )\r | |
86 | {\r | |
ad400b07 | 87 | PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_DATA_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);\r |
e1f414b6 | 88 | }\r |
89 | \r | |
90 | /**\r | |
91 | Writes Back and Invalidates a range of data cache lines in the cache\r | |
92 | coherency domain of the calling CPU.\r | |
93 | \r | |
94 | Writes Back and Invalidate the data cache lines specified by Address and\r | |
95 | Length. If Address is not aligned on a cache line boundary, then entire data\r | |
96 | cache line containing Address is written back and invalidated. If Address +\r | |
97 | Length is not aligned on a cache line boundary, then the entire data cache\r | |
98 | line containing Address + Length -1 is written back and invalidated. This\r | |
99 | function may choose to write back and invalidate the entire data cache if\r | |
100 | that is more efficient than writing back and invalidating the specified\r | |
101 | range. If Length is 0, the no data cache lines are written back and\r | |
102 | invalidated. Address is returned.\r | |
103 | \r | |
104 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
105 | \r | |
106 | @param Address The base address of the data cache lines to write back and\r | |
107 | invalidate. If the CPU is in a physical addressing mode, then\r | |
108 | Address is a physical address. If the CPU is in a virtual\r | |
109 | addressing mode, then Address is a virtual address.\r | |
110 | @param Length The number of bytes to write back and invalidate from the\r | |
111 | data cache.\r | |
112 | \r | |
38bbd3d9 | 113 | @return Address of cache invalidation.\r |
e1f414b6 | 114 | \r |
115 | **/\r | |
116 | VOID *\r | |
117 | EFIAPI\r | |
118 | WriteBackInvalidateDataCacheRange (\r | |
119 | IN VOID *Address,\r | |
120 | IN UINTN Length\r | |
121 | )\r | |
122 | {\r | |
123 | ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r | |
124 | \r | |
cc39b88b | 125 | return AsmFlushCacheRange (Address, Length);\r |
e1f414b6 | 126 | }\r |
127 | \r | |
128 | /**\r | |
129 | Writes Back the entire data cache in cache coherency domain of the calling\r | |
130 | CPU.\r | |
131 | \r | |
132 | Writes Back the entire data cache in cache coherency domain of the calling\r | |
133 | CPU. This function guarantees that all dirty cache lines are written back to\r | |
134 | system memory. This function may also invalidate all the data cache lines in\r | |
135 | the cache coherency domain of the calling CPU.\r | |
136 | \r | |
137 | **/\r | |
138 | VOID\r | |
139 | EFIAPI\r | |
140 | WriteBackDataCache (\r | |
141 | VOID\r | |
142 | )\r | |
143 | {\r | |
4199d92d | 144 | PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_DATA_ALL, PAL_CACHE_FLUSH_NO_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);\r |
e1f414b6 | 145 | }\r |
146 | \r | |
147 | /**\r | |
148 | Writes Back a range of data cache lines in the cache coherency domain of the\r | |
149 | calling CPU.\r | |
150 | \r | |
151 | Writes Back the data cache lines specified by Address and Length. If Address\r | |
152 | is not aligned on a cache line boundary, then entire data cache line\r | |
153 | containing Address is written back. If Address + Length is not aligned on a\r | |
154 | cache line boundary, then the entire data cache line containing Address +\r | |
155 | Length -1 is written back. This function may choose to write back the entire\r | |
156 | data cache if that is more efficient than writing back the specified range.\r | |
157 | If Length is 0, the no data cache lines are written back. This function may\r | |
158 | also invalidate all the data cache lines in the specified range of the cache\r | |
159 | coherency domain of the calling CPU. Address is returned.\r | |
160 | \r | |
161 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
162 | \r | |
163 | @param Address The base address of the data cache lines to write back. If\r | |
164 | the CPU is in a physical addressing mode, then Address is a\r | |
165 | physical address. If the CPU is in a virtual addressing\r | |
166 | mode, then Address is a virtual address.\r | |
167 | @param Length The number of bytes to write back from the data cache.\r | |
168 | \r | |
ad400b07 | 169 | @return Address of cache written in main memory.\r |
e1f414b6 | 170 | \r |
171 | **/\r | |
172 | VOID *\r | |
173 | EFIAPI\r | |
174 | WriteBackDataCacheRange (\r | |
175 | IN VOID *Address,\r | |
176 | IN UINTN Length\r | |
177 | )\r | |
178 | {\r | |
179 | ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r | |
180 | \r | |
cc39b88b | 181 | return AsmFlushCacheRange (Address, Length);\r |
e1f414b6 | 182 | }\r |
183 | \r | |
184 | /**\r | |
185 | Invalidates the entire data cache in cache coherency domain of the calling\r | |
186 | CPU.\r | |
187 | \r | |
188 | Invalidates the entire data cache in cache coherency domain of the calling\r | |
189 | CPU. This function must be used with care because dirty cache lines are not\r | |
190 | written back to system memory. It is typically used for cache diagnostics. If\r | |
191 | the CPU does not support invalidation of the entire data cache, then a write\r | |
192 | back and invalidate operation should be performed on the entire data cache.\r | |
193 | \r | |
194 | **/\r | |
195 | VOID\r | |
196 | EFIAPI\r | |
197 | InvalidateDataCache (\r | |
198 | VOID\r | |
199 | )\r | |
200 | {\r | |
ad400b07 | 201 | //\r |
202 | // Invalidation of entire data cache without writing back is not supported on\r | |
203 | // IPF architecture, so write back and invalidate operation is performed.\r | |
204 | //\r | |
e1f414b6 | 205 | WriteBackInvalidateDataCache ();\r |
206 | }\r | |
207 | \r | |
208 | /**\r | |
209 | Invalidates a range of data cache lines in the cache coherency domain of the\r | |
210 | calling CPU.\r | |
211 | \r | |
212 | Invalidates the data cache lines specified by Address and Length. If Address\r | |
213 | is not aligned on a cache line boundary, then entire data cache line\r | |
214 | containing Address is invalidated. If Address + Length is not aligned on a\r | |
215 | cache line boundary, then the entire data cache line containing Address +\r | |
216 | Length -1 is invalidated. This function must never invalidate any cache lines\r | |
217 | outside the specified range. If Length is 0, the no data cache lines are\r | |
218 | invalidated. Address is returned. This function must be used with care\r | |
219 | because dirty cache lines are not written back to system memory. It is\r | |
220 | typically used for cache diagnostics. If the CPU does not support\r | |
221 | invalidation of a data cache range, then a write back and invalidate\r | |
222 | operation should be performed on the data cache range.\r | |
223 | \r | |
224 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
225 | \r | |
226 | @param Address The base address of the data cache lines to invalidate. If\r | |
227 | the CPU is in a physical addressing mode, then Address is a\r | |
228 | physical address. If the CPU is in a virtual addressing mode,\r | |
229 | then Address is a virtual address.\r | |
230 | @param Length The number of bytes to invalidate from the data cache.\r | |
231 | \r | |
eb1c78db | 232 | @return Address.\r |
e1f414b6 | 233 | \r |
234 | **/\r | |
235 | VOID *\r | |
236 | EFIAPI\r | |
237 | InvalidateDataCacheRange (\r | |
238 | IN VOID *Address,\r | |
239 | IN UINTN Length\r | |
240 | )\r | |
241 | {\r | |
ad400b07 | 242 | ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r |
243 | //\r | |
244 | // Invalidation of a data cache range without writing back is not supported on\r | |
245 | // IPF architecture, so write back and invalidate operation is performed.\r | |
246 | //\r | |
cc39b88b | 247 | return AsmFlushCacheRange (Address, Length);\r |
e1f414b6 | 248 | }\r |