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e1f414b6 | 1 | /** @file\r |
2 | Cache Maintenance Functions.\r | |
3 | \r | |
2f7c0ad1 HT |
4 | Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r |
5 | This program and the accompanying materials\r | |
e1f414b6 | 6 | are licensed and made available under the terms and conditions of the BSD License\r |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
35a17154 | 8 | http://opensource.org/licenses/bsd-license.php.\r |
e1f414b6 | 9 | \r |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
e1f414b6 | 13 | \r |
14 | **/\r | |
15 | \r | |
f734a10a A |
16 | #include <Base.h>\r |
17 | #include <Library/BaseLib.h>\r | |
18 | #include <Library/DebugLib.h>\r | |
e1f414b6 | 19 | \r |
20 | //\r | |
21 | // This size must be at or below the smallest cache size possible among all\r | |
22 | // supported processors\r | |
23 | //\r | |
24 | #define CACHE_LINE_SIZE 0x20\r | |
25 | \r | |
26 | /**\r | |
27 | Invalidates the entire instruction cache in cache coherency domain of the\r | |
28 | calling CPU.\r | |
29 | \r | |
e1f414b6 | 30 | **/\r |
31 | VOID\r | |
32 | EFIAPI\r | |
33 | InvalidateInstructionCache (\r | |
34 | VOID\r | |
35 | )\r | |
36 | {\r | |
37 | }\r | |
38 | \r | |
39 | /**\r | |
40 | Invalidates a range of instruction cache lines in the cache coherency domain\r | |
41 | of the calling CPU.\r | |
42 | \r | |
43 | Invalidates the instruction cache lines specified by Address and Length. If\r | |
44 | Address is not aligned on a cache line boundary, then entire instruction\r | |
45 | cache line containing Address is invalidated. If Address + Length is not\r | |
46 | aligned on a cache line boundary, then the entire instruction cache line\r | |
47 | containing Address + Length -1 is invalidated. This function may choose to\r | |
48 | invalidate the entire instruction cache if that is more efficient than\r | |
35a17154 | 49 | invalidating the specified range. If Length is 0, then no instruction cache\r |
e1f414b6 | 50 | lines are invalidated. Address is returned.\r |
51 | \r | |
52 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
53 | \r | |
54 | @param Address The base address of the instruction cache lines to\r | |
55 | invalidate. If the CPU is in a physical addressing mode, then\r | |
56 | Address is a physical address. If the CPU is in a virtual\r | |
57 | addressing mode, then Address is a virtual address.\r | |
58 | \r | |
59 | @param Length The number of bytes to invalidate from the instruction cache.\r | |
60 | \r | |
eb1c78db | 61 | @return Address.\r |
e1f414b6 | 62 | \r |
63 | **/\r | |
64 | VOID *\r | |
65 | EFIAPI\r | |
66 | InvalidateInstructionCacheRange (\r | |
67 | IN VOID *Address,\r | |
68 | IN UINTN Length\r | |
69 | )\r | |
70 | {\r | |
351d6e7f LG |
71 | if (Length == 0) {\r |
72 | return Address;\r | |
73 | }\r | |
74 | \r | |
75 | ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Address));\r | |
e1f414b6 | 76 | return Address;\r |
77 | }\r | |
78 | \r | |
79 | /**\r | |
35a17154 | 80 | Writes back and invalidates the entire data cache in cache coherency domain\r |
e1f414b6 | 81 | of the calling CPU.\r |
82 | \r | |
35a17154 | 83 | Writes back and invalidates the entire data cache in cache coherency domain\r |
e1f414b6 | 84 | of the calling CPU. This function guarantees that all dirty cache lines are\r |
85 | written back to system memory, and also invalidates all the data cache lines\r | |
86 | in the cache coherency domain of the calling CPU.\r | |
87 | \r | |
88 | **/\r | |
89 | VOID\r | |
90 | EFIAPI\r | |
91 | WriteBackInvalidateDataCache (\r | |
92 | VOID\r | |
93 | )\r | |
94 | {\r | |
95 | AsmWbinvd ();\r | |
96 | }\r | |
97 | \r | |
98 | /**\r | |
35a17154 | 99 | Writes back and invalidates a range of data cache lines in the cache\r |
e1f414b6 | 100 | coherency domain of the calling CPU.\r |
101 | \r | |
35a17154 | 102 | Writes back and invalidates the data cache lines specified by Address and\r |
e1f414b6 | 103 | Length. If Address is not aligned on a cache line boundary, then entire data\r |
104 | cache line containing Address is written back and invalidated. If Address +\r | |
105 | Length is not aligned on a cache line boundary, then the entire data cache\r | |
106 | line containing Address + Length -1 is written back and invalidated. This\r | |
107 | function may choose to write back and invalidate the entire data cache if\r | |
108 | that is more efficient than writing back and invalidating the specified\r | |
35a17154 | 109 | range. If Length is 0, then no data cache lines are written back and\r |
e1f414b6 | 110 | invalidated. Address is returned.\r |
111 | \r | |
112 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
113 | \r | |
114 | @param Address The base address of the data cache lines to write back and\r | |
115 | invalidate. If the CPU is in a physical addressing mode, then\r | |
116 | Address is a physical address. If the CPU is in a virtual\r | |
117 | addressing mode, then Address is a virtual address.\r | |
118 | @param Length The number of bytes to write back and invalidate from the\r | |
119 | data cache.\r | |
120 | \r | |
38bbd3d9 | 121 | @return Address of cache invalidation.\r |
e1f414b6 | 122 | \r |
123 | **/\r | |
124 | VOID *\r | |
125 | EFIAPI\r | |
126 | WriteBackInvalidateDataCacheRange (\r | |
127 | IN VOID *Address,\r | |
128 | IN UINTN Length\r | |
129 | )\r | |
130 | {\r | |
ad400b07 | 131 | UINTN Start;\r |
132 | UINTN End;\r | |
e1f414b6 | 133 | \r |
e1f414b6 | 134 | if (Length == 0) {\r |
135 | return Address;\r | |
136 | }\r | |
137 | \r | |
351d6e7f LG |
138 | ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Address));\r |
139 | \r | |
e1f414b6 | 140 | Start = (UINTN)Address;\r |
38bbd3d9 | 141 | //\r |
142 | // Calculate the cache line alignment\r | |
143 | // \r | |
e1f414b6 | 144 | End = (Start + Length + (CACHE_LINE_SIZE - 1)) & ~(CACHE_LINE_SIZE - 1);\r |
145 | Start &= ~(CACHE_LINE_SIZE - 1);\r | |
146 | \r | |
147 | do {\r | |
148 | Start = (UINTN)AsmFlushCacheLine ((VOID*)Start) + CACHE_LINE_SIZE;\r | |
149 | } while (Start != End);\r | |
150 | return Address;\r | |
151 | }\r | |
152 | \r | |
153 | /**\r | |
35a17154 | 154 | Writes back the entire data cache in cache coherency domain of the calling\r |
e1f414b6 | 155 | CPU.\r |
156 | \r | |
35a17154 | 157 | Writes back the entire data cache in cache coherency domain of the calling\r |
e1f414b6 | 158 | CPU. This function guarantees that all dirty cache lines are written back to\r |
159 | system memory. This function may also invalidate all the data cache lines in\r | |
160 | the cache coherency domain of the calling CPU.\r | |
161 | \r | |
162 | **/\r | |
163 | VOID\r | |
164 | EFIAPI\r | |
165 | WriteBackDataCache (\r | |
166 | VOID\r | |
167 | )\r | |
168 | {\r | |
169 | WriteBackInvalidateDataCache ();\r | |
170 | }\r | |
171 | \r | |
172 | /**\r | |
35a17154 | 173 | Writes back a range of data cache lines in the cache coherency domain of the\r |
e1f414b6 | 174 | calling CPU.\r |
175 | \r | |
35a17154 | 176 | Writes back the data cache lines specified by Address and Length. If Address\r |
e1f414b6 | 177 | is not aligned on a cache line boundary, then entire data cache line\r |
178 | containing Address is written back. If Address + Length is not aligned on a\r | |
179 | cache line boundary, then the entire data cache line containing Address +\r | |
180 | Length -1 is written back. This function may choose to write back the entire\r | |
181 | data cache if that is more efficient than writing back the specified range.\r | |
35a17154 | 182 | If Length is 0, then no data cache lines are written back. This function may\r |
e1f414b6 | 183 | also invalidate all the data cache lines in the specified range of the cache\r |
184 | coherency domain of the calling CPU. Address is returned.\r | |
185 | \r | |
186 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
187 | \r | |
188 | @param Address The base address of the data cache lines to write back. If\r | |
189 | the CPU is in a physical addressing mode, then Address is a\r | |
190 | physical address. If the CPU is in a virtual addressing\r | |
191 | mode, then Address is a virtual address.\r | |
192 | @param Length The number of bytes to write back from the data cache.\r | |
193 | \r | |
ad400b07 | 194 | @return Address of cache written in main memory.\r |
e1f414b6 | 195 | \r |
196 | **/\r | |
197 | VOID *\r | |
198 | EFIAPI\r | |
199 | WriteBackDataCacheRange (\r | |
200 | IN VOID *Address,\r | |
201 | IN UINTN Length\r | |
202 | )\r | |
203 | {\r | |
204 | return WriteBackInvalidateDataCacheRange (Address, Length);\r | |
205 | }\r | |
206 | \r | |
207 | /**\r | |
208 | Invalidates the entire data cache in cache coherency domain of the calling\r | |
209 | CPU.\r | |
210 | \r | |
211 | Invalidates the entire data cache in cache coherency domain of the calling\r | |
212 | CPU. This function must be used with care because dirty cache lines are not\r | |
213 | written back to system memory. It is typically used for cache diagnostics. If\r | |
214 | the CPU does not support invalidation of the entire data cache, then a write\r | |
215 | back and invalidate operation should be performed on the entire data cache.\r | |
216 | \r | |
217 | **/\r | |
218 | VOID\r | |
219 | EFIAPI\r | |
220 | InvalidateDataCache (\r | |
221 | VOID\r | |
222 | )\r | |
223 | {\r | |
224 | AsmInvd ();\r | |
225 | }\r | |
226 | \r | |
227 | /**\r | |
228 | Invalidates a range of data cache lines in the cache coherency domain of the\r | |
229 | calling CPU.\r | |
230 | \r | |
231 | Invalidates the data cache lines specified by Address and Length. If Address\r | |
232 | is not aligned on a cache line boundary, then entire data cache line\r | |
233 | containing Address is invalidated. If Address + Length is not aligned on a\r | |
234 | cache line boundary, then the entire data cache line containing Address +\r | |
235 | Length -1 is invalidated. This function must never invalidate any cache lines\r | |
35a17154 | 236 | outside the specified range. If Length is 0, then no data cache lines are\r |
e1f414b6 | 237 | invalidated. Address is returned. This function must be used with care\r |
238 | because dirty cache lines are not written back to system memory. It is\r | |
239 | typically used for cache diagnostics. If the CPU does not support\r | |
240 | invalidation of a data cache range, then a write back and invalidate\r | |
241 | operation should be performed on the data cache range.\r | |
242 | \r | |
243 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
244 | \r | |
245 | @param Address The base address of the data cache lines to invalidate. If\r | |
246 | the CPU is in a physical addressing mode, then Address is a\r | |
247 | physical address. If the CPU is in a virtual addressing mode,\r | |
248 | then Address is a virtual address.\r | |
249 | @param Length The number of bytes to invalidate from the data cache.\r | |
250 | \r | |
eb1c78db | 251 | @return Address.\r |
e1f414b6 | 252 | \r |
253 | **/\r | |
254 | VOID *\r | |
255 | EFIAPI\r | |
256 | InvalidateDataCacheRange (\r | |
257 | IN VOID *Address,\r | |
258 | IN UINTN Length\r | |
259 | )\r | |
260 | {\r | |
ad400b07 | 261 | //\r |
262 | // Invalidation of a data cache range without writing back is not supported on\r | |
263 | // x86 architecture, so write back and invalidate operation is performed.\r | |
264 | //\r | |
e1f414b6 | 265 | return WriteBackInvalidateDataCacheRange (Address, Length);\r |
266 | }\r |