]>
Commit | Line | Data |
---|---|---|
f1baef62 | 1 | /** @file\r |
2 | Base Library CPU Functions for EBC\r | |
3 | \r | |
76d99594 | 4 | Copyright (c) 2006 - 2008, Intel Corporation<BR>\r |
f1baef62 | 5 | All rights reserved. This program and the accompanying materials\r |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
1efcc4ae | 14 | \r |
47fc17d8 | 15 | #include "BaseLibInternals.h"\r |
f1baef62 | 16 | \r |
17 | extern\r | |
18 | UINT64\r | |
19 | _break (\r | |
20 | CHAR8 BreakCode\r | |
21 | );\r | |
22 | \r | |
23 | /**\r | |
24 | Generates a breakpoint on the CPU.\r | |
25 | \r | |
26 | Generates a breakpoint on the CPU. The breakpoint must be implemented such\r | |
27 | that code can resume normal execution after the breakpoint.\r | |
28 | \r | |
29 | **/\r | |
30 | VOID\r | |
31 | EFIAPI\r | |
32 | CpuBreakpoint (\r | |
33 | VOID\r | |
34 | )\r | |
35 | {\r | |
36 | _break (3);\r | |
37 | }\r | |
38 | \r | |
39 | /**\r | |
40 | Used to serialize load and store operations.\r | |
41 | \r | |
42 | All loads and stores that proceed calls to this function are guaranteed to be\r | |
43 | globally visible when this function returns.\r | |
44 | \r | |
45 | **/\r | |
46 | VOID\r | |
47 | EFIAPI\r | |
48 | MemoryFence (\r | |
49 | VOID\r | |
50 | )\r | |
51 | {\r | |
52 | }\r | |
53 | \r | |
54 | /**\r | |
55 | Disables CPU interrupts.\r | |
56 | \r | |
f1baef62 | 57 | **/\r |
58 | VOID\r | |
59 | EFIAPI\r | |
60 | DisableInterrupts (\r | |
61 | VOID\r | |
62 | )\r | |
63 | {\r | |
64 | ASSERT (FALSE);\r | |
65 | }\r | |
66 | \r | |
67 | /**\r | |
68 | Enables CPU interrupts.\r | |
69 | \r | |
f1baef62 | 70 | **/\r |
71 | VOID\r | |
72 | EFIAPI\r | |
73 | EnableInterrupts (\r | |
74 | VOID\r | |
75 | )\r | |
76 | {\r | |
77 | ASSERT (FALSE);\r | |
78 | }\r | |
79 | \r | |
80 | /**\r | |
81 | Retrieves the current CPU interrupt state.\r | |
82 | \r | |
9aa049d9 | 83 | Returns TRUE is interrupts are currently enabled. Otherwise\r |
84 | returns FALSE.\r | |
f1baef62 | 85 | \r |
86 | @retval TRUE CPU interrupts are enabled.\r | |
87 | @retval FALSE CPU interrupts are disabled.\r | |
88 | \r | |
89 | **/\r | |
90 | BOOLEAN\r | |
91 | EFIAPI\r | |
92 | GetInterruptState (\r | |
93 | VOID\r | |
94 | )\r | |
95 | {\r | |
96 | ASSERT (FALSE);\r | |
97 | return FALSE;\r | |
98 | }\r | |
99 | \r | |
100 | /**\r | |
101 | Enables CPU interrupts for the smallest window required to capture any\r | |
102 | pending interrupts.\r | |
103 | \r | |
f1baef62 | 104 | **/\r |
105 | VOID\r | |
106 | EFIAPI\r | |
107 | EnableDisableInterrupts (\r | |
108 | VOID\r | |
109 | )\r | |
110 | {\r | |
111 | EnableInterrupts ();\r | |
112 | DisableInterrupts ();\r | |
113 | }\r | |
114 | \r | |
115 | /**\r | |
116 | Requests CPU to pause for a short period of time.\r | |
117 | \r | |
118 | Requests CPU to pause for a short period of time. Typically used in MP\r | |
119 | systems to prevent memory starvation while waiting for a spin lock.\r | |
120 | \r | |
121 | **/\r | |
122 | VOID\r | |
123 | EFIAPI\r | |
124 | CpuPause (\r | |
125 | VOID\r | |
126 | )\r | |
127 | {\r | |
128 | }\r | |
129 | \r |