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9f4f2f0e | 1 | /** @file\r |
2 | AsmDisableCache function\r | |
3 | \r | |
bb817c56 HT |
4 | Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r |
5 | This program and the accompanying materials\r | |
9f4f2f0e | 6 | are licensed and made available under the terms and conditions of the BSD License\r |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
35a17154 | 8 | http://opensource.org/licenses/bsd-license.php.\r |
9f4f2f0e | 9 | \r |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | /**\r | |
be5f1614 | 16 | Set CD bit and clear NW bit of CR0 followed by a WBINVD.\r |
9f4f2f0e | 17 | \r |
be5f1614 | 18 | Disables the caches by setting the CD bit of CR0 to 1, clearing the NW bit of CR0 to 0,\r |
19 | and executing a WBINVD instruction. This function is only available on IA-32 and x64.\r | |
9f4f2f0e | 20 | \r |
21 | **/\r | |
22 | VOID\r | |
23 | EFIAPI\r | |
24 | AsmDisableCache (\r | |
25 | VOID\r | |
26 | )\r | |
27 | {\r | |
28 | _asm {\r | |
29 | mov eax, cr0\r | |
30 | bts eax, 30\r | |
31 | btr eax, 29\r | |
32 | mov cr0, eax\r | |
33 | wbinvd\r | |
34 | }\r | |
35 | }\r | |
36 | \r |