[mirror_edk2.git] / MdePkg / Library / BaseLib / Ia32 / Thunk16.S

#------------------------------------------------------------------------------\r
#\r
# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution.  The full text of the license may be found at\r
# http://opensource.org/licenses/bsd-license.php.\r
#\r
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
#\r
# Module Name:\r
#\r
#   Thunk16.S\r
#\r
# Abstract:\r
#\r
#   Real mode thunk\r
#\r
#------------------------------------------------------------------------------\r
\r
#include <Library/BaseLib.h>\r
\r
ASM_GLOBAL ASM_PFX(m16Start), ASM_PFX(m16Size), ASM_PFX(mThunk16Attr), ASM_PFX(m16Gdt), ASM_PFX(m16GdtrBase), ASM_PFX(mTransition)\r
ASM_GLOBAL ASM_PFX(InternalAsmThunk16)\r
\r
# define the structure of IA32_REGS\r
.set  _EDI, 0       #size 4\r
.set  _ESI, 4       #size 4\r
.set  _EBP, 8       #size 4\r
.set  _ESP, 12      #size 4\r
.set  _EBX, 16      #size 4\r
.set  _EDX, 20      #size 4\r
.set  _ECX, 24      #size 4\r
.set  _EAX, 28      #size 4\r
.set  _DS,  32      #size 2\r
.set  _ES,  34      #size 2\r
.set  _FS,  36      #size 2\r
.set  _GS,  38      #size 2\r
.set  _EFLAGS, 40   #size 4\r
.set  _EIP, 44      #size 4\r
.set  _CS, 48       #size 2\r
.set  _SS, 50       #size 2\r
.set  IA32_REGS_SIZE, 52\r
\r
    .text\r
    .code16\r
\r
ASM_PFX(m16Start):\r
\r
SavedGdt:     .space  6\r
\r
ASM_PFX(BackFromUserCode):\r
    push    %ss\r
    push    %cs\r
\r
    calll   L_Base1                     # push eip\r
L_Base1:\r
    pushfl\r
    cli                                 # disable interrupts\r
    push    %gs\r
    push    %fs\r
    push    %es\r
    push    %ds\r
    pushal\r
    .byte   0x66, 0xba                  # mov edx, imm32\r
ASM_PFX(ThunkAttr): .space  4\r
    testb   $THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15, %dl\r
    jz      1f\r
    movw    $0x2401, %ax\r
    int     $0x15\r
    cli                                 # disable interrupts\r
    jnc     2f\r
1:\r
    testb   $THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL, %dl\r
    jz      2f\r
    inb     $0x92, %al\r
    orb     $2, %al\r
    outb    %al, $0x92                  # deactivate A20M#\r
2:\r
    xorl    %eax, %eax\r
    movw    %ss, %ax\r
    leal    IA32_REGS_SIZE(%esp), %ebp\r
    mov     %ebp, (_ESP - IA32_REGS_SIZE)(%bp)\r
    mov     (_EIP - IA32_REGS_SIZE)(%bp), %bx\r
    shll    $4, %eax\r
    addl    %eax, %ebp\r
    .byte   0x66, 0xb8                  # mov eax, imm32\r
SavedCr4:   .space  4\r
    movl    %eax, %cr4\r
    lgdtl   %cs:(SavedGdt - L_Base1)(%bx)\r
    .byte   0x66, 0xb8                  # mov eax, imm32\r
SavedCr0:   .space  4\r
    movl    %eax, %cr0\r
    .byte   0xb8                        # mov ax, imm16\r
SavedSs:    .space  2\r
    movl    %eax, %ss\r
    .byte   0x66, 0xbc                  # mov esp, imm32\r
SavedEsp:   .space  4\r
    lretl                               # return to protected mode\r
\r
_EntryPoint:    .long      ASM_PFX(ToUserCode) - ASM_PFX(m16Start)\r
                .word      0x8\r
_16Idtr:        .word      0x3ff\r
                .long      0\r
_16Gdtr:        .word      GdtEnd - _NullSegDesc - 1\r
_16GdtrBase:    .long      _NullSegDesc\r
\r
ASM_PFX(ToUserCode):\r
    movw    %ss, %dx\r
    movw    %cx, %ss                    # set new segment selectors\r
    movw    %cx, %ds\r
    movw    %cx, %es\r
    movw    %cx, %fs\r
    movw    %cx, %gs\r
    movl    %eax, %cr0                  # real mode starts at next instruction\r
                                        #  which (per SDM) *must* be a far JMP.\r
    ljmpw   $0,$0                       # will be filled in by InternalAsmThunk16\r
L_Base:                                 #  to point here.\r
    movl    %ebp, %cr4\r
    movw    %si, %ss                    # set up 16-bit stack segment\r
    xchgl   %ebx, %esp                  # set up 16-bit stack pointer\r
\r
    movw    IA32_REGS_SIZE(%esp), %bp   # get BackToUserCode address from stack\r
    mov     %dx, %cs:(SavedSs - ASM_PFX(BackFromUserCode))(%bp)\r
    mov     %ebx, %cs:(SavedEsp - ASM_PFX(BackFromUserCode))(%bp)\r
    lidtl   %cs:(_16Idtr - ASM_PFX(BackFromUserCode))(%bp)\r
    popal\r
    pop     %ds\r
    pop     %es\r
    pop     %fs\r
    pop     %gs\r
    popfl\r
    lretl                               # transfer control to user code\r
\r
_NullSegDesc:   .quad   0\r
_16CsDesc:\r
                .word   -1\r
                .word   0\r
                .byte   0\r
                .byte   0x9b\r
                .byte   0x8f            # 16-bit segment, 4GB limit\r
                .byte   0\r
_16DsDesc:\r
                .word   -1\r
                .word   0\r
                .byte   0\r
                .byte   0x93\r
                .byte   0x8f            # 16-bit segment, 4GB limit\r
                .byte   0\r
GdtEnd:\r
\r
    .code32\r
#\r
#   @param  RegSet  The pointer to a IA32_DWORD_REGS structure\r
#   @param  Transition  The pointer to the transition code\r
#   @return The address of the 16-bit stack after returning from user code\r
#\r
ASM_PFX(InternalAsmThunk16):\r
    push    %ebp\r
    push    %ebx\r
    push    %esi\r
    push    %edi\r
    push    %ds\r
    push    %es\r
    push    %fs\r
    push    %gs\r
    movl    36(%esp), %esi              # esi <- RegSet\r
    movzwl  _SS(%esi), %edx\r
    mov     _ESP(%esi), %edi\r
    add     $(-(IA32_REGS_SIZE + 4)), %edi\r
    movl    %edi, %ebx                  # ebx <- stack offset\r
    imul    $0x10, %edx, %eax\r
    push    $(IA32_REGS_SIZE / 4)\r
    addl    %eax, %edi                  # edi <- linear address of 16-bit stack\r
    pop     %ecx\r
    rep\r
    movsl                               # copy RegSet\r
    movl    40(%esp), %eax              # eax <- address of transition code\r
    movl    %edx, %esi                  # esi <- 16-bit stack segment\r
    lea     (SavedCr0 - ASM_PFX(m16Start))(%eax), %edx\r
    movl    %eax, %ecx\r
    andl    $0xf, %ecx\r
    shll    $12, %eax\r
    lea     (ASM_PFX(BackFromUserCode) - ASM_PFX(m16Start))(%ecx), %ecx\r
    movw    %cx, %ax\r
    stosl                               # [edi] <- return address of user code\r
    addl    $(L_Base - ASM_PFX(BackFromUserCode)), %eax\r
    movl    %eax, (L_Base - SavedCr0 - 4)(%edx)\r
    sgdtl   (SavedGdt - SavedCr0)(%edx)\r
    sidtl   0x24(%esp)\r
    movl    %cr0, %eax\r
    movl    %eax, (%edx)                # save CR0 in SavedCr0\r
    andl    $0x7ffffffe, %eax           # clear PE, PG bits\r
    movl    %cr4, %ebp\r
    mov     %ebp, (SavedCr4 - SavedCr0)(%edx)\r
    andl    $0xffffffcf, %ebp           # clear PAE, PSE bits\r
    pushl   $0x10\r
    pop     %ecx                        # ecx <- selector for data segments\r
    lgdtl   (_16Gdtr - SavedCr0)(%edx)\r
    pushfl\r
    lcall   *(_EntryPoint - SavedCr0)(%edx)\r
    popfl\r
    lidtl   0x24(%esp)\r
    lea     -IA32_REGS_SIZE(%ebp), %eax\r
    pop     %gs\r
    pop     %fs\r
    pop     %es\r
    pop     %ds\r
    pop     %edi\r
    pop     %esi\r
    pop     %ebx\r
    pop     %ebp\r
    ret\r
\r
    .const:\r
\r
ASM_PFX(m16Size):        .word      ASM_PFX(InternalAsmThunk16)  - ASM_PFX(m16Start)\r
ASM_PFX(mThunk16Attr):   .word      ASM_PFX(ThunkAttr)          - ASM_PFX(m16Start)\r
ASM_PFX(m16Gdt):         .word      _NullSegDesc        - ASM_PFX(m16Start)\r
ASM_PFX(m16GdtrBase):    .word      _16GdtrBase         - ASM_PFX(m16Start)\r
ASM_PFX(mTransition):    .word      _EntryPoint         - ASM_PFX(m16Start)\r
Commit	Line	Data
e1f414b6	1	#------------------------------------------------------------------------------\r
e1f414b6	2	#\r
48c8b6a2	3	# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>\r
bb817c56	4	# This program and the accompanying materials\r
e1f414b6	5	# are licensed and made available under the terms and conditions of the BSD License\r
e1f414b6	6	# which accompanies this distribution. The full text of the license may be found at\r
e4a34497	7	# http://opensource.org/licenses/bsd-license.php.\r
e1f414b6	8	#\r
	9	# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	10	# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	11	#\r
	12	# Module Name:\r
	13	#\r
	14	# Thunk16.S\r
	15	#\r
	16	# Abstract:\r
	17	#\r
	18	# Real mode thunk\r
	19	#\r
	20	#------------------------------------------------------------------------------\r
	21	\r
bff2467a	22	#include <Library/BaseLib.h>\r
bff2467a	23	\r
132f41f0	24	ASM_GLOBAL ASM_PFX(m16Start), ASM_PFX(m16Size), ASM_PFX(mThunk16Attr), ASM_PFX(m16Gdt), ASM_PFX(m16GdtrBase), ASM_PFX(mTransition)\r
132f41f0	25	ASM_GLOBAL ASM_PFX(InternalAsmThunk16)\r
e1f414b6	26	\r
321c89c2 DW	27	# define the structure of IA32_REGS\r
	28	.set _EDI, 0 #size 4\r
	29	.set _ESI, 4 #size 4\r
	30	.set _EBP, 8 #size 4\r
	31	.set _ESP, 12 #size 4\r
	32	.set _EBX, 16 #size 4\r
	33	.set _EDX, 20 #size 4\r
	34	.set _ECX, 24 #size 4\r
	35	.set _EAX, 28 #size 4\r
	36	.set _DS, 32 #size 2\r
	37	.set _ES, 34 #size 2\r
	38	.set _FS, 36 #size 2\r
	39	.set _GS, 38 #size 2\r
	40	.set _EFLAGS, 40 #size 4\r
	41	.set _EIP, 44 #size 4\r
	42	.set _CS, 48 #size 2\r
	43	.set _SS, 50 #size 2\r
	44	.set IA32_REGS_SIZE, 52\r
	45	\r
	46	.text\r
	47	.code16\r
	48	\r
e1f414b6	49	ASM_PFX(m16Start):\r
	50	\r
	51	SavedGdt: .space 6\r
	52	\r
	53	ASM_PFX(BackFromUserCode):\r
	54	push %ss\r
	55	push %cs\r
321c89c2 DW	56	\r
321c89c2 DW	57	calll L_Base1 # push eip\r
e1f414b6	58	L_Base1:\r
321c89c2	59	pushfl\r
e1f414b6	60	cli # disable interrupts\r
	61	push %gs\r
	62	push %fs\r
	63	push %es\r
	64	push %ds\r
321c89c2	65	pushal\r
e1f414b6	66	.byte 0x66, 0xba # mov edx, imm32\r
	67	ASM_PFX(ThunkAttr): .space 4\r
	68	testb $THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15, %dl\r
	69	jz 1f\r
321c89c2 DW	70	movw $0x2401, %ax\r
321c89c2 DW	71	int $0x15\r
e1f414b6	72	cli # disable interrupts\r
	73	jnc 2f\r
	74	1:\r
	75	testb $THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL, %dl\r
	76	jz 2f\r
	77	inb $0x92, %al\r
	78	orb $2, %al\r
	79	outb %al, $0x92 # deactivate A20M#\r
	80	2:\r
321c89c2 DW	81	xorl %eax, %eax\r
	82	movw %ss, %ax\r
	83	leal IA32_REGS_SIZE(%esp), %ebp\r
	84	mov %ebp, (_ESP - IA32_REGS_SIZE)(%bp)\r
	85	mov (_EIP - IA32_REGS_SIZE)(%bp), %bx\r
	86	shll $4, %eax\r
	87	addl %eax, %ebp\r
	88	.byte 0x66, 0xb8 # mov eax, imm32\r
e1f414b6	89	SavedCr4: .space 4\r
e1f414b6	90	movl %eax, %cr4\r
321c89c2 DW	91	lgdtl %cs:(SavedGdt - L_Base1)(%bx)\r
321c89c2 DW	92	.byte 0x66, 0xb8 # mov eax, imm32\r
e1f414b6	93	SavedCr0: .space 4\r
	94	movl %eax, %cr0\r
	95	.byte 0xb8 # mov ax, imm16\r
	96	SavedSs: .space 2\r
	97	movl %eax, %ss\r
321c89c2	98	.byte 0x66, 0xbc # mov esp, imm32\r
e1f414b6	99	SavedEsp: .space 4\r
321c89c2	100	lretl # return to protected mode\r
e1f414b6	101	\r
	102	_EntryPoint: .long ASM_PFX(ToUserCode) - ASM_PFX(m16Start)\r
	103	.word 0x8\r
	104	_16Idtr: .word 0x3ff\r
	105	.long 0\r
	106	_16Gdtr: .word GdtEnd - _NullSegDesc - 1\r
	107	_16GdtrBase: .long _NullSegDesc\r
	108	\r
	109	ASM_PFX(ToUserCode):\r
321c89c2 DW	110	movw %ss, %dx\r
	111	movw %cx, %ss # set new segment selectors\r
	112	movw %cx, %ds\r
	113	movw %cx, %es\r
	114	movw %cx, %fs\r
	115	movw %cx, %gs\r
af8aa62d DW	116	movl %eax, %cr0 # real mode starts at next instruction\r
	117	# which (per SDM) must be a far JMP.\r
	118	ljmpw $0,$0 # will be filled in by InternalAsmThunk16\r
	119	L_Base: # to point here.\r
	120	movl %ebp, %cr4\r
321c89c2 DW	121	movw %si, %ss # set up 16-bit stack segment\r
321c89c2 DW	122	xchgl %ebx, %esp # set up 16-bit stack pointer\r
e1f414b6	123	\r
af8aa62d DW	124	movw IA32_REGS_SIZE(%esp), %bp # get BackToUserCode address from stack\r
	125	mov %dx, %cs:(SavedSs - ASM_PFX(BackFromUserCode))(%bp)\r
	126	mov %ebx, %cs:(SavedEsp - ASM_PFX(BackFromUserCode))(%bp)\r
	127	lidtl %cs:(_16Idtr - ASM_PFX(BackFromUserCode))(%bp)\r
321c89c2	128	popal\r
e1f414b6	129	pop %ds\r
	130	pop %es\r
	131	pop %fs\r
	132	pop %gs\r
321c89c2 DW	133	popfl\r
321c89c2 DW	134	lretl # transfer control to user code\r
e1f414b6	135	\r
	136	_NullSegDesc: .quad 0\r
	137	_16CsDesc:\r
	138	.word -1\r
	139	.word 0\r
	140	.byte 0\r
	141	.byte 0x9b\r
	142	.byte 0x8f # 16-bit segment, 4GB limit\r
	143	.byte 0\r
	144	_16DsDesc:\r
	145	.word -1\r
	146	.word 0\r
	147	.byte 0\r
	148	.byte 0x93\r
	149	.byte 0x8f # 16-bit segment, 4GB limit\r
	150	.byte 0\r
	151	GdtEnd:\r
	152	\r
321c89c2	153	.code32\r
e1f414b6	154	#\r
2fc59a00	155	# @param RegSet The pointer to a IA32_DWORD_REGS structure\r
2fc59a00	156	# @param Transition The pointer to the transition code\r
e1f414b6	157	# @return The address of the 16-bit stack after returning from user code\r
	158	#\r
	159	ASM_PFX(InternalAsmThunk16):\r
	160	push %ebp\r
	161	push %ebx\r
	162	push %esi\r
	163	push %edi\r
	164	push %ds\r
	165	push %es\r
	166	push %fs\r
	167	push %gs\r
	168	movl 36(%esp), %esi # esi <- RegSet\r
321c89c2 DW	169	movzwl _SS(%esi), %edx\r
	170	mov _ESP(%esi), %edi\r
	171	add $(-(IA32_REGS_SIZE + 4)), %edi\r
e1f414b6	172	movl %edi, %ebx # ebx <- stack offset\r
e1f414b6	173	imul $0x10, %edx, %eax\r
321c89c2	174	push $(IA32_REGS_SIZE / 4)\r
e1f414b6	175	addl %eax, %edi # edi <- linear address of 16-bit stack\r
	176	pop %ecx\r
	177	rep\r
	178	movsl # copy RegSet\r
	179	movl 40(%esp), %eax # eax <- address of transition code\r
	180	movl %edx, %esi # esi <- 16-bit stack segment\r
321c89c2	181	lea (SavedCr0 - ASM_PFX(m16Start))(%eax), %edx\r
e1f414b6	182	movl %eax, %ecx\r
	183	andl $0xf, %ecx\r
	184	shll $12, %eax\r
321c89c2	185	lea (ASM_PFX(BackFromUserCode) - ASM_PFX(m16Start))(%ecx), %ecx\r
e1f414b6	186	movw %cx, %ax\r
e1f414b6	187	stosl # [edi] <- return address of user code\r
af8aa62d DW	188	addl $(L_Base - ASM_PFX(BackFromUserCode)), %eax\r
af8aa62d DW	189	movl %eax, (L_Base - SavedCr0 - 4)(%edx)\r
321c89c2	190	sgdtl (SavedGdt - SavedCr0)(%edx)\r
e1f414b6	191	sidtl 0x24(%esp)\r
	192	movl %cr0, %eax\r
	193	movl %eax, (%edx) # save CR0 in SavedCr0\r
	194	andl $0x7ffffffe, %eax # clear PE, PG bits\r
	195	movl %cr4, %ebp\r
321c89c2	196	mov %ebp, (SavedCr4 - SavedCr0)(%edx)\r
48c8b6a2	197	andl $0xffffffcf, %ebp # clear PAE, PSE bits\r
e1f414b6	198	pushl $0x10\r
e1f414b6	199	pop %ecx # ecx <- selector for data segments\r
321c89c2	200	lgdtl (_16Gdtr - SavedCr0)(%edx)\r
e1f414b6	201	pushfl\r
321c89c2	202	lcall *(_EntryPoint - SavedCr0)(%edx)\r
e1f414b6	203	popfl\r
e1f414b6	204	lidtl 0x24(%esp)\r
321c89c2	205	lea -IA32_REGS_SIZE(%ebp), %eax\r
6f890d5b	206	pop %gs\r
	207	pop %fs\r
	208	pop %es\r
	209	pop %ds\r
	210	pop %edi\r
	211	pop %esi\r
	212	pop %ebx\r
	213	pop %ebp\r
e1f414b6	214	ret\r
	215	\r
	216	.const:\r
	217	\r
6a8e44d9	218	ASM_PFX(m16Size): .word ASM_PFX(InternalAsmThunk16) - ASM_PFX(m16Start)\r
6a8e44d9	219	ASM_PFX(mThunk16Attr): .word ASM_PFX(ThunkAttr) - ASM_PFX(m16Start)\r
e1f414b6	220	ASM_PFX(m16Gdt): .word _NullSegDesc - ASM_PFX(m16Start)\r
	221	ASM_PFX(m16GdtrBase): .word _16GdtrBase - ASM_PFX(m16Start)\r
	222	ASM_PFX(mTransition): .word _EntryPoint - ASM_PFX(m16Start)\r