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878ddf1f | 1 | /** @file\r |
2 | Base Library CPU functions for Itanium\r | |
3 | \r | |
4 | Copyright (c) 2006, Intel Corporation<BR>\r | |
5 | All rights reserved. This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | //void __mfa (void);\r | |
16 | \r | |
17 | #pragma intrinsic (_enable)\r | |
18 | #pragma intrinsic (_disable)\r | |
19 | #pragma intrinsic (__break)\r | |
20 | #pragma intrinsic (__mfa)\r | |
21 | \r | |
4cbd2175 | 22 | typedef struct {\r |
23 | UINT64 Status;\r | |
24 | UINT64 r9;\r | |
25 | UINT64 r10;\r | |
26 | UINT64 r11;\r | |
27 | } PAL_PROC_RETURN;\r | |
28 | \r | |
29 | PAL_PROC_RETURN\r | |
30 | PalCallStatic (\r | |
31 | IN CONST VOID *PalEntryPoint,\r | |
32 | IN UINT64 Arg1,\r | |
33 | IN UINT64 Arg2,\r | |
34 | IN UINT64 Arg3,\r | |
35 | IN UINT64 Arg4\r | |
36 | );\r | |
37 | \r | |
878ddf1f | 38 | /**\r |
39 | Generates a breakpoint on the CPU.\r | |
40 | \r | |
41 | Generates a breakpoint on the CPU. The breakpoint must be implemented such\r | |
42 | that code can resume normal execution after the breakpoint.\r | |
43 | \r | |
44 | **/\r | |
45 | VOID\r | |
46 | EFIAPI\r | |
47 | CpuBreakpoint (\r | |
48 | VOID\r | |
49 | )\r | |
50 | {\r | |
51 | __break (0);\r | |
52 | }\r | |
53 | \r | |
54 | /**\r | |
55 | Used to serialize load and store operations.\r | |
56 | \r | |
57 | All loads and stores that proceed calls to this function are guaranteed to be\r | |
58 | globally visible when this function returns.\r | |
59 | \r | |
60 | **/\r | |
61 | VOID\r | |
62 | EFIAPI\r | |
63 | MemoryFence (\r | |
64 | VOID\r | |
65 | )\r | |
66 | {\r | |
67 | __mfa ();\r | |
68 | }\r | |
69 | \r | |
70 | /**\r | |
71 | Disables CPU interrupts.\r | |
72 | \r | |
73 | Disables CPU interrupts.\r | |
74 | \r | |
75 | **/\r | |
76 | VOID\r | |
77 | EFIAPI\r | |
78 | DisableInterrupts (\r | |
79 | VOID\r | |
80 | )\r | |
81 | {\r | |
82 | _disable ();\r | |
83 | }\r | |
84 | \r | |
85 | /**\r | |
86 | Enables CPU interrupts.\r | |
87 | \r | |
88 | Enables CPU interrupts.\r | |
89 | \r | |
90 | **/\r | |
91 | VOID\r | |
92 | EFIAPI\r | |
93 | EnableInterrupts (\r | |
94 | VOID\r | |
95 | )\r | |
96 | {\r | |
97 | _enable ();\r | |
98 | }\r | |
99 | \r | |
97d92bda | 100 | /**\r |
101 | Enables CPU interrupts for the smallest window required to capture any\r | |
102 | pending interrupts.\r | |
103 | \r | |
104 | Enables CPU interrupts for the smallest window required to capture any\r | |
105 | pending interrupts.\r | |
106 | \r | |
107 | **/\r | |
108 | VOID\r | |
109 | EFIAPI\r | |
110 | EnableDisableInterrupts (\r | |
111 | VOID\r | |
112 | )\r | |
113 | {\r | |
114 | EnableInterrupts ();\r | |
115 | DisableInterrupts ();\r | |
116 | }\r | |
4cbd2175 | 117 | \r |
118 | /**\r | |
119 | Places the CPU in a sleep state until an interrupt is received.\r | |
120 | \r | |
121 | Places the CPU in a sleep state until an interrupt is received. If interrupts\r | |
122 | are disabled prior to calling this function, then the CPU will be placed in a\r | |
123 | sleep state indefinitely.\r | |
124 | \r | |
125 | **/\r | |
126 | VOID\r | |
127 | EFIAPI\r | |
128 | CpuSleep (\r | |
129 | VOID\r | |
130 | )\r | |
131 | {\r | |
132 | PalCallStatic (NULL, 29, 0, 0, 0);\r | |
133 | }\r |