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f1baef62 | 1 | //++\r |
2 | // Copyright (c) 2006, Intel Corporation \r | |
3 | // All rights reserved. This program and the accompanying materials \r | |
4 | // are licensed and made available under the terms and conditions of the BSD License \r | |
5 | // which accompanies this distribution. The full text of the license may be found at \r | |
6 | // http://opensource.org/licenses/bsd-license.php \r | |
7 | // \r | |
8 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
9 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
10 | // \r | |
11 | // Module Name:\r | |
12 | // FlushCacheRange.s \r | |
13 | //\r | |
14 | // Abstract:\r | |
15 | // Assemble routine to flush cache lines \r | |
16 | //\r | |
17 | // Revision History:\r | |
18 | //\r | |
19 | //--\r | |
20 | .file "IpfCpuCache.s"\r | |
21 | \r | |
22 | #include "IpfMacro.i"\r | |
23 | //#include "IpfDefines.h"\r | |
24 | \r | |
25 | //\r | |
26 | // Invalidates a range of instruction cache lines in the cache coherency domain\r | |
27 | // of the calling CPU.\r | |
28 | //\r | |
29 | // Invalidates the instruction cache lines specified by Address and Length. If\r | |
30 | // Address is not aligned on a cache line boundary, then entire instruction\r | |
31 | // cache line containing Address is invalidated. If Address + Length is not\r | |
32 | // aligned on a cache line boundary, then the entire instruction cache line\r | |
33 | // containing Address + Length -1 is invalidated. This function may choose to\r | |
34 | // invalidate the entire instruction cache if that is more efficient than\r | |
35 | // invalidating the specified range. If Length is 0, the no instruction cache\r | |
36 | // lines are invalidated. Address is returned.\r | |
37 | //\r | |
38 | // If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
39 | //\r | |
40 | // @param Address The base address of the instruction cache lines to\r | |
41 | // invalidate. If the CPU is in a physical addressing mode, then\r | |
42 | // Address is a physical address. If the CPU is in a virtual\r | |
43 | // addressing mode, then Address is a virtual address.\r | |
44 | //\r | |
45 | // @param Length The number of bytes to invalidate from the instruction cache.\r | |
46 | //\r | |
47 | // @return Address\r | |
48 | // \r | |
49 | // VOID *\r | |
50 | // EFIAPI\r | |
51 | // IpfFlushCacheRange (\r | |
52 | // IN VOID *Address,\r | |
53 | // IN UINTN Length\r | |
54 | // );\r | |
55 | //\r | |
56 | PROCEDURE_ENTRY (IpfFlushCacheRange)\r | |
57 | \r | |
58 | NESTED_SETUP (5,8,0,0)\r | |
59 | \r | |
60 | mov loc2 = ar.lc\r | |
61 | \r | |
62 | mov loc3 = in0 // Start address.\r | |
63 | mov loc4 = in1;; // Length in bytes.\r | |
64 | \r | |
65 | cmp.eq p6,p7 = loc4, r0;; // If Length is zero then don't flush any cache\r | |
66 | (p6) br.spnt.many DoneFlushingC;; \r | |
67 | \r | |
68 | add loc4 = loc4,loc3 \r | |
69 | mov loc5 = 1;;\r | |
70 | sub loc4 = loc4, loc5 ;; // the End address to flush\r | |
71 | \r | |
72 | dep loc3 = r0,loc3,0,5 \r | |
73 | dep loc4 = r0,loc4,0,5;; \r | |
74 | shr loc3 = loc3,5 \r | |
75 | shr loc4 = loc4,5;; // 32 byte cache line\r | |
76 | \r | |
77 | sub loc4 = loc4,loc3;; // total flush count, It should be add 1 but \r | |
78 | // the br.cloop will first execute one time \r | |
79 | mov loc3 = in0 \r | |
80 | mov loc5 = 32 \r | |
81 | mov ar.lc = loc4;;\r | |
82 | \r | |
83 | StillFlushingC:\r | |
84 | fc loc3;; \r | |
85 | sync.i;;\r | |
86 | srlz.i;;\r | |
87 | add loc3 = loc5,loc3;;\r | |
88 | br.cloop.sptk.few StillFlushingC;;\r | |
89 | \r | |
90 | DoneFlushingC: \r | |
91 | mov ar.lc = loc2 \r | |
92 | mov r8 = in0 // return *Address\r | |
93 | NESTED_RETURN\r | |
94 | \r | |
95 | PROCEDURE_EXIT (IpfFlushCacheRange)\r | |
96 | \r |