]>
Commit | Line | Data |
---|---|---|
e1f414b6 | 1 | /** @file\r |
5c57f3ea | 2 | PCI Library functions that use the 256 MB PCI Express MMIO window to perform PCI\r |
3 | Configuration cycles. Layers on PCI Express Library.\r | |
e1f414b6 | 4 | \r |
9095d37b | 5 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r |
9344f092 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
e1f414b6 | 7 | \r |
e1f414b6 | 8 | **/\r |
9 | \r | |
c892d846 | 10 | \r |
c7d265a9 | 11 | #include <Base.h>\r |
c892d846 | 12 | \r |
c7d265a9 | 13 | #include <Library/PciLib.h>\r |
14 | #include <Library/PciExpressLib.h>\r | |
e1f414b6 | 15 | \r |
3e3ae634 | 16 | /**\r |
9095d37b | 17 | Registers a PCI device so PCI configuration registers may be accessed after\r |
3e3ae634 | 18 | SetVirtualAddressMap().\r |
9095d37b LG |
19 | \r |
20 | Registers the PCI device specified by Address so all the PCI configuration registers\r | |
d11195a3 | 21 | associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r |
9095d37b | 22 | \r |
3e3ae634 | 23 | If Address > 0x0FFFFFFF, then ASSERT().\r |
24 | \r | |
2fc59a00 | 25 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
3e3ae634 | 26 | Register.\r |
9095d37b | 27 | \r |
3e3ae634 | 28 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r |
9095d37b | 29 | @retval RETURN_UNSUPPORTED An attempt was made to call this function\r |
3e3ae634 | 30 | after ExitBootServices().\r |
31 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
32 | at runtime could not be mapped.\r | |
33 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
34 | complete the registration.\r | |
35 | \r | |
36 | **/\r | |
37 | RETURN_STATUS\r | |
38 | EFIAPI\r | |
39 | PciRegisterForRuntimeAccess (\r | |
40 | IN UINTN Address\r | |
41 | )\r | |
42 | {\r | |
43 | return PciExpressRegisterForRuntimeAccess (Address);\r | |
44 | }\r | |
45 | \r | |
e1f414b6 | 46 | /**\r |
47 | Reads an 8-bit PCI configuration register.\r | |
48 | \r | |
49 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
50 | This function must guarantee that all PCI read and write operations are\r | |
51 | serialized.\r | |
52 | \r | |
53 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
54 | \r | |
2fc59a00 | 55 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 56 | Register.\r |
57 | \r | |
58 | @return The read value from the PCI configuration register.\r | |
59 | \r | |
60 | **/\r | |
61 | UINT8\r | |
62 | EFIAPI\r | |
63 | PciRead8 (\r | |
64 | IN UINTN Address\r | |
65 | )\r | |
66 | {\r | |
67 | return PciExpressRead8 (Address);\r | |
68 | }\r | |
69 | \r | |
70 | /**\r | |
71 | Writes an 8-bit PCI configuration register.\r | |
72 | \r | |
73 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
74 | value specified by Value. Value is returned. This function must guarantee\r | |
75 | that all PCI read and write operations are serialized.\r | |
76 | \r | |
77 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
78 | \r | |
2fc59a00 | 79 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 80 | Register.\r |
7612cbf0 | 81 | @param Value The value to write.\r |
e1f414b6 | 82 | \r |
83 | @return The value written to the PCI configuration register.\r | |
84 | \r | |
85 | **/\r | |
86 | UINT8\r | |
87 | EFIAPI\r | |
88 | PciWrite8 (\r | |
89 | IN UINTN Address,\r | |
94646ec0 | 90 | IN UINT8 Value\r |
e1f414b6 | 91 | )\r |
92 | {\r | |
94646ec0 | 93 | return PciExpressWrite8 (Address, Value);\r |
e1f414b6 | 94 | }\r |
95 | \r | |
96 | /**\r | |
62991af2 | 97 | Performs a bitwise OR of an 8-bit PCI configuration register with\r |
e1f414b6 | 98 | an 8-bit value.\r |
99 | \r | |
100 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 101 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 102 | OrData, and writes the result to the 8-bit PCI configuration register\r |
103 | specified by Address. The value written to the PCI configuration register is\r | |
104 | returned. This function must guarantee that all PCI read and write operations\r | |
105 | are serialized.\r | |
106 | \r | |
107 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
108 | \r | |
2fc59a00 | 109 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 110 | Register.\r |
111 | @param OrData The value to OR with the PCI configuration register.\r | |
112 | \r | |
113 | @return The value written back to the PCI configuration register.\r | |
114 | \r | |
115 | **/\r | |
116 | UINT8\r | |
117 | EFIAPI\r | |
118 | PciOr8 (\r | |
119 | IN UINTN Address,\r | |
120 | IN UINT8 OrData\r | |
121 | )\r | |
122 | {\r | |
123 | return PciExpressOr8 (Address, OrData);\r | |
124 | }\r | |
125 | \r | |
126 | /**\r | |
127 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
128 | value.\r | |
129 | \r | |
130 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
131 | bitwise AND between the read result and the value specified by AndData, and\r | |
132 | writes the result to the 8-bit PCI configuration register specified by\r | |
133 | Address. The value written to the PCI configuration register is returned.\r | |
134 | This function must guarantee that all PCI read and write operations are\r | |
135 | serialized.\r | |
136 | \r | |
137 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
138 | \r | |
2fc59a00 | 139 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 140 | Register.\r |
141 | @param AndData The value to AND with the PCI configuration register.\r | |
142 | \r | |
143 | @return The value written back to the PCI configuration register.\r | |
144 | \r | |
145 | **/\r | |
146 | UINT8\r | |
147 | EFIAPI\r | |
148 | PciAnd8 (\r | |
149 | IN UINTN Address,\r | |
150 | IN UINT8 AndData\r | |
151 | )\r | |
152 | {\r | |
153 | return PciExpressAnd8 (Address, AndData);\r | |
154 | }\r | |
155 | \r | |
156 | /**\r | |
157 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
62991af2 | 158 | value, followed a bitwise OR with another 8-bit value.\r |
e1f414b6 | 159 | \r |
160 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
161 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 162 | performs a bitwise OR between the result of the AND operation and\r |
e1f414b6 | 163 | the value specified by OrData, and writes the result to the 8-bit PCI\r |
164 | configuration register specified by Address. The value written to the PCI\r | |
165 | configuration register is returned. This function must guarantee that all PCI\r | |
166 | read and write operations are serialized.\r | |
167 | \r | |
168 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
169 | \r | |
2fc59a00 | 170 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 171 | Register.\r |
172 | @param AndData The value to AND with the PCI configuration register.\r | |
173 | @param OrData The value to OR with the result of the AND operation.\r | |
174 | \r | |
175 | @return The value written back to the PCI configuration register.\r | |
176 | \r | |
177 | **/\r | |
178 | UINT8\r | |
179 | EFIAPI\r | |
180 | PciAndThenOr8 (\r | |
181 | IN UINTN Address,\r | |
182 | IN UINT8 AndData,\r | |
183 | IN UINT8 OrData\r | |
184 | )\r | |
185 | {\r | |
186 | return PciExpressAndThenOr8 (Address, AndData, OrData);\r | |
187 | }\r | |
188 | \r | |
189 | /**\r | |
190 | Reads a bit field of a PCI configuration register.\r | |
191 | \r | |
192 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
193 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
194 | returned.\r | |
195 | \r | |
196 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
197 | If StartBit is greater than 7, then ASSERT().\r | |
198 | If EndBit is greater than 7, then ASSERT().\r | |
199 | If EndBit is less than StartBit, then ASSERT().\r | |
200 | \r | |
2fc59a00 | 201 | @param Address The PCI configuration register to read.\r |
e1f414b6 | 202 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
203 | Range 0..7.\r | |
204 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
205 | Range 0..7.\r | |
206 | \r | |
207 | @return The value of the bit field read from the PCI configuration register.\r | |
208 | \r | |
209 | **/\r | |
210 | UINT8\r | |
211 | EFIAPI\r | |
212 | PciBitFieldRead8 (\r | |
213 | IN UINTN Address,\r | |
214 | IN UINTN StartBit,\r | |
215 | IN UINTN EndBit\r | |
216 | )\r | |
217 | {\r | |
218 | return PciExpressBitFieldRead8 (Address, StartBit, EndBit);\r | |
219 | }\r | |
220 | \r | |
221 | /**\r | |
222 | Writes a bit field to a PCI configuration register.\r | |
223 | \r | |
224 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
225 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
226 | destination PCI configuration register are preserved. The new value of the\r | |
227 | 8-bit register is returned.\r | |
228 | \r | |
229 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
230 | If StartBit is greater than 7, then ASSERT().\r | |
231 | If EndBit is greater than 7, then ASSERT().\r | |
232 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 233 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 234 | \r |
2fc59a00 | 235 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 236 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
237 | Range 0..7.\r | |
238 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
239 | Range 0..7.\r | |
2fc59a00 | 240 | @param Value The new value of the bit field.\r |
e1f414b6 | 241 | \r |
242 | @return The value written back to the PCI configuration register.\r | |
243 | \r | |
244 | **/\r | |
245 | UINT8\r | |
246 | EFIAPI\r | |
247 | PciBitFieldWrite8 (\r | |
248 | IN UINTN Address,\r | |
249 | IN UINTN StartBit,\r | |
250 | IN UINTN EndBit,\r | |
251 | IN UINT8 Value\r | |
252 | )\r | |
253 | {\r | |
254 | return PciExpressBitFieldWrite8 (Address, StartBit, EndBit, Value);\r | |
255 | }\r | |
256 | \r | |
257 | /**\r | |
258 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
259 | writes the result back to the bit field in the 8-bit port.\r | |
260 | \r | |
261 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 262 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 263 | OrData, and writes the result to the 8-bit PCI configuration register\r |
264 | specified by Address. The value written to the PCI configuration register is\r | |
265 | returned. This function must guarantee that all PCI read and write operations\r | |
266 | are serialized. Extra left bits in OrData are stripped.\r | |
267 | \r | |
268 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
269 | If StartBit is greater than 7, then ASSERT().\r | |
270 | If EndBit is greater than 7, then ASSERT().\r | |
271 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 272 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 273 | \r |
2fc59a00 | 274 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 275 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
276 | Range 0..7.\r | |
277 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
278 | Range 0..7.\r | |
279 | @param OrData The value to OR with the PCI configuration register.\r | |
280 | \r | |
281 | @return The value written back to the PCI configuration register.\r | |
282 | \r | |
283 | **/\r | |
284 | UINT8\r | |
285 | EFIAPI\r | |
286 | PciBitFieldOr8 (\r | |
287 | IN UINTN Address,\r | |
288 | IN UINTN StartBit,\r | |
289 | IN UINTN EndBit,\r | |
290 | IN UINT8 OrData\r | |
291 | )\r | |
292 | {\r | |
293 | return PciExpressBitFieldOr8 (Address, StartBit, EndBit, OrData);\r | |
294 | }\r | |
295 | \r | |
296 | /**\r | |
297 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
298 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
299 | \r | |
300 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
301 | bitwise AND between the read result and the value specified by AndData, and\r | |
302 | writes the result to the 8-bit PCI configuration register specified by\r | |
303 | Address. The value written to the PCI configuration register is returned.\r | |
304 | This function must guarantee that all PCI read and write operations are\r | |
305 | serialized. Extra left bits in AndData are stripped.\r | |
306 | \r | |
307 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
308 | If StartBit is greater than 7, then ASSERT().\r | |
309 | If EndBit is greater than 7, then ASSERT().\r | |
310 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 311 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 312 | \r |
2fc59a00 | 313 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 314 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
315 | Range 0..7.\r | |
316 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
317 | Range 0..7.\r | |
318 | @param AndData The value to AND with the PCI configuration register.\r | |
319 | \r | |
320 | @return The value written back to the PCI configuration register.\r | |
321 | \r | |
322 | **/\r | |
323 | UINT8\r | |
324 | EFIAPI\r | |
325 | PciBitFieldAnd8 (\r | |
326 | IN UINTN Address,\r | |
327 | IN UINTN StartBit,\r | |
328 | IN UINTN EndBit,\r | |
329 | IN UINT8 AndData\r | |
330 | )\r | |
331 | {\r | |
332 | return PciExpressBitFieldAnd8 (Address, StartBit, EndBit, AndData);\r | |
333 | }\r | |
334 | \r | |
335 | /**\r | |
336 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 337 | bitwise OR, and writes the result back to the bit field in the\r |
e1f414b6 | 338 | 8-bit port.\r |
339 | \r | |
340 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 341 | bitwise AND followed by a bitwise OR between the read result and\r |
e1f414b6 | 342 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
343 | configuration register specified by Address. The value written to the PCI\r | |
344 | configuration register is returned. This function must guarantee that all PCI\r | |
345 | read and write operations are serialized. Extra left bits in both AndData and\r | |
346 | OrData are stripped.\r | |
347 | \r | |
348 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
349 | If StartBit is greater than 7, then ASSERT().\r | |
350 | If EndBit is greater than 7, then ASSERT().\r | |
351 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
352 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
353 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
e1f414b6 | 354 | \r |
2fc59a00 | 355 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 356 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
357 | Range 0..7.\r | |
358 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
359 | Range 0..7.\r | |
360 | @param AndData The value to AND with the PCI configuration register.\r | |
361 | @param OrData The value to OR with the result of the AND operation.\r | |
362 | \r | |
363 | @return The value written back to the PCI configuration register.\r | |
364 | \r | |
365 | **/\r | |
366 | UINT8\r | |
367 | EFIAPI\r | |
368 | PciBitFieldAndThenOr8 (\r | |
369 | IN UINTN Address,\r | |
370 | IN UINTN StartBit,\r | |
371 | IN UINTN EndBit,\r | |
372 | IN UINT8 AndData,\r | |
373 | IN UINT8 OrData\r | |
374 | )\r | |
375 | {\r | |
376 | return PciExpressBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData);\r | |
377 | }\r | |
378 | \r | |
379 | /**\r | |
380 | Reads a 16-bit PCI configuration register.\r | |
381 | \r | |
382 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
383 | This function must guarantee that all PCI read and write operations are\r | |
384 | serialized.\r | |
385 | \r | |
386 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 387 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 388 | \r |
2fc59a00 | 389 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 390 | Register.\r |
391 | \r | |
392 | @return The read value from the PCI configuration register.\r | |
393 | \r | |
394 | **/\r | |
395 | UINT16\r | |
396 | EFIAPI\r | |
397 | PciRead16 (\r | |
398 | IN UINTN Address\r | |
399 | )\r | |
400 | {\r | |
401 | return PciExpressRead16 (Address);\r | |
402 | }\r | |
403 | \r | |
404 | /**\r | |
405 | Writes a 16-bit PCI configuration register.\r | |
406 | \r | |
407 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
408 | value specified by Value. Value is returned. This function must guarantee\r | |
409 | that all PCI read and write operations are serialized.\r | |
410 | \r | |
411 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 412 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 413 | \r |
2fc59a00 | 414 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 415 | Register.\r |
9638ba6d | 416 | @param Value The value to write.\r |
e1f414b6 | 417 | \r |
418 | @return The value written to the PCI configuration register.\r | |
419 | \r | |
420 | **/\r | |
421 | UINT16\r | |
422 | EFIAPI\r | |
423 | PciWrite16 (\r | |
424 | IN UINTN Address,\r | |
94646ec0 | 425 | IN UINT16 Value\r |
e1f414b6 | 426 | )\r |
427 | {\r | |
94646ec0 | 428 | return PciExpressWrite16 (Address, Value);\r |
e1f414b6 | 429 | }\r |
430 | \r | |
431 | /**\r | |
62991af2 | 432 | Performs a bitwise OR of a 16-bit PCI configuration register with\r |
e1f414b6 | 433 | a 16-bit value.\r |
434 | \r | |
435 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 436 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 437 | OrData, and writes the result to the 16-bit PCI configuration register\r |
438 | specified by Address. The value written to the PCI configuration register is\r | |
439 | returned. This function must guarantee that all PCI read and write operations\r | |
440 | are serialized.\r | |
441 | \r | |
442 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 443 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 444 | \r |
2fc59a00 | 445 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 446 | Register.\r |
447 | @param OrData The value to OR with the PCI configuration register.\r | |
448 | \r | |
449 | @return The value written back to the PCI configuration register.\r | |
450 | \r | |
451 | **/\r | |
452 | UINT16\r | |
453 | EFIAPI\r | |
454 | PciOr16 (\r | |
455 | IN UINTN Address,\r | |
456 | IN UINT16 OrData\r | |
457 | )\r | |
458 | {\r | |
459 | return PciExpressOr16 (Address, OrData);\r | |
460 | }\r | |
461 | \r | |
462 | /**\r | |
463 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
464 | value.\r | |
465 | \r | |
466 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
467 | bitwise AND between the read result and the value specified by AndData, and\r | |
468 | writes the result to the 16-bit PCI configuration register specified by\r | |
469 | Address. The value written to the PCI configuration register is returned.\r | |
470 | This function must guarantee that all PCI read and write operations are\r | |
471 | serialized.\r | |
472 | \r | |
473 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 474 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 475 | \r |
2fc59a00 | 476 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 477 | Register.\r |
478 | @param AndData The value to AND with the PCI configuration register.\r | |
479 | \r | |
480 | @return The value written back to the PCI configuration register.\r | |
481 | \r | |
482 | **/\r | |
483 | UINT16\r | |
484 | EFIAPI\r | |
485 | PciAnd16 (\r | |
486 | IN UINTN Address,\r | |
487 | IN UINT16 AndData\r | |
488 | )\r | |
489 | {\r | |
490 | return PciExpressAnd16 (Address, AndData);\r | |
491 | }\r | |
492 | \r | |
493 | /**\r | |
494 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
62991af2 | 495 | value, followed a bitwise OR with another 16-bit value.\r |
e1f414b6 | 496 | \r |
497 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
498 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 499 | performs a bitwise OR between the result of the AND operation and\r |
e1f414b6 | 500 | the value specified by OrData, and writes the result to the 16-bit PCI\r |
501 | configuration register specified by Address. The value written to the PCI\r | |
502 | configuration register is returned. This function must guarantee that all PCI\r | |
503 | read and write operations are serialized.\r | |
504 | \r | |
505 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 506 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 507 | \r |
2fc59a00 | 508 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 509 | Register.\r |
510 | @param AndData The value to AND with the PCI configuration register.\r | |
511 | @param OrData The value to OR with the result of the AND operation.\r | |
512 | \r | |
513 | @return The value written back to the PCI configuration register.\r | |
514 | \r | |
515 | **/\r | |
516 | UINT16\r | |
517 | EFIAPI\r | |
518 | PciAndThenOr16 (\r | |
519 | IN UINTN Address,\r | |
520 | IN UINT16 AndData,\r | |
521 | IN UINT16 OrData\r | |
522 | )\r | |
523 | {\r | |
524 | return PciExpressAndThenOr16 (Address, AndData, OrData);\r | |
525 | }\r | |
526 | \r | |
527 | /**\r | |
528 | Reads a bit field of a PCI configuration register.\r | |
529 | \r | |
530 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
531 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
532 | returned.\r | |
533 | \r | |
534 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 535 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 536 | If StartBit is greater than 15, then ASSERT().\r |
537 | If EndBit is greater than 15, then ASSERT().\r | |
538 | If EndBit is less than StartBit, then ASSERT().\r | |
539 | \r | |
2fc59a00 | 540 | @param Address The PCI configuration register to read.\r |
e1f414b6 | 541 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
542 | Range 0..15.\r | |
543 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
544 | Range 0..15.\r | |
545 | \r | |
546 | @return The value of the bit field read from the PCI configuration register.\r | |
547 | \r | |
548 | **/\r | |
549 | UINT16\r | |
550 | EFIAPI\r | |
551 | PciBitFieldRead16 (\r | |
552 | IN UINTN Address,\r | |
553 | IN UINTN StartBit,\r | |
554 | IN UINTN EndBit\r | |
555 | )\r | |
556 | {\r | |
557 | return PciExpressBitFieldRead16 (Address, StartBit, EndBit);\r | |
558 | }\r | |
559 | \r | |
560 | /**\r | |
561 | Writes a bit field to a PCI configuration register.\r | |
562 | \r | |
563 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
564 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
565 | destination PCI configuration register are preserved. The new value of the\r | |
566 | 16-bit register is returned.\r | |
567 | \r | |
568 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 569 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 570 | If StartBit is greater than 15, then ASSERT().\r |
571 | If EndBit is greater than 15, then ASSERT().\r | |
572 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 573 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 574 | \r |
2fc59a00 | 575 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 576 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
577 | Range 0..15.\r | |
578 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
579 | Range 0..15.\r | |
2fc59a00 | 580 | @param Value The new value of the bit field.\r |
e1f414b6 | 581 | \r |
582 | @return The value written back to the PCI configuration register.\r | |
583 | \r | |
584 | **/\r | |
585 | UINT16\r | |
586 | EFIAPI\r | |
587 | PciBitFieldWrite16 (\r | |
588 | IN UINTN Address,\r | |
589 | IN UINTN StartBit,\r | |
590 | IN UINTN EndBit,\r | |
591 | IN UINT16 Value\r | |
592 | )\r | |
593 | {\r | |
594 | return PciExpressBitFieldWrite16 (Address, StartBit, EndBit, Value);\r | |
595 | }\r | |
596 | \r | |
597 | /**\r | |
598 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
599 | writes the result back to the bit field in the 16-bit port.\r | |
600 | \r | |
601 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 602 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 603 | OrData, and writes the result to the 16-bit PCI configuration register\r |
604 | specified by Address. The value written to the PCI configuration register is\r | |
605 | returned. This function must guarantee that all PCI read and write operations\r | |
606 | are serialized. Extra left bits in OrData are stripped.\r | |
607 | \r | |
608 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 609 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 610 | If StartBit is greater than 15, then ASSERT().\r |
611 | If EndBit is greater than 15, then ASSERT().\r | |
612 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 613 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 614 | \r |
2fc59a00 | 615 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 616 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
617 | Range 0..15.\r | |
618 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
619 | Range 0..15.\r | |
620 | @param OrData The value to OR with the PCI configuration register.\r | |
621 | \r | |
622 | @return The value written back to the PCI configuration register.\r | |
623 | \r | |
624 | **/\r | |
625 | UINT16\r | |
626 | EFIAPI\r | |
627 | PciBitFieldOr16 (\r | |
628 | IN UINTN Address,\r | |
629 | IN UINTN StartBit,\r | |
630 | IN UINTN EndBit,\r | |
631 | IN UINT16 OrData\r | |
632 | )\r | |
633 | {\r | |
634 | return PciExpressBitFieldOr16 (Address, StartBit, EndBit, OrData);\r | |
635 | }\r | |
636 | \r | |
637 | /**\r | |
638 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
639 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
640 | \r | |
641 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
642 | bitwise AND between the read result and the value specified by AndData, and\r | |
643 | writes the result to the 16-bit PCI configuration register specified by\r | |
644 | Address. The value written to the PCI configuration register is returned.\r | |
645 | This function must guarantee that all PCI read and write operations are\r | |
646 | serialized. Extra left bits in AndData are stripped.\r | |
647 | \r | |
648 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 649 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 650 | If StartBit is greater than 15, then ASSERT().\r |
651 | If EndBit is greater than 15, then ASSERT().\r | |
652 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 653 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 654 | \r |
2fc59a00 | 655 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 656 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
657 | Range 0..15.\r | |
658 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
659 | Range 0..15.\r | |
660 | @param AndData The value to AND with the PCI configuration register.\r | |
661 | \r | |
662 | @return The value written back to the PCI configuration register.\r | |
663 | \r | |
664 | **/\r | |
665 | UINT16\r | |
666 | EFIAPI\r | |
667 | PciBitFieldAnd16 (\r | |
668 | IN UINTN Address,\r | |
669 | IN UINTN StartBit,\r | |
670 | IN UINTN EndBit,\r | |
671 | IN UINT16 AndData\r | |
672 | )\r | |
673 | {\r | |
674 | return PciExpressBitFieldAnd16 (Address, StartBit, EndBit, AndData);\r | |
675 | }\r | |
676 | \r | |
677 | /**\r | |
678 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 679 | bitwise OR, and writes the result back to the bit field in the\r |
e1f414b6 | 680 | 16-bit port.\r |
681 | \r | |
682 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 683 | bitwise AND followed by a bitwise OR between the read result and\r |
e1f414b6 | 684 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
685 | configuration register specified by Address. The value written to the PCI\r | |
686 | configuration register is returned. This function must guarantee that all PCI\r | |
687 | read and write operations are serialized. Extra left bits in both AndData and\r | |
688 | OrData are stripped.\r | |
689 | \r | |
690 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 691 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 692 | If StartBit is greater than 15, then ASSERT().\r |
693 | If EndBit is greater than 15, then ASSERT().\r | |
694 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
695 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
696 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
e1f414b6 | 697 | \r |
2fc59a00 | 698 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 699 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
700 | Range 0..15.\r | |
701 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
702 | Range 0..15.\r | |
703 | @param AndData The value to AND with the PCI configuration register.\r | |
704 | @param OrData The value to OR with the result of the AND operation.\r | |
705 | \r | |
706 | @return The value written back to the PCI configuration register.\r | |
707 | \r | |
708 | **/\r | |
709 | UINT16\r | |
710 | EFIAPI\r | |
711 | PciBitFieldAndThenOr16 (\r | |
712 | IN UINTN Address,\r | |
713 | IN UINTN StartBit,\r | |
714 | IN UINTN EndBit,\r | |
715 | IN UINT16 AndData,\r | |
716 | IN UINT16 OrData\r | |
717 | )\r | |
718 | {\r | |
719 | return PciExpressBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData);\r | |
720 | }\r | |
721 | \r | |
722 | /**\r | |
723 | Reads a 32-bit PCI configuration register.\r | |
724 | \r | |
725 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
726 | This function must guarantee that all PCI read and write operations are\r | |
727 | serialized.\r | |
728 | \r | |
729 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 730 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 731 | \r |
2fc59a00 | 732 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 733 | Register.\r |
734 | \r | |
735 | @return The read value from the PCI configuration register.\r | |
736 | \r | |
737 | **/\r | |
738 | UINT32\r | |
739 | EFIAPI\r | |
740 | PciRead32 (\r | |
741 | IN UINTN Address\r | |
742 | )\r | |
743 | {\r | |
744 | return PciExpressRead32 (Address);\r | |
745 | }\r | |
746 | \r | |
747 | /**\r | |
748 | Writes a 32-bit PCI configuration register.\r | |
749 | \r | |
750 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
751 | value specified by Value. Value is returned. This function must guarantee\r | |
752 | that all PCI read and write operations are serialized.\r | |
753 | \r | |
754 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 755 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 756 | \r |
2fc59a00 | 757 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 758 | Register.\r |
7612cbf0 | 759 | @param Value The value to write.\r |
e1f414b6 | 760 | \r |
761 | @return The value written to the PCI configuration register.\r | |
762 | \r | |
763 | **/\r | |
764 | UINT32\r | |
765 | EFIAPI\r | |
766 | PciWrite32 (\r | |
767 | IN UINTN Address,\r | |
94646ec0 | 768 | IN UINT32 Value\r |
e1f414b6 | 769 | )\r |
770 | {\r | |
94646ec0 | 771 | return PciExpressWrite32 (Address, Value);\r |
e1f414b6 | 772 | }\r |
773 | \r | |
774 | /**\r | |
62991af2 | 775 | Performs a bitwise OR of a 32-bit PCI configuration register with\r |
e1f414b6 | 776 | a 32-bit value.\r |
777 | \r | |
778 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 779 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 780 | OrData, and writes the result to the 32-bit PCI configuration register\r |
781 | specified by Address. The value written to the PCI configuration register is\r | |
782 | returned. This function must guarantee that all PCI read and write operations\r | |
783 | are serialized.\r | |
784 | \r | |
785 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 786 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 787 | \r |
2fc59a00 | 788 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 789 | Register.\r |
790 | @param OrData The value to OR with the PCI configuration register.\r | |
791 | \r | |
792 | @return The value written back to the PCI configuration register.\r | |
793 | \r | |
794 | **/\r | |
795 | UINT32\r | |
796 | EFIAPI\r | |
797 | PciOr32 (\r | |
798 | IN UINTN Address,\r | |
799 | IN UINT32 OrData\r | |
800 | )\r | |
801 | {\r | |
802 | return PciExpressOr32 (Address, OrData);\r | |
803 | }\r | |
804 | \r | |
805 | /**\r | |
806 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
807 | value.\r | |
808 | \r | |
809 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
810 | bitwise AND between the read result and the value specified by AndData, and\r | |
811 | writes the result to the 32-bit PCI configuration register specified by\r | |
812 | Address. The value written to the PCI configuration register is returned.\r | |
813 | This function must guarantee that all PCI read and write operations are\r | |
814 | serialized.\r | |
815 | \r | |
816 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 817 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 818 | \r |
2fc59a00 | 819 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 820 | Register.\r |
821 | @param AndData The value to AND with the PCI configuration register.\r | |
822 | \r | |
823 | @return The value written back to the PCI configuration register.\r | |
824 | \r | |
825 | **/\r | |
826 | UINT32\r | |
827 | EFIAPI\r | |
828 | PciAnd32 (\r | |
829 | IN UINTN Address,\r | |
830 | IN UINT32 AndData\r | |
831 | )\r | |
832 | {\r | |
833 | return PciExpressAnd32 (Address, AndData);\r | |
834 | }\r | |
835 | \r | |
836 | /**\r | |
837 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
62991af2 | 838 | value, followed a bitwise OR with another 32-bit value.\r |
e1f414b6 | 839 | \r |
840 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
841 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 842 | performs a bitwise OR between the result of the AND operation and\r |
e1f414b6 | 843 | the value specified by OrData, and writes the result to the 32-bit PCI\r |
844 | configuration register specified by Address. The value written to the PCI\r | |
845 | configuration register is returned. This function must guarantee that all PCI\r | |
846 | read and write operations are serialized.\r | |
847 | \r | |
848 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 849 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 850 | \r |
2fc59a00 | 851 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 852 | Register.\r |
853 | @param AndData The value to AND with the PCI configuration register.\r | |
854 | @param OrData The value to OR with the result of the AND operation.\r | |
855 | \r | |
856 | @return The value written back to the PCI configuration register.\r | |
857 | \r | |
858 | **/\r | |
859 | UINT32\r | |
860 | EFIAPI\r | |
861 | PciAndThenOr32 (\r | |
862 | IN UINTN Address,\r | |
863 | IN UINT32 AndData,\r | |
864 | IN UINT32 OrData\r | |
865 | )\r | |
866 | {\r | |
867 | return PciExpressAndThenOr32 (Address, AndData, OrData);\r | |
868 | }\r | |
869 | \r | |
870 | /**\r | |
871 | Reads a bit field of a PCI configuration register.\r | |
872 | \r | |
873 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
874 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
875 | returned.\r | |
876 | \r | |
877 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 878 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 879 | If StartBit is greater than 31, then ASSERT().\r |
880 | If EndBit is greater than 31, then ASSERT().\r | |
881 | If EndBit is less than StartBit, then ASSERT().\r | |
882 | \r | |
2fc59a00 | 883 | @param Address The PCI configuration register to read.\r |
e1f414b6 | 884 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
885 | Range 0..31.\r | |
886 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
887 | Range 0..31.\r | |
888 | \r | |
889 | @return The value of the bit field read from the PCI configuration register.\r | |
890 | \r | |
891 | **/\r | |
892 | UINT32\r | |
893 | EFIAPI\r | |
894 | PciBitFieldRead32 (\r | |
895 | IN UINTN Address,\r | |
896 | IN UINTN StartBit,\r | |
897 | IN UINTN EndBit\r | |
898 | )\r | |
899 | {\r | |
900 | return PciExpressBitFieldRead32 (Address, StartBit, EndBit);\r | |
901 | }\r | |
902 | \r | |
903 | /**\r | |
904 | Writes a bit field to a PCI configuration register.\r | |
905 | \r | |
906 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
907 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
908 | destination PCI configuration register are preserved. The new value of the\r | |
909 | 32-bit register is returned.\r | |
910 | \r | |
911 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 912 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 913 | If StartBit is greater than 31, then ASSERT().\r |
914 | If EndBit is greater than 31, then ASSERT().\r | |
915 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 916 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 917 | \r |
2fc59a00 | 918 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 919 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
920 | Range 0..31.\r | |
921 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
922 | Range 0..31.\r | |
2fc59a00 | 923 | @param Value The new value of the bit field.\r |
e1f414b6 | 924 | \r |
925 | @return The value written back to the PCI configuration register.\r | |
926 | \r | |
927 | **/\r | |
928 | UINT32\r | |
929 | EFIAPI\r | |
930 | PciBitFieldWrite32 (\r | |
931 | IN UINTN Address,\r | |
932 | IN UINTN StartBit,\r | |
933 | IN UINTN EndBit,\r | |
934 | IN UINT32 Value\r | |
935 | )\r | |
936 | {\r | |
937 | return PciExpressBitFieldWrite32 (Address, StartBit, EndBit, Value);\r | |
938 | }\r | |
939 | \r | |
940 | /**\r | |
941 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
942 | writes the result back to the bit field in the 32-bit port.\r | |
943 | \r | |
944 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 945 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 946 | OrData, and writes the result to the 32-bit PCI configuration register\r |
947 | specified by Address. The value written to the PCI configuration register is\r | |
948 | returned. This function must guarantee that all PCI read and write operations\r | |
949 | are serialized. Extra left bits in OrData are stripped.\r | |
950 | \r | |
951 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 952 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 953 | If StartBit is greater than 31, then ASSERT().\r |
954 | If EndBit is greater than 31, then ASSERT().\r | |
955 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 956 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 957 | \r |
2fc59a00 | 958 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 959 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
960 | Range 0..31.\r | |
961 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
962 | Range 0..31.\r | |
963 | @param OrData The value to OR with the PCI configuration register.\r | |
964 | \r | |
965 | @return The value written back to the PCI configuration register.\r | |
966 | \r | |
967 | **/\r | |
968 | UINT32\r | |
969 | EFIAPI\r | |
970 | PciBitFieldOr32 (\r | |
971 | IN UINTN Address,\r | |
972 | IN UINTN StartBit,\r | |
973 | IN UINTN EndBit,\r | |
974 | IN UINT32 OrData\r | |
975 | )\r | |
976 | {\r | |
977 | return PciExpressBitFieldOr32 (Address, StartBit, EndBit, OrData);\r | |
978 | }\r | |
979 | \r | |
980 | /**\r | |
981 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
982 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
983 | \r | |
984 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
985 | bitwise AND between the read result and the value specified by AndData, and\r | |
986 | writes the result to the 32-bit PCI configuration register specified by\r | |
987 | Address. The value written to the PCI configuration register is returned.\r | |
988 | This function must guarantee that all PCI read and write operations are\r | |
989 | serialized. Extra left bits in AndData are stripped.\r | |
990 | \r | |
991 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 992 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 993 | If StartBit is greater than 31, then ASSERT().\r |
994 | If EndBit is greater than 31, then ASSERT().\r | |
995 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 996 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 997 | \r |
2fc59a00 | 998 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 999 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1000 | Range 0..31.\r | |
1001 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1002 | Range 0..31.\r | |
1003 | @param AndData The value to AND with the PCI configuration register.\r | |
1004 | \r | |
1005 | @return The value written back to the PCI configuration register.\r | |
1006 | \r | |
1007 | **/\r | |
1008 | UINT32\r | |
1009 | EFIAPI\r | |
1010 | PciBitFieldAnd32 (\r | |
1011 | IN UINTN Address,\r | |
1012 | IN UINTN StartBit,\r | |
1013 | IN UINTN EndBit,\r | |
1014 | IN UINT32 AndData\r | |
1015 | )\r | |
1016 | {\r | |
1017 | return PciExpressBitFieldAnd32 (Address, StartBit, EndBit, AndData);\r | |
1018 | }\r | |
1019 | \r | |
1020 | /**\r | |
1021 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 1022 | bitwise OR, and writes the result back to the bit field in the\r |
e1f414b6 | 1023 | 32-bit port.\r |
1024 | \r | |
1025 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 1026 | bitwise AND followed by a bitwise OR between the read result and\r |
e1f414b6 | 1027 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
1028 | configuration register specified by Address. The value written to the PCI\r | |
1029 | configuration register is returned. This function must guarantee that all PCI\r | |
1030 | read and write operations are serialized. Extra left bits in both AndData and\r | |
1031 | OrData are stripped.\r | |
1032 | \r | |
1033 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 1034 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 1035 | If StartBit is greater than 31, then ASSERT().\r |
1036 | If EndBit is greater than 31, then ASSERT().\r | |
1037 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
1038 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1039 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
e1f414b6 | 1040 | \r |
2fc59a00 | 1041 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 1042 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1043 | Range 0..31.\r | |
1044 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1045 | Range 0..31.\r | |
1046 | @param AndData The value to AND with the PCI configuration register.\r | |
1047 | @param OrData The value to OR with the result of the AND operation.\r | |
1048 | \r | |
1049 | @return The value written back to the PCI configuration register.\r | |
1050 | \r | |
1051 | **/\r | |
1052 | UINT32\r | |
1053 | EFIAPI\r | |
1054 | PciBitFieldAndThenOr32 (\r | |
1055 | IN UINTN Address,\r | |
1056 | IN UINTN StartBit,\r | |
1057 | IN UINTN EndBit,\r | |
1058 | IN UINT32 AndData,\r | |
1059 | IN UINT32 OrData\r | |
1060 | )\r | |
1061 | {\r | |
1062 | return PciExpressBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData);\r | |
1063 | }\r | |
1064 | \r | |
1065 | /**\r | |
1066 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
1067 | \r | |
1068 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
1069 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1070 | configuration registers from a single PCI function to be read. Size is\r | |
1071 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
1072 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
1073 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
1074 | end of the range.\r | |
1075 | \r | |
1076 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1077 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1078 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1079 | \r | |
2fc59a00 | 1080 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r |
e1f414b6 | 1081 | Function and Register.\r |
2fc59a00 | 1082 | @param Size The size in bytes of the transfer.\r |
1083 | @param Buffer The pointer to a buffer receiving the data read.\r | |
e1f414b6 | 1084 | \r |
1085 | @return Size\r | |
1086 | \r | |
1087 | **/\r | |
1088 | UINTN\r | |
1089 | EFIAPI\r | |
1090 | PciReadBuffer (\r | |
1091 | IN UINTN StartAddress,\r | |
1092 | IN UINTN Size,\r | |
1093 | OUT VOID *Buffer\r | |
1094 | )\r | |
1095 | {\r | |
1096 | return PciExpressReadBuffer (StartAddress, Size, Buffer);\r | |
1097 | }\r | |
1098 | \r | |
1099 | /**\r | |
1100 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1101 | configuration space.\r | |
1102 | \r | |
1103 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1104 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1105 | configuration registers from a single PCI function to be written. Size is\r | |
1106 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1107 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1108 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1109 | and the end of the range.\r | |
1110 | \r | |
1111 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1112 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1113 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1114 | \r | |
2fc59a00 | 1115 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r |
e1f414b6 | 1116 | Function and Register.\r |
2fc59a00 | 1117 | @param Size The size in bytes of the transfer.\r |
1118 | @param Buffer The pointer to a buffer containing the data to write.\r | |
e1f414b6 | 1119 | \r |
efb23117 | 1120 | @return Size written to StartAddress.\r |
e1f414b6 | 1121 | \r |
1122 | **/\r | |
1123 | UINTN\r | |
1124 | EFIAPI\r | |
1125 | PciWriteBuffer (\r | |
1126 | IN UINTN StartAddress,\r | |
1127 | IN UINTN Size,\r | |
1128 | IN VOID *Buffer\r | |
1129 | )\r | |
1130 | {\r | |
1131 | return PciExpressWriteBuffer (StartAddress, Size, Buffer);\r | |
1132 | }\r |