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e1f414b6 | 1 | /** @file\r |
5c57f3ea | 2 | PCI Library functions that use the 256 MB PCI Express MMIO window to perform PCI\r |
3 | Configuration cycles. Layers on PCI Express Library.\r | |
e1f414b6 | 4 | \r |
94952554 | 5 | Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r |
19388d29 | 6 | This program and the accompanying materials\r |
e1f414b6 | 7 | are licensed and made available under the terms and conditions of the BSD License\r |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
2fc59a00 | 9 | http://opensource.org/licenses/bsd-license.php.\r |
e1f414b6 | 10 | \r |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
e1f414b6 | 14 | **/\r |
15 | \r | |
c892d846 | 16 | \r |
c7d265a9 | 17 | #include <Base.h>\r |
c892d846 | 18 | \r |
c7d265a9 | 19 | #include <Library/PciLib.h>\r |
20 | #include <Library/PciExpressLib.h>\r | |
e1f414b6 | 21 | \r |
3e3ae634 | 22 | /**\r |
d11195a3 | 23 | Registers a PCI device so PCI configuration registers may be accessed after \r |
3e3ae634 | 24 | SetVirtualAddressMap().\r |
25 | \r | |
d11195a3 | 26 | Registers the PCI device specified by Address so all the PCI configuration registers \r |
27 | associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r | |
28 | \r | |
3e3ae634 | 29 | If Address > 0x0FFFFFFF, then ASSERT().\r |
30 | \r | |
2fc59a00 | 31 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
3e3ae634 | 32 | Register.\r |
33 | \r | |
34 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r | |
35 | @retval RETURN_UNSUPPORTED An attempt was made to call this function \r | |
36 | after ExitBootServices().\r | |
37 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
38 | at runtime could not be mapped.\r | |
39 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
40 | complete the registration.\r | |
41 | \r | |
42 | **/\r | |
43 | RETURN_STATUS\r | |
44 | EFIAPI\r | |
45 | PciRegisterForRuntimeAccess (\r | |
46 | IN UINTN Address\r | |
47 | )\r | |
48 | {\r | |
49 | return PciExpressRegisterForRuntimeAccess (Address);\r | |
50 | }\r | |
51 | \r | |
e1f414b6 | 52 | /**\r |
53 | Reads an 8-bit PCI configuration register.\r | |
54 | \r | |
55 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
56 | This function must guarantee that all PCI read and write operations are\r | |
57 | serialized.\r | |
58 | \r | |
59 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
60 | \r | |
2fc59a00 | 61 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 62 | Register.\r |
63 | \r | |
64 | @return The read value from the PCI configuration register.\r | |
65 | \r | |
66 | **/\r | |
67 | UINT8\r | |
68 | EFIAPI\r | |
69 | PciRead8 (\r | |
70 | IN UINTN Address\r | |
71 | )\r | |
72 | {\r | |
73 | return PciExpressRead8 (Address);\r | |
74 | }\r | |
75 | \r | |
76 | /**\r | |
77 | Writes an 8-bit PCI configuration register.\r | |
78 | \r | |
79 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
80 | value specified by Value. Value is returned. This function must guarantee\r | |
81 | that all PCI read and write operations are serialized.\r | |
82 | \r | |
83 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
84 | \r | |
2fc59a00 | 85 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 86 | Register.\r |
7612cbf0 | 87 | @param Value The value to write.\r |
e1f414b6 | 88 | \r |
89 | @return The value written to the PCI configuration register.\r | |
90 | \r | |
91 | **/\r | |
92 | UINT8\r | |
93 | EFIAPI\r | |
94 | PciWrite8 (\r | |
95 | IN UINTN Address,\r | |
94646ec0 | 96 | IN UINT8 Value\r |
e1f414b6 | 97 | )\r |
98 | {\r | |
94646ec0 | 99 | return PciExpressWrite8 (Address, Value);\r |
e1f414b6 | 100 | }\r |
101 | \r | |
102 | /**\r | |
62991af2 | 103 | Performs a bitwise OR of an 8-bit PCI configuration register with\r |
e1f414b6 | 104 | an 8-bit value.\r |
105 | \r | |
106 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 107 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 108 | OrData, and writes the result to the 8-bit PCI configuration register\r |
109 | specified by Address. The value written to the PCI configuration register is\r | |
110 | returned. This function must guarantee that all PCI read and write operations\r | |
111 | are serialized.\r | |
112 | \r | |
113 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
114 | \r | |
2fc59a00 | 115 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 116 | Register.\r |
117 | @param OrData The value to OR with the PCI configuration register.\r | |
118 | \r | |
119 | @return The value written back to the PCI configuration register.\r | |
120 | \r | |
121 | **/\r | |
122 | UINT8\r | |
123 | EFIAPI\r | |
124 | PciOr8 (\r | |
125 | IN UINTN Address,\r | |
126 | IN UINT8 OrData\r | |
127 | )\r | |
128 | {\r | |
129 | return PciExpressOr8 (Address, OrData);\r | |
130 | }\r | |
131 | \r | |
132 | /**\r | |
133 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
134 | value.\r | |
135 | \r | |
136 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
137 | bitwise AND between the read result and the value specified by AndData, and\r | |
138 | writes the result to the 8-bit PCI configuration register specified by\r | |
139 | Address. The value written to the PCI configuration register is returned.\r | |
140 | This function must guarantee that all PCI read and write operations are\r | |
141 | serialized.\r | |
142 | \r | |
143 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
144 | \r | |
2fc59a00 | 145 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 146 | Register.\r |
147 | @param AndData The value to AND with the PCI configuration register.\r | |
148 | \r | |
149 | @return The value written back to the PCI configuration register.\r | |
150 | \r | |
151 | **/\r | |
152 | UINT8\r | |
153 | EFIAPI\r | |
154 | PciAnd8 (\r | |
155 | IN UINTN Address,\r | |
156 | IN UINT8 AndData\r | |
157 | )\r | |
158 | {\r | |
159 | return PciExpressAnd8 (Address, AndData);\r | |
160 | }\r | |
161 | \r | |
162 | /**\r | |
163 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
62991af2 | 164 | value, followed a bitwise OR with another 8-bit value.\r |
e1f414b6 | 165 | \r |
166 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
167 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 168 | performs a bitwise OR between the result of the AND operation and\r |
e1f414b6 | 169 | the value specified by OrData, and writes the result to the 8-bit PCI\r |
170 | configuration register specified by Address. The value written to the PCI\r | |
171 | configuration register is returned. This function must guarantee that all PCI\r | |
172 | read and write operations are serialized.\r | |
173 | \r | |
174 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
175 | \r | |
2fc59a00 | 176 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 177 | Register.\r |
178 | @param AndData The value to AND with the PCI configuration register.\r | |
179 | @param OrData The value to OR with the result of the AND operation.\r | |
180 | \r | |
181 | @return The value written back to the PCI configuration register.\r | |
182 | \r | |
183 | **/\r | |
184 | UINT8\r | |
185 | EFIAPI\r | |
186 | PciAndThenOr8 (\r | |
187 | IN UINTN Address,\r | |
188 | IN UINT8 AndData,\r | |
189 | IN UINT8 OrData\r | |
190 | )\r | |
191 | {\r | |
192 | return PciExpressAndThenOr8 (Address, AndData, OrData);\r | |
193 | }\r | |
194 | \r | |
195 | /**\r | |
196 | Reads a bit field of a PCI configuration register.\r | |
197 | \r | |
198 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
199 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
200 | returned.\r | |
201 | \r | |
202 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
203 | If StartBit is greater than 7, then ASSERT().\r | |
204 | If EndBit is greater than 7, then ASSERT().\r | |
205 | If EndBit is less than StartBit, then ASSERT().\r | |
206 | \r | |
2fc59a00 | 207 | @param Address The PCI configuration register to read.\r |
e1f414b6 | 208 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
209 | Range 0..7.\r | |
210 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
211 | Range 0..7.\r | |
212 | \r | |
213 | @return The value of the bit field read from the PCI configuration register.\r | |
214 | \r | |
215 | **/\r | |
216 | UINT8\r | |
217 | EFIAPI\r | |
218 | PciBitFieldRead8 (\r | |
219 | IN UINTN Address,\r | |
220 | IN UINTN StartBit,\r | |
221 | IN UINTN EndBit\r | |
222 | )\r | |
223 | {\r | |
224 | return PciExpressBitFieldRead8 (Address, StartBit, EndBit);\r | |
225 | }\r | |
226 | \r | |
227 | /**\r | |
228 | Writes a bit field to a PCI configuration register.\r | |
229 | \r | |
230 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
231 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
232 | destination PCI configuration register are preserved. The new value of the\r | |
233 | 8-bit register is returned.\r | |
234 | \r | |
235 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
236 | If StartBit is greater than 7, then ASSERT().\r | |
237 | If EndBit is greater than 7, then ASSERT().\r | |
238 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 239 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 240 | \r |
2fc59a00 | 241 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 242 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
243 | Range 0..7.\r | |
244 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
245 | Range 0..7.\r | |
2fc59a00 | 246 | @param Value The new value of the bit field.\r |
e1f414b6 | 247 | \r |
248 | @return The value written back to the PCI configuration register.\r | |
249 | \r | |
250 | **/\r | |
251 | UINT8\r | |
252 | EFIAPI\r | |
253 | PciBitFieldWrite8 (\r | |
254 | IN UINTN Address,\r | |
255 | IN UINTN StartBit,\r | |
256 | IN UINTN EndBit,\r | |
257 | IN UINT8 Value\r | |
258 | )\r | |
259 | {\r | |
260 | return PciExpressBitFieldWrite8 (Address, StartBit, EndBit, Value);\r | |
261 | }\r | |
262 | \r | |
263 | /**\r | |
264 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
265 | writes the result back to the bit field in the 8-bit port.\r | |
266 | \r | |
267 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 268 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 269 | OrData, and writes the result to the 8-bit PCI configuration register\r |
270 | specified by Address. The value written to the PCI configuration register is\r | |
271 | returned. This function must guarantee that all PCI read and write operations\r | |
272 | are serialized. Extra left bits in OrData are stripped.\r | |
273 | \r | |
274 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
275 | If StartBit is greater than 7, then ASSERT().\r | |
276 | If EndBit is greater than 7, then ASSERT().\r | |
277 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 278 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 279 | \r |
2fc59a00 | 280 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 281 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
282 | Range 0..7.\r | |
283 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
284 | Range 0..7.\r | |
285 | @param OrData The value to OR with the PCI configuration register.\r | |
286 | \r | |
287 | @return The value written back to the PCI configuration register.\r | |
288 | \r | |
289 | **/\r | |
290 | UINT8\r | |
291 | EFIAPI\r | |
292 | PciBitFieldOr8 (\r | |
293 | IN UINTN Address,\r | |
294 | IN UINTN StartBit,\r | |
295 | IN UINTN EndBit,\r | |
296 | IN UINT8 OrData\r | |
297 | )\r | |
298 | {\r | |
299 | return PciExpressBitFieldOr8 (Address, StartBit, EndBit, OrData);\r | |
300 | }\r | |
301 | \r | |
302 | /**\r | |
303 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
304 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
305 | \r | |
306 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
307 | bitwise AND between the read result and the value specified by AndData, and\r | |
308 | writes the result to the 8-bit PCI configuration register specified by\r | |
309 | Address. The value written to the PCI configuration register is returned.\r | |
310 | This function must guarantee that all PCI read and write operations are\r | |
311 | serialized. Extra left bits in AndData are stripped.\r | |
312 | \r | |
313 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
314 | If StartBit is greater than 7, then ASSERT().\r | |
315 | If EndBit is greater than 7, then ASSERT().\r | |
316 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 317 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 318 | \r |
2fc59a00 | 319 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 320 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
321 | Range 0..7.\r | |
322 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
323 | Range 0..7.\r | |
324 | @param AndData The value to AND with the PCI configuration register.\r | |
325 | \r | |
326 | @return The value written back to the PCI configuration register.\r | |
327 | \r | |
328 | **/\r | |
329 | UINT8\r | |
330 | EFIAPI\r | |
331 | PciBitFieldAnd8 (\r | |
332 | IN UINTN Address,\r | |
333 | IN UINTN StartBit,\r | |
334 | IN UINTN EndBit,\r | |
335 | IN UINT8 AndData\r | |
336 | )\r | |
337 | {\r | |
338 | return PciExpressBitFieldAnd8 (Address, StartBit, EndBit, AndData);\r | |
339 | }\r | |
340 | \r | |
341 | /**\r | |
342 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 343 | bitwise OR, and writes the result back to the bit field in the\r |
e1f414b6 | 344 | 8-bit port.\r |
345 | \r | |
346 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 347 | bitwise AND followed by a bitwise OR between the read result and\r |
e1f414b6 | 348 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
349 | configuration register specified by Address. The value written to the PCI\r | |
350 | configuration register is returned. This function must guarantee that all PCI\r | |
351 | read and write operations are serialized. Extra left bits in both AndData and\r | |
352 | OrData are stripped.\r | |
353 | \r | |
354 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
355 | If StartBit is greater than 7, then ASSERT().\r | |
356 | If EndBit is greater than 7, then ASSERT().\r | |
357 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
358 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
359 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
e1f414b6 | 360 | \r |
2fc59a00 | 361 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 362 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
363 | Range 0..7.\r | |
364 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
365 | Range 0..7.\r | |
366 | @param AndData The value to AND with the PCI configuration register.\r | |
367 | @param OrData The value to OR with the result of the AND operation.\r | |
368 | \r | |
369 | @return The value written back to the PCI configuration register.\r | |
370 | \r | |
371 | **/\r | |
372 | UINT8\r | |
373 | EFIAPI\r | |
374 | PciBitFieldAndThenOr8 (\r | |
375 | IN UINTN Address,\r | |
376 | IN UINTN StartBit,\r | |
377 | IN UINTN EndBit,\r | |
378 | IN UINT8 AndData,\r | |
379 | IN UINT8 OrData\r | |
380 | )\r | |
381 | {\r | |
382 | return PciExpressBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData);\r | |
383 | }\r | |
384 | \r | |
385 | /**\r | |
386 | Reads a 16-bit PCI configuration register.\r | |
387 | \r | |
388 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
389 | This function must guarantee that all PCI read and write operations are\r | |
390 | serialized.\r | |
391 | \r | |
392 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 393 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 394 | \r |
2fc59a00 | 395 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 396 | Register.\r |
397 | \r | |
398 | @return The read value from the PCI configuration register.\r | |
399 | \r | |
400 | **/\r | |
401 | UINT16\r | |
402 | EFIAPI\r | |
403 | PciRead16 (\r | |
404 | IN UINTN Address\r | |
405 | )\r | |
406 | {\r | |
407 | return PciExpressRead16 (Address);\r | |
408 | }\r | |
409 | \r | |
410 | /**\r | |
411 | Writes a 16-bit PCI configuration register.\r | |
412 | \r | |
413 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
414 | value specified by Value. Value is returned. This function must guarantee\r | |
415 | that all PCI read and write operations are serialized.\r | |
416 | \r | |
417 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 418 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 419 | \r |
2fc59a00 | 420 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 421 | Register.\r |
9638ba6d | 422 | @param Value The value to write.\r |
e1f414b6 | 423 | \r |
424 | @return The value written to the PCI configuration register.\r | |
425 | \r | |
426 | **/\r | |
427 | UINT16\r | |
428 | EFIAPI\r | |
429 | PciWrite16 (\r | |
430 | IN UINTN Address,\r | |
94646ec0 | 431 | IN UINT16 Value\r |
e1f414b6 | 432 | )\r |
433 | {\r | |
94646ec0 | 434 | return PciExpressWrite16 (Address, Value);\r |
e1f414b6 | 435 | }\r |
436 | \r | |
437 | /**\r | |
62991af2 | 438 | Performs a bitwise OR of a 16-bit PCI configuration register with\r |
e1f414b6 | 439 | a 16-bit value.\r |
440 | \r | |
441 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 442 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 443 | OrData, and writes the result to the 16-bit PCI configuration register\r |
444 | specified by Address. The value written to the PCI configuration register is\r | |
445 | returned. This function must guarantee that all PCI read and write operations\r | |
446 | are serialized.\r | |
447 | \r | |
448 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 449 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 450 | \r |
2fc59a00 | 451 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 452 | Register.\r |
453 | @param OrData The value to OR with the PCI configuration register.\r | |
454 | \r | |
455 | @return The value written back to the PCI configuration register.\r | |
456 | \r | |
457 | **/\r | |
458 | UINT16\r | |
459 | EFIAPI\r | |
460 | PciOr16 (\r | |
461 | IN UINTN Address,\r | |
462 | IN UINT16 OrData\r | |
463 | )\r | |
464 | {\r | |
465 | return PciExpressOr16 (Address, OrData);\r | |
466 | }\r | |
467 | \r | |
468 | /**\r | |
469 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
470 | value.\r | |
471 | \r | |
472 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
473 | bitwise AND between the read result and the value specified by AndData, and\r | |
474 | writes the result to the 16-bit PCI configuration register specified by\r | |
475 | Address. The value written to the PCI configuration register is returned.\r | |
476 | This function must guarantee that all PCI read and write operations are\r | |
477 | serialized.\r | |
478 | \r | |
479 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 480 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 481 | \r |
2fc59a00 | 482 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 483 | Register.\r |
484 | @param AndData The value to AND with the PCI configuration register.\r | |
485 | \r | |
486 | @return The value written back to the PCI configuration register.\r | |
487 | \r | |
488 | **/\r | |
489 | UINT16\r | |
490 | EFIAPI\r | |
491 | PciAnd16 (\r | |
492 | IN UINTN Address,\r | |
493 | IN UINT16 AndData\r | |
494 | )\r | |
495 | {\r | |
496 | return PciExpressAnd16 (Address, AndData);\r | |
497 | }\r | |
498 | \r | |
499 | /**\r | |
500 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
62991af2 | 501 | value, followed a bitwise OR with another 16-bit value.\r |
e1f414b6 | 502 | \r |
503 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
504 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 505 | performs a bitwise OR between the result of the AND operation and\r |
e1f414b6 | 506 | the value specified by OrData, and writes the result to the 16-bit PCI\r |
507 | configuration register specified by Address. The value written to the PCI\r | |
508 | configuration register is returned. This function must guarantee that all PCI\r | |
509 | read and write operations are serialized.\r | |
510 | \r | |
511 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 512 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 513 | \r |
2fc59a00 | 514 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 515 | Register.\r |
516 | @param AndData The value to AND with the PCI configuration register.\r | |
517 | @param OrData The value to OR with the result of the AND operation.\r | |
518 | \r | |
519 | @return The value written back to the PCI configuration register.\r | |
520 | \r | |
521 | **/\r | |
522 | UINT16\r | |
523 | EFIAPI\r | |
524 | PciAndThenOr16 (\r | |
525 | IN UINTN Address,\r | |
526 | IN UINT16 AndData,\r | |
527 | IN UINT16 OrData\r | |
528 | )\r | |
529 | {\r | |
530 | return PciExpressAndThenOr16 (Address, AndData, OrData);\r | |
531 | }\r | |
532 | \r | |
533 | /**\r | |
534 | Reads a bit field of a PCI configuration register.\r | |
535 | \r | |
536 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
537 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
538 | returned.\r | |
539 | \r | |
540 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 541 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 542 | If StartBit is greater than 15, then ASSERT().\r |
543 | If EndBit is greater than 15, then ASSERT().\r | |
544 | If EndBit is less than StartBit, then ASSERT().\r | |
545 | \r | |
2fc59a00 | 546 | @param Address The PCI configuration register to read.\r |
e1f414b6 | 547 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
548 | Range 0..15.\r | |
549 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
550 | Range 0..15.\r | |
551 | \r | |
552 | @return The value of the bit field read from the PCI configuration register.\r | |
553 | \r | |
554 | **/\r | |
555 | UINT16\r | |
556 | EFIAPI\r | |
557 | PciBitFieldRead16 (\r | |
558 | IN UINTN Address,\r | |
559 | IN UINTN StartBit,\r | |
560 | IN UINTN EndBit\r | |
561 | )\r | |
562 | {\r | |
563 | return PciExpressBitFieldRead16 (Address, StartBit, EndBit);\r | |
564 | }\r | |
565 | \r | |
566 | /**\r | |
567 | Writes a bit field to a PCI configuration register.\r | |
568 | \r | |
569 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
570 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
571 | destination PCI configuration register are preserved. The new value of the\r | |
572 | 16-bit register is returned.\r | |
573 | \r | |
574 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 575 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 576 | If StartBit is greater than 15, then ASSERT().\r |
577 | If EndBit is greater than 15, then ASSERT().\r | |
578 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 579 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 580 | \r |
2fc59a00 | 581 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 582 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
583 | Range 0..15.\r | |
584 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
585 | Range 0..15.\r | |
2fc59a00 | 586 | @param Value The new value of the bit field.\r |
e1f414b6 | 587 | \r |
588 | @return The value written back to the PCI configuration register.\r | |
589 | \r | |
590 | **/\r | |
591 | UINT16\r | |
592 | EFIAPI\r | |
593 | PciBitFieldWrite16 (\r | |
594 | IN UINTN Address,\r | |
595 | IN UINTN StartBit,\r | |
596 | IN UINTN EndBit,\r | |
597 | IN UINT16 Value\r | |
598 | )\r | |
599 | {\r | |
600 | return PciExpressBitFieldWrite16 (Address, StartBit, EndBit, Value);\r | |
601 | }\r | |
602 | \r | |
603 | /**\r | |
604 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
605 | writes the result back to the bit field in the 16-bit port.\r | |
606 | \r | |
607 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 608 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 609 | OrData, and writes the result to the 16-bit PCI configuration register\r |
610 | specified by Address. The value written to the PCI configuration register is\r | |
611 | returned. This function must guarantee that all PCI read and write operations\r | |
612 | are serialized. Extra left bits in OrData are stripped.\r | |
613 | \r | |
614 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 615 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 616 | If StartBit is greater than 15, then ASSERT().\r |
617 | If EndBit is greater than 15, then ASSERT().\r | |
618 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 619 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 620 | \r |
2fc59a00 | 621 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 622 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
623 | Range 0..15.\r | |
624 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
625 | Range 0..15.\r | |
626 | @param OrData The value to OR with the PCI configuration register.\r | |
627 | \r | |
628 | @return The value written back to the PCI configuration register.\r | |
629 | \r | |
630 | **/\r | |
631 | UINT16\r | |
632 | EFIAPI\r | |
633 | PciBitFieldOr16 (\r | |
634 | IN UINTN Address,\r | |
635 | IN UINTN StartBit,\r | |
636 | IN UINTN EndBit,\r | |
637 | IN UINT16 OrData\r | |
638 | )\r | |
639 | {\r | |
640 | return PciExpressBitFieldOr16 (Address, StartBit, EndBit, OrData);\r | |
641 | }\r | |
642 | \r | |
643 | /**\r | |
644 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
645 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
646 | \r | |
647 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
648 | bitwise AND between the read result and the value specified by AndData, and\r | |
649 | writes the result to the 16-bit PCI configuration register specified by\r | |
650 | Address. The value written to the PCI configuration register is returned.\r | |
651 | This function must guarantee that all PCI read and write operations are\r | |
652 | serialized. Extra left bits in AndData are stripped.\r | |
653 | \r | |
654 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 655 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 656 | If StartBit is greater than 15, then ASSERT().\r |
657 | If EndBit is greater than 15, then ASSERT().\r | |
658 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 659 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 660 | \r |
2fc59a00 | 661 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 662 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
663 | Range 0..15.\r | |
664 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
665 | Range 0..15.\r | |
666 | @param AndData The value to AND with the PCI configuration register.\r | |
667 | \r | |
668 | @return The value written back to the PCI configuration register.\r | |
669 | \r | |
670 | **/\r | |
671 | UINT16\r | |
672 | EFIAPI\r | |
673 | PciBitFieldAnd16 (\r | |
674 | IN UINTN Address,\r | |
675 | IN UINTN StartBit,\r | |
676 | IN UINTN EndBit,\r | |
677 | IN UINT16 AndData\r | |
678 | )\r | |
679 | {\r | |
680 | return PciExpressBitFieldAnd16 (Address, StartBit, EndBit, AndData);\r | |
681 | }\r | |
682 | \r | |
683 | /**\r | |
684 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 685 | bitwise OR, and writes the result back to the bit field in the\r |
e1f414b6 | 686 | 16-bit port.\r |
687 | \r | |
688 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 689 | bitwise AND followed by a bitwise OR between the read result and\r |
e1f414b6 | 690 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
691 | configuration register specified by Address. The value written to the PCI\r | |
692 | configuration register is returned. This function must guarantee that all PCI\r | |
693 | read and write operations are serialized. Extra left bits in both AndData and\r | |
694 | OrData are stripped.\r | |
695 | \r | |
696 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 697 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 698 | If StartBit is greater than 15, then ASSERT().\r |
699 | If EndBit is greater than 15, then ASSERT().\r | |
700 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
701 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
702 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
e1f414b6 | 703 | \r |
2fc59a00 | 704 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 705 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
706 | Range 0..15.\r | |
707 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
708 | Range 0..15.\r | |
709 | @param AndData The value to AND with the PCI configuration register.\r | |
710 | @param OrData The value to OR with the result of the AND operation.\r | |
711 | \r | |
712 | @return The value written back to the PCI configuration register.\r | |
713 | \r | |
714 | **/\r | |
715 | UINT16\r | |
716 | EFIAPI\r | |
717 | PciBitFieldAndThenOr16 (\r | |
718 | IN UINTN Address,\r | |
719 | IN UINTN StartBit,\r | |
720 | IN UINTN EndBit,\r | |
721 | IN UINT16 AndData,\r | |
722 | IN UINT16 OrData\r | |
723 | )\r | |
724 | {\r | |
725 | return PciExpressBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData);\r | |
726 | }\r | |
727 | \r | |
728 | /**\r | |
729 | Reads a 32-bit PCI configuration register.\r | |
730 | \r | |
731 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
732 | This function must guarantee that all PCI read and write operations are\r | |
733 | serialized.\r | |
734 | \r | |
735 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 736 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 737 | \r |
2fc59a00 | 738 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 739 | Register.\r |
740 | \r | |
741 | @return The read value from the PCI configuration register.\r | |
742 | \r | |
743 | **/\r | |
744 | UINT32\r | |
745 | EFIAPI\r | |
746 | PciRead32 (\r | |
747 | IN UINTN Address\r | |
748 | )\r | |
749 | {\r | |
750 | return PciExpressRead32 (Address);\r | |
751 | }\r | |
752 | \r | |
753 | /**\r | |
754 | Writes a 32-bit PCI configuration register.\r | |
755 | \r | |
756 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
757 | value specified by Value. Value is returned. This function must guarantee\r | |
758 | that all PCI read and write operations are serialized.\r | |
759 | \r | |
760 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 761 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 762 | \r |
2fc59a00 | 763 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 764 | Register.\r |
7612cbf0 | 765 | @param Value The value to write.\r |
e1f414b6 | 766 | \r |
767 | @return The value written to the PCI configuration register.\r | |
768 | \r | |
769 | **/\r | |
770 | UINT32\r | |
771 | EFIAPI\r | |
772 | PciWrite32 (\r | |
773 | IN UINTN Address,\r | |
94646ec0 | 774 | IN UINT32 Value\r |
e1f414b6 | 775 | )\r |
776 | {\r | |
94646ec0 | 777 | return PciExpressWrite32 (Address, Value);\r |
e1f414b6 | 778 | }\r |
779 | \r | |
780 | /**\r | |
62991af2 | 781 | Performs a bitwise OR of a 32-bit PCI configuration register with\r |
e1f414b6 | 782 | a 32-bit value.\r |
783 | \r | |
784 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 785 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 786 | OrData, and writes the result to the 32-bit PCI configuration register\r |
787 | specified by Address. The value written to the PCI configuration register is\r | |
788 | returned. This function must guarantee that all PCI read and write operations\r | |
789 | are serialized.\r | |
790 | \r | |
791 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 792 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 793 | \r |
2fc59a00 | 794 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 795 | Register.\r |
796 | @param OrData The value to OR with the PCI configuration register.\r | |
797 | \r | |
798 | @return The value written back to the PCI configuration register.\r | |
799 | \r | |
800 | **/\r | |
801 | UINT32\r | |
802 | EFIAPI\r | |
803 | PciOr32 (\r | |
804 | IN UINTN Address,\r | |
805 | IN UINT32 OrData\r | |
806 | )\r | |
807 | {\r | |
808 | return PciExpressOr32 (Address, OrData);\r | |
809 | }\r | |
810 | \r | |
811 | /**\r | |
812 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
813 | value.\r | |
814 | \r | |
815 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
816 | bitwise AND between the read result and the value specified by AndData, and\r | |
817 | writes the result to the 32-bit PCI configuration register specified by\r | |
818 | Address. The value written to the PCI configuration register is returned.\r | |
819 | This function must guarantee that all PCI read and write operations are\r | |
820 | serialized.\r | |
821 | \r | |
822 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 823 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 824 | \r |
2fc59a00 | 825 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 826 | Register.\r |
827 | @param AndData The value to AND with the PCI configuration register.\r | |
828 | \r | |
829 | @return The value written back to the PCI configuration register.\r | |
830 | \r | |
831 | **/\r | |
832 | UINT32\r | |
833 | EFIAPI\r | |
834 | PciAnd32 (\r | |
835 | IN UINTN Address,\r | |
836 | IN UINT32 AndData\r | |
837 | )\r | |
838 | {\r | |
839 | return PciExpressAnd32 (Address, AndData);\r | |
840 | }\r | |
841 | \r | |
842 | /**\r | |
843 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
62991af2 | 844 | value, followed a bitwise OR with another 32-bit value.\r |
e1f414b6 | 845 | \r |
846 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
847 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 848 | performs a bitwise OR between the result of the AND operation and\r |
e1f414b6 | 849 | the value specified by OrData, and writes the result to the 32-bit PCI\r |
850 | configuration register specified by Address. The value written to the PCI\r | |
851 | configuration register is returned. This function must guarantee that all PCI\r | |
852 | read and write operations are serialized.\r | |
853 | \r | |
854 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 855 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 856 | \r |
2fc59a00 | 857 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 858 | Register.\r |
859 | @param AndData The value to AND with the PCI configuration register.\r | |
860 | @param OrData The value to OR with the result of the AND operation.\r | |
861 | \r | |
862 | @return The value written back to the PCI configuration register.\r | |
863 | \r | |
864 | **/\r | |
865 | UINT32\r | |
866 | EFIAPI\r | |
867 | PciAndThenOr32 (\r | |
868 | IN UINTN Address,\r | |
869 | IN UINT32 AndData,\r | |
870 | IN UINT32 OrData\r | |
871 | )\r | |
872 | {\r | |
873 | return PciExpressAndThenOr32 (Address, AndData, OrData);\r | |
874 | }\r | |
875 | \r | |
876 | /**\r | |
877 | Reads a bit field of a PCI configuration register.\r | |
878 | \r | |
879 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
880 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
881 | returned.\r | |
882 | \r | |
883 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 884 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 885 | If StartBit is greater than 31, then ASSERT().\r |
886 | If EndBit is greater than 31, then ASSERT().\r | |
887 | If EndBit is less than StartBit, then ASSERT().\r | |
888 | \r | |
2fc59a00 | 889 | @param Address The PCI configuration register to read.\r |
e1f414b6 | 890 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
891 | Range 0..31.\r | |
892 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
893 | Range 0..31.\r | |
894 | \r | |
895 | @return The value of the bit field read from the PCI configuration register.\r | |
896 | \r | |
897 | **/\r | |
898 | UINT32\r | |
899 | EFIAPI\r | |
900 | PciBitFieldRead32 (\r | |
901 | IN UINTN Address,\r | |
902 | IN UINTN StartBit,\r | |
903 | IN UINTN EndBit\r | |
904 | )\r | |
905 | {\r | |
906 | return PciExpressBitFieldRead32 (Address, StartBit, EndBit);\r | |
907 | }\r | |
908 | \r | |
909 | /**\r | |
910 | Writes a bit field to a PCI configuration register.\r | |
911 | \r | |
912 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
913 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
914 | destination PCI configuration register are preserved. The new value of the\r | |
915 | 32-bit register is returned.\r | |
916 | \r | |
917 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 918 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 919 | If StartBit is greater than 31, then ASSERT().\r |
920 | If EndBit is greater than 31, then ASSERT().\r | |
921 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 922 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 923 | \r |
2fc59a00 | 924 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 925 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
926 | Range 0..31.\r | |
927 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
928 | Range 0..31.\r | |
2fc59a00 | 929 | @param Value The new value of the bit field.\r |
e1f414b6 | 930 | \r |
931 | @return The value written back to the PCI configuration register.\r | |
932 | \r | |
933 | **/\r | |
934 | UINT32\r | |
935 | EFIAPI\r | |
936 | PciBitFieldWrite32 (\r | |
937 | IN UINTN Address,\r | |
938 | IN UINTN StartBit,\r | |
939 | IN UINTN EndBit,\r | |
940 | IN UINT32 Value\r | |
941 | )\r | |
942 | {\r | |
943 | return PciExpressBitFieldWrite32 (Address, StartBit, EndBit, Value);\r | |
944 | }\r | |
945 | \r | |
946 | /**\r | |
947 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
948 | writes the result back to the bit field in the 32-bit port.\r | |
949 | \r | |
950 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 951 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 952 | OrData, and writes the result to the 32-bit PCI configuration register\r |
953 | specified by Address. The value written to the PCI configuration register is\r | |
954 | returned. This function must guarantee that all PCI read and write operations\r | |
955 | are serialized. Extra left bits in OrData are stripped.\r | |
956 | \r | |
957 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 958 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 959 | If StartBit is greater than 31, then ASSERT().\r |
960 | If EndBit is greater than 31, then ASSERT().\r | |
961 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 962 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 963 | \r |
2fc59a00 | 964 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 965 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
966 | Range 0..31.\r | |
967 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
968 | Range 0..31.\r | |
969 | @param OrData The value to OR with the PCI configuration register.\r | |
970 | \r | |
971 | @return The value written back to the PCI configuration register.\r | |
972 | \r | |
973 | **/\r | |
974 | UINT32\r | |
975 | EFIAPI\r | |
976 | PciBitFieldOr32 (\r | |
977 | IN UINTN Address,\r | |
978 | IN UINTN StartBit,\r | |
979 | IN UINTN EndBit,\r | |
980 | IN UINT32 OrData\r | |
981 | )\r | |
982 | {\r | |
983 | return PciExpressBitFieldOr32 (Address, StartBit, EndBit, OrData);\r | |
984 | }\r | |
985 | \r | |
986 | /**\r | |
987 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
988 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
989 | \r | |
990 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
991 | bitwise AND between the read result and the value specified by AndData, and\r | |
992 | writes the result to the 32-bit PCI configuration register specified by\r | |
993 | Address. The value written to the PCI configuration register is returned.\r | |
994 | This function must guarantee that all PCI read and write operations are\r | |
995 | serialized. Extra left bits in AndData are stripped.\r | |
996 | \r | |
997 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 998 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 999 | If StartBit is greater than 31, then ASSERT().\r |
1000 | If EndBit is greater than 31, then ASSERT().\r | |
1001 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 1002 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 1003 | \r |
2fc59a00 | 1004 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 1005 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1006 | Range 0..31.\r | |
1007 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1008 | Range 0..31.\r | |
1009 | @param AndData The value to AND with the PCI configuration register.\r | |
1010 | \r | |
1011 | @return The value written back to the PCI configuration register.\r | |
1012 | \r | |
1013 | **/\r | |
1014 | UINT32\r | |
1015 | EFIAPI\r | |
1016 | PciBitFieldAnd32 (\r | |
1017 | IN UINTN Address,\r | |
1018 | IN UINTN StartBit,\r | |
1019 | IN UINTN EndBit,\r | |
1020 | IN UINT32 AndData\r | |
1021 | )\r | |
1022 | {\r | |
1023 | return PciExpressBitFieldAnd32 (Address, StartBit, EndBit, AndData);\r | |
1024 | }\r | |
1025 | \r | |
1026 | /**\r | |
1027 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 1028 | bitwise OR, and writes the result back to the bit field in the\r |
e1f414b6 | 1029 | 32-bit port.\r |
1030 | \r | |
1031 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 1032 | bitwise AND followed by a bitwise OR between the read result and\r |
e1f414b6 | 1033 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
1034 | configuration register specified by Address. The value written to the PCI\r | |
1035 | configuration register is returned. This function must guarantee that all PCI\r | |
1036 | read and write operations are serialized. Extra left bits in both AndData and\r | |
1037 | OrData are stripped.\r | |
1038 | \r | |
1039 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 1040 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 1041 | If StartBit is greater than 31, then ASSERT().\r |
1042 | If EndBit is greater than 31, then ASSERT().\r | |
1043 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
1044 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1045 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
e1f414b6 | 1046 | \r |
2fc59a00 | 1047 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 1048 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1049 | Range 0..31.\r | |
1050 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1051 | Range 0..31.\r | |
1052 | @param AndData The value to AND with the PCI configuration register.\r | |
1053 | @param OrData The value to OR with the result of the AND operation.\r | |
1054 | \r | |
1055 | @return The value written back to the PCI configuration register.\r | |
1056 | \r | |
1057 | **/\r | |
1058 | UINT32\r | |
1059 | EFIAPI\r | |
1060 | PciBitFieldAndThenOr32 (\r | |
1061 | IN UINTN Address,\r | |
1062 | IN UINTN StartBit,\r | |
1063 | IN UINTN EndBit,\r | |
1064 | IN UINT32 AndData,\r | |
1065 | IN UINT32 OrData\r | |
1066 | )\r | |
1067 | {\r | |
1068 | return PciExpressBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData);\r | |
1069 | }\r | |
1070 | \r | |
1071 | /**\r | |
1072 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
1073 | \r | |
1074 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
1075 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1076 | configuration registers from a single PCI function to be read. Size is\r | |
1077 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
1078 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
1079 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
1080 | end of the range.\r | |
1081 | \r | |
1082 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1083 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1084 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1085 | \r | |
2fc59a00 | 1086 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r |
e1f414b6 | 1087 | Function and Register.\r |
2fc59a00 | 1088 | @param Size The size in bytes of the transfer.\r |
1089 | @param Buffer The pointer to a buffer receiving the data read.\r | |
e1f414b6 | 1090 | \r |
1091 | @return Size\r | |
1092 | \r | |
1093 | **/\r | |
1094 | UINTN\r | |
1095 | EFIAPI\r | |
1096 | PciReadBuffer (\r | |
1097 | IN UINTN StartAddress,\r | |
1098 | IN UINTN Size,\r | |
1099 | OUT VOID *Buffer\r | |
1100 | )\r | |
1101 | {\r | |
1102 | return PciExpressReadBuffer (StartAddress, Size, Buffer);\r | |
1103 | }\r | |
1104 | \r | |
1105 | /**\r | |
1106 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1107 | configuration space.\r | |
1108 | \r | |
1109 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1110 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1111 | configuration registers from a single PCI function to be written. Size is\r | |
1112 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1113 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1114 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1115 | and the end of the range.\r | |
1116 | \r | |
1117 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1118 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1119 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1120 | \r | |
2fc59a00 | 1121 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r |
e1f414b6 | 1122 | Function and Register.\r |
2fc59a00 | 1123 | @param Size The size in bytes of the transfer.\r |
1124 | @param Buffer The pointer to a buffer containing the data to write.\r | |
e1f414b6 | 1125 | \r |
efb23117 | 1126 | @return Size written to StartAddress.\r |
e1f414b6 | 1127 | \r |
1128 | **/\r | |
1129 | UINTN\r | |
1130 | EFIAPI\r | |
1131 | PciWriteBuffer (\r | |
1132 | IN UINTN StartAddress,\r | |
1133 | IN UINTN Size,\r | |
1134 | IN VOID *Buffer\r | |
1135 | )\r | |
1136 | {\r | |
1137 | return PciExpressWriteBuffer (StartAddress, Size, Buffer);\r | |
1138 | }\r |