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863be5d0 | 1 | /** @file\r |
2 | DXE PCI Segment Library instance layered on top of ESAL services.\r | |
3 | \r | |
94952554 | 4 | Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r |
863be5d0 | 5 | This program and the accompanying materials\r |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php.\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #include <PiDxe.h>\r | |
16 | \r | |
17 | #include <Protocol/ExtendedSalServiceClasses.h>\r | |
18 | \r | |
19 | #include <Library/PciSegmentLib.h>\r | |
20 | #include <Library/BaseLib.h>\r | |
21 | #include <Library/DebugLib.h>\r | |
22 | #include <Library/ExtendedSalLib.h>\r | |
23 | \r | |
24 | /**\r | |
25 | Assert the validity of a PCI Segment address.\r | |
26 | A valid PCI Segment address should not contain 1's in bits 31:28\r | |
27 | \r | |
28 | @param A The address to validate.\r | |
29 | @param M Additional bits to assert to be zero.\r | |
30 | \r | |
31 | **/\r | |
32 | #define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \\r | |
33 | ASSERT (((A) & (0xf0000000 | (M))) == 0)\r | |
34 | \r | |
35 | /**\r | |
36 | Converts a PCI Library Address to a ESAL PCI Service Address.\r | |
37 | Based on SAL Spec 3.2, there are two SAL PCI Address:\r | |
38 | \r | |
39 | If address type = 0\r | |
40 | Bits 0..7 - Register address\r | |
41 | Bits 8..10 - Function number\r | |
42 | Bits 11..15 - Device number\r | |
43 | Bits 16..23 - Bus number\r | |
44 | Bits 24..31 - PCI segment group\r | |
45 | Bits 32..63 - Reserved (0)\r | |
46 | \r | |
47 | If address type = 1\r | |
48 | Bits 0..7 - Register address\r | |
49 | Bits 8..11 - Extended Register address\r | |
50 | Bits 12..14 - Function number\r | |
51 | Bits 15..19 - Device number\r | |
52 | Bits 20..27 - Bus number\r | |
53 | Bits 28..43 - PCI segment group\r | |
54 | Bits 44..63 - Reserved (0)\r | |
55 | \r | |
56 | @param A The PCI Library Address to convert.\r | |
57 | \r | |
58 | **/\r | |
59 | #define CONVERT_PCI_SEGMENT_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0(Address) (((Address >> 8) & 0xff000000) | (((Address) >> 4) & 0x00ffff00) | ((Address) & 0xff))\r | |
60 | #define CONVERT_PCI_SEGMENT_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1(Address) (((Address >> 4) & 0xffff0000000) | ((Address) & 0xfffffff))\r | |
61 | \r | |
62 | /**\r | |
63 | Check a PCI Library Address is a PCI Compatible Address or not.\r | |
64 | **/\r | |
65 | #define IS_PCI_COMPATIBLE_ADDRESS(Address) (((Address) & 0xf00) == 0)\r | |
66 | \r | |
67 | /**\r | |
68 | Internal worker function to read a PCI configuration register.\r | |
69 | \r | |
70 | This function wraps EsalPciConfigRead function of Extended SAL PCI\r | |
71 | Services Class.\r | |
72 | It reads and returns the PCI configuration register specified by Address,\r | |
73 | the width of data is specified by Width.\r | |
74 | \r | |
75 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
76 | Register.\r | |
77 | @param Width Width of data to read\r | |
78 | \r | |
79 | @return The value read from the PCI configuration register.\r | |
80 | \r | |
81 | **/\r | |
82 | UINT32\r | |
83 | DxePciSegmentLibEsalReadWorker (\r | |
84 | IN UINT64 Address,\r | |
85 | IN UINTN Width\r | |
86 | )\r | |
87 | {\r | |
88 | SAL_RETURN_REGS Return;\r | |
89 | \r | |
90 | if (IS_PCI_COMPATIBLE_ADDRESS(Address)) {\r | |
91 | Return = EsalCall (\r | |
92 | EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,\r | |
93 | EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,\r | |
94 | SalPciConfigReadFunctionId,\r | |
95 | CONVERT_PCI_SEGMENT_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0 (Address),\r | |
96 | Width,\r | |
97 | EFI_SAL_PCI_COMPATIBLE_ADDRESS,\r | |
98 | 0,\r | |
99 | 0,\r | |
100 | 0,\r | |
101 | 0\r | |
102 | );\r | |
103 | } else {\r | |
104 | Return = EsalCall (\r | |
105 | EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,\r | |
106 | EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,\r | |
107 | SalPciConfigReadFunctionId,\r | |
108 | CONVERT_PCI_SEGMENT_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1 (Address),\r | |
109 | Width,\r | |
110 | EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS,\r | |
111 | 0,\r | |
112 | 0,\r | |
113 | 0,\r | |
114 | 0\r | |
115 | );\r | |
116 | }\r | |
117 | \r | |
118 | return (UINT32) Return.r9;\r | |
119 | }\r | |
120 | \r | |
121 | /**\r | |
122 | Internal worker function to writes a PCI configuration register.\r | |
123 | \r | |
124 | This function wraps EsalPciConfigWrite function of Extended SAL PCI\r | |
125 | Services Class.\r | |
126 | It writes the PCI configuration register specified by Address with the\r | |
a750b4ae | 127 | value specified by Data. The width of data is specified by Width.\r |
863be5d0 | 128 | Data is returned.\r |
129 | \r | |
130 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
131 | Register.\r | |
132 | @param Width Width of data to write\r | |
133 | @param Data The value to write.\r | |
134 | \r | |
135 | @return The value written to the PCI configuration register.\r | |
136 | \r | |
137 | **/\r | |
138 | UINT32\r | |
139 | DxePciSegmentLibEsalWriteWorker (\r | |
140 | IN UINT64 Address,\r | |
141 | IN UINTN Width,\r | |
142 | IN UINT32 Data\r | |
143 | )\r | |
144 | {\r | |
145 | if (IS_PCI_COMPATIBLE_ADDRESS(Address)) {\r | |
146 | EsalCall (\r | |
147 | EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,\r | |
148 | EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,\r | |
149 | SalPciConfigWriteFunctionId,\r | |
150 | CONVERT_PCI_SEGMENT_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0 (Address),\r | |
151 | Width,\r | |
152 | Data,\r | |
153 | EFI_SAL_PCI_COMPATIBLE_ADDRESS,\r | |
154 | 0,\r | |
155 | 0,\r | |
156 | 0\r | |
157 | );\r | |
158 | } else {\r | |
159 | EsalCall (\r | |
160 | EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,\r | |
161 | EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,\r | |
162 | SalPciConfigWriteFunctionId,\r | |
163 | CONVERT_PCI_SEGMENT_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1 (Address),\r | |
164 | Width,\r | |
165 | Data,\r | |
166 | EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS,\r | |
167 | 0,\r | |
168 | 0,\r | |
169 | 0\r | |
170 | );\r | |
171 | }\r | |
172 | \r | |
173 | return Data;\r | |
174 | }\r | |
175 | \r | |
176 | /**\r | |
177 | Reads an 8-bit PCI configuration register.\r | |
178 | \r | |
179 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
180 | This function must guarantee that all PCI read and write operations are\r | |
181 | serialized.\r | |
182 | \r | |
183 | If any reserved bits in Address are set, then ASSERT().\r | |
184 | \r | |
185 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
186 | Register.\r | |
187 | \r | |
188 | @return The value read from the PCI configuration register.\r | |
189 | \r | |
190 | **/\r | |
191 | UINT8\r | |
192 | EFIAPI\r | |
193 | PciSegmentRead8 (\r | |
194 | IN UINT64 Address\r | |
195 | )\r | |
196 | {\r | |
197 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r | |
198 | \r | |
199 | return (UINT8) DxePciSegmentLibEsalReadWorker (Address, 1);\r | |
200 | }\r | |
201 | \r | |
202 | /**\r | |
203 | Writes an 8-bit PCI configuration register.\r | |
204 | \r | |
205 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
206 | value specified by Value. Value is returned. This function must guarantee\r | |
207 | that all PCI read and write operations are serialized.\r | |
208 | \r | |
209 | If any reserved bits in Address are set, then ASSERT().\r | |
210 | \r | |
211 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
212 | Register.\r | |
213 | @param Data The value to write.\r | |
214 | \r | |
215 | @return The value written to the PCI configuration register.\r | |
216 | \r | |
217 | **/\r | |
218 | UINT8\r | |
219 | EFIAPI\r | |
220 | PciSegmentWrite8 (\r | |
221 | IN UINT64 Address,\r | |
222 | IN UINT8 Data\r | |
223 | )\r | |
224 | {\r | |
225 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r | |
226 | \r | |
227 | return (UINT8) DxePciSegmentLibEsalWriteWorker (Address, 1, Data);\r | |
228 | }\r | |
229 | \r | |
230 | /**\r | |
231 | Performs a bitwise OR of an 8-bit PCI configuration register with\r | |
232 | an 8-bit value.\r | |
233 | \r | |
234 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
235 | bitwise OR between the read result and the value specified by\r | |
236 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
237 | specified by Address. The value written to the PCI configuration register is\r | |
238 | returned. This function must guarantee that all PCI read and write operations\r | |
239 | are serialized.\r | |
240 | \r | |
241 | If any reserved bits in Address are set, then ASSERT().\r | |
242 | \r | |
243 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
244 | Register.\r | |
245 | @param OrData The value to OR with the PCI configuration register.\r | |
246 | \r | |
247 | @return The value written back to the PCI configuration register.\r | |
248 | \r | |
249 | **/\r | |
250 | UINT8\r | |
251 | EFIAPI\r | |
252 | PciSegmentOr8 (\r | |
253 | IN UINT64 Address,\r | |
254 | IN UINT8 OrData\r | |
255 | )\r | |
256 | {\r | |
257 | return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | OrData));\r | |
258 | }\r | |
259 | \r | |
260 | /**\r | |
261 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
262 | value.\r | |
263 | \r | |
264 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
265 | bitwise AND between the read result and the value specified by AndData, and\r | |
266 | writes the result to the 8-bit PCI configuration register specified by\r | |
267 | Address. The value written to the PCI configuration register is returned.\r | |
268 | This function must guarantee that all PCI read and write operations are\r | |
269 | serialized.\r | |
270 | \r | |
271 | If any reserved bits in Address are set, then ASSERT().\r | |
272 | \r | |
273 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
274 | Register.\r | |
275 | @param AndData The value to AND with the PCI configuration register.\r | |
276 | \r | |
277 | @return The value written back to the PCI configuration register.\r | |
278 | \r | |
279 | **/\r | |
280 | UINT8\r | |
281 | EFIAPI\r | |
282 | PciSegmentAnd8 (\r | |
283 | IN UINT64 Address,\r | |
284 | IN UINT8 AndData\r | |
285 | )\r | |
286 | {\r | |
287 | return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData));\r | |
288 | }\r | |
289 | \r | |
290 | /**\r | |
291 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
292 | value, followed a bitwise OR with another 8-bit value.\r | |
293 | \r | |
294 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
295 | bitwise AND between the read result and the value specified by AndData,\r | |
296 | performs a bitwise OR between the result of the AND operation and\r | |
297 | the value specified by OrData, and writes the result to the 8-bit PCI\r | |
298 | configuration register specified by Address. The value written to the PCI\r | |
299 | configuration register is returned. This function must guarantee that all PCI\r | |
300 | read and write operations are serialized.\r | |
301 | \r | |
302 | If any reserved bits in Address are set, then ASSERT().\r | |
303 | \r | |
304 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
305 | Register.\r | |
306 | @param AndData The value to AND with the PCI configuration register.\r | |
307 | @param OrData The value to OR with the result of the AND operation.\r | |
308 | \r | |
309 | @return The value written back to the PCI configuration register.\r | |
310 | \r | |
311 | **/\r | |
312 | UINT8\r | |
313 | EFIAPI\r | |
314 | PciSegmentAndThenOr8 (\r | |
315 | IN UINT64 Address,\r | |
316 | IN UINT8 AndData,\r | |
317 | IN UINT8 OrData\r | |
318 | )\r | |
319 | {\r | |
320 | return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData));\r | |
321 | }\r | |
322 | \r | |
323 | /**\r | |
324 | Reads a bit field of a PCI configuration register.\r | |
325 | \r | |
326 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
327 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
328 | returned.\r | |
329 | \r | |
330 | If any reserved bits in Address are set, then ASSERT().\r | |
331 | If StartBit is greater than 7, then ASSERT().\r | |
332 | If EndBit is greater than 7, then ASSERT().\r | |
333 | If EndBit is less than StartBit, then ASSERT().\r | |
334 | \r | |
335 | @param Address PCI configuration register to read.\r | |
336 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
337 | Range 0..7.\r | |
338 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
339 | Range 0..7.\r | |
340 | \r | |
341 | @return The value of the bit field read from the PCI configuration register.\r | |
342 | \r | |
343 | **/\r | |
344 | UINT8\r | |
345 | EFIAPI\r | |
346 | PciSegmentBitFieldRead8 (\r | |
347 | IN UINT64 Address,\r | |
348 | IN UINTN StartBit,\r | |
349 | IN UINTN EndBit\r | |
350 | )\r | |
351 | {\r | |
352 | return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);\r | |
353 | }\r | |
354 | \r | |
355 | /**\r | |
356 | Writes a bit field to a PCI configuration register.\r | |
357 | \r | |
358 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
359 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
360 | destination PCI configuration register are preserved. The new value of the\r | |
361 | 8-bit register is returned.\r | |
362 | \r | |
363 | If any reserved bits in Address are set, then ASSERT().\r | |
364 | If StartBit is greater than 7, then ASSERT().\r | |
365 | If EndBit is greater than 7, then ASSERT().\r | |
366 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 367 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
863be5d0 | 368 | \r |
369 | @param Address PCI configuration register to write.\r | |
370 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
371 | Range 0..7.\r | |
372 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
373 | Range 0..7.\r | |
374 | @param Value New value of the bit field.\r | |
375 | \r | |
376 | @return The value written back to the PCI configuration register.\r | |
377 | \r | |
378 | **/\r | |
379 | UINT8\r | |
380 | EFIAPI\r | |
381 | PciSegmentBitFieldWrite8 (\r | |
382 | IN UINT64 Address,\r | |
383 | IN UINTN StartBit,\r | |
384 | IN UINTN EndBit,\r | |
385 | IN UINT8 Value\r | |
386 | )\r | |
387 | {\r | |
388 | return PciSegmentWrite8 (\r | |
389 | Address,\r | |
390 | BitFieldWrite8 (PciSegmentRead8 (Address), StartBit, EndBit, Value)\r | |
391 | );\r | |
392 | }\r | |
393 | \r | |
394 | /**\r | |
395 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
396 | writes the result back to the bit field in the 8-bit port.\r | |
397 | \r | |
398 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
399 | bitwise OR between the read result and the value specified by\r | |
400 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
401 | specified by Address. The value written to the PCI configuration register is\r | |
402 | returned. This function must guarantee that all PCI read and write operations\r | |
403 | are serialized. Extra left bits in OrData are stripped.\r | |
404 | \r | |
405 | If any reserved bits in Address are set, then ASSERT().\r | |
406 | If StartBit is greater than 7, then ASSERT().\r | |
407 | If EndBit is greater than 7, then ASSERT().\r | |
408 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 409 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
863be5d0 | 410 | \r |
411 | @param Address PCI configuration register to write.\r | |
412 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
413 | Range 0..7.\r | |
414 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
415 | Range 0..7.\r | |
416 | @param OrData The value to OR with the PCI configuration register.\r | |
417 | \r | |
418 | @return The value written back to the PCI configuration register.\r | |
419 | \r | |
420 | **/\r | |
421 | UINT8\r | |
422 | EFIAPI\r | |
423 | PciSegmentBitFieldOr8 (\r | |
424 | IN UINT64 Address,\r | |
425 | IN UINTN StartBit,\r | |
426 | IN UINTN EndBit,\r | |
427 | IN UINT8 OrData\r | |
428 | )\r | |
429 | {\r | |
430 | return PciSegmentWrite8 (\r | |
431 | Address,\r | |
432 | BitFieldOr8 (PciSegmentRead8 (Address), StartBit, EndBit, OrData)\r | |
433 | );\r | |
434 | }\r | |
435 | \r | |
436 | /**\r | |
437 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
438 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
439 | \r | |
440 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
441 | bitwise AND between the read result and the value specified by AndData, and\r | |
442 | writes the result to the 8-bit PCI configuration register specified by\r | |
443 | Address. The value written to the PCI configuration register is returned.\r | |
444 | This function must guarantee that all PCI read and write operations are\r | |
445 | serialized. Extra left bits in AndData are stripped.\r | |
446 | \r | |
447 | If any reserved bits in Address are set, then ASSERT().\r | |
448 | If StartBit is greater than 7, then ASSERT().\r | |
449 | If EndBit is greater than 7, then ASSERT().\r | |
450 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 451 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
863be5d0 | 452 | \r |
453 | @param Address PCI configuration register to write.\r | |
454 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
455 | Range 0..7.\r | |
456 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
457 | Range 0..7.\r | |
458 | @param AndData The value to AND with the PCI configuration register.\r | |
459 | \r | |
460 | @return The value written back to the PCI configuration register.\r | |
461 | \r | |
462 | **/\r | |
463 | UINT8\r | |
464 | EFIAPI\r | |
465 | PciSegmentBitFieldAnd8 (\r | |
466 | IN UINT64 Address,\r | |
467 | IN UINTN StartBit,\r | |
468 | IN UINTN EndBit,\r | |
469 | IN UINT8 AndData\r | |
470 | )\r | |
471 | {\r | |
472 | return PciSegmentWrite8 (\r | |
473 | Address,\r | |
474 | BitFieldAnd8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData)\r | |
475 | );\r | |
476 | }\r | |
477 | \r | |
478 | /**\r | |
479 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
480 | bitwise OR, and writes the result back to the bit field in the\r | |
481 | 8-bit port.\r | |
482 | \r | |
483 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
484 | bitwise AND followed by a bitwise OR between the read result and\r | |
485 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
486 | configuration register specified by Address. The value written to the PCI\r | |
487 | configuration register is returned. This function must guarantee that all PCI\r | |
488 | read and write operations are serialized. Extra left bits in both AndData and\r | |
489 | OrData are stripped.\r | |
490 | \r | |
491 | If any reserved bits in Address are set, then ASSERT().\r | |
492 | If StartBit is greater than 7, then ASSERT().\r | |
493 | If EndBit is greater than 7, then ASSERT().\r | |
494 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
495 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
496 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
863be5d0 | 497 | \r |
498 | @param Address PCI configuration register to write.\r | |
499 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
500 | Range 0..7.\r | |
501 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
502 | Range 0..7.\r | |
503 | @param AndData The value to AND with the PCI configuration register.\r | |
504 | @param OrData The value to OR with the result of the AND operation.\r | |
505 | \r | |
506 | @return The value written back to the PCI configuration register.\r | |
507 | \r | |
508 | **/\r | |
509 | UINT8\r | |
510 | EFIAPI\r | |
511 | PciSegmentBitFieldAndThenOr8 (\r | |
512 | IN UINT64 Address,\r | |
513 | IN UINTN StartBit,\r | |
514 | IN UINTN EndBit,\r | |
515 | IN UINT8 AndData,\r | |
516 | IN UINT8 OrData\r | |
517 | )\r | |
518 | {\r | |
519 | return PciSegmentWrite8 (\r | |
520 | Address,\r | |
521 | BitFieldAndThenOr8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData, OrData)\r | |
522 | );\r | |
523 | }\r | |
524 | \r | |
525 | /**\r | |
526 | Reads a 16-bit PCI configuration register.\r | |
527 | \r | |
528 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
529 | This function must guarantee that all PCI read and write operations are\r | |
530 | serialized.\r | |
531 | \r | |
532 | If any reserved bits in Address are set, then ASSERT().\r | |
533 | \r | |
534 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
535 | Register.\r | |
536 | \r | |
537 | @return The value read from the PCI configuration register.\r | |
538 | \r | |
539 | **/\r | |
540 | UINT16\r | |
541 | EFIAPI\r | |
542 | PciSegmentRead16 (\r | |
543 | IN UINT64 Address\r | |
544 | )\r | |
545 | {\r | |
546 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);\r | |
547 | \r | |
548 | return (UINT16) DxePciSegmentLibEsalReadWorker (Address, 2);\r | |
549 | }\r | |
550 | \r | |
551 | /**\r | |
552 | Writes a 16-bit PCI configuration register.\r | |
553 | \r | |
554 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
555 | value specified by Value. Value is returned. This function must guarantee\r | |
556 | that all PCI read and write operations are serialized.\r | |
557 | \r | |
558 | If any reserved bits in Address are set, then ASSERT().\r | |
559 | \r | |
560 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
561 | Register.\r | |
562 | @param Data The value to write.\r | |
563 | \r | |
564 | @return The value written to the PCI configuration register.\r | |
565 | \r | |
566 | **/\r | |
567 | UINT16\r | |
568 | EFIAPI\r | |
569 | PciSegmentWrite16 (\r | |
570 | IN UINT64 Address,\r | |
571 | IN UINT16 Data\r | |
572 | )\r | |
573 | {\r | |
574 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);\r | |
575 | \r | |
576 | return (UINT16) DxePciSegmentLibEsalWriteWorker (Address, 2, Data);\r | |
577 | }\r | |
578 | \r | |
579 | /**\r | |
580 | Performs a bitwise OR of a 16-bit PCI configuration register with\r | |
581 | a 16-bit value.\r | |
582 | \r | |
583 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
584 | bitwise OR between the read result and the value specified by\r | |
585 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
586 | specified by Address. The value written to the PCI configuration register is\r | |
587 | returned. This function must guarantee that all PCI read and write operations\r | |
588 | are serialized.\r | |
589 | \r | |
590 | If any reserved bits in Address are set, then ASSERT().\r | |
591 | \r | |
592 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
593 | Register.\r | |
594 | @param OrData The value to OR with the PCI configuration register.\r | |
595 | \r | |
596 | @return The value written back to the PCI configuration register.\r | |
597 | \r | |
598 | **/\r | |
599 | UINT16\r | |
600 | EFIAPI\r | |
601 | PciSegmentOr16 (\r | |
602 | IN UINT64 Address,\r | |
603 | IN UINT16 OrData\r | |
604 | )\r | |
605 | {\r | |
606 | return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData));\r | |
607 | }\r | |
608 | \r | |
609 | /**\r | |
610 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
611 | value.\r | |
612 | \r | |
613 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
614 | bitwise AND between the read result and the value specified by AndData, and\r | |
615 | writes the result to the 16-bit PCI configuration register specified by\r | |
616 | Address. The value written to the PCI configuration register is returned.\r | |
617 | This function must guarantee that all PCI read and write operations are\r | |
618 | serialized.\r | |
619 | \r | |
620 | If any reserved bits in Address are set, then ASSERT().\r | |
621 | \r | |
622 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
623 | Register.\r | |
624 | @param AndData The value to AND with the PCI configuration register.\r | |
625 | \r | |
626 | @return The value written back to the PCI configuration register.\r | |
627 | \r | |
628 | **/\r | |
629 | UINT16\r | |
630 | EFIAPI\r | |
631 | PciSegmentAnd16 (\r | |
632 | IN UINT64 Address,\r | |
633 | IN UINT16 AndData\r | |
634 | )\r | |
635 | {\r | |
636 | return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData));\r | |
637 | }\r | |
638 | \r | |
639 | /**\r | |
640 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
641 | value, followed a bitwise OR with another 16-bit value.\r | |
642 | \r | |
643 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
644 | bitwise AND between the read result and the value specified by AndData,\r | |
645 | performs a bitwise OR between the result of the AND operation and\r | |
646 | the value specified by OrData, and writes the result to the 16-bit PCI\r | |
647 | configuration register specified by Address. The value written to the PCI\r | |
648 | configuration register is returned. This function must guarantee that all PCI\r | |
649 | read and write operations are serialized.\r | |
650 | \r | |
651 | If any reserved bits in Address are set, then ASSERT().\r | |
652 | \r | |
653 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
654 | Register.\r | |
655 | @param AndData The value to AND with the PCI configuration register.\r | |
656 | @param OrData The value to OR with the result of the AND operation.\r | |
657 | \r | |
658 | @return The value written back to the PCI configuration register.\r | |
659 | \r | |
660 | **/\r | |
661 | UINT16\r | |
662 | EFIAPI\r | |
663 | PciSegmentAndThenOr16 (\r | |
664 | IN UINT64 Address,\r | |
665 | IN UINT16 AndData,\r | |
666 | IN UINT16 OrData\r | |
667 | )\r | |
668 | {\r | |
669 | return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData));\r | |
670 | }\r | |
671 | \r | |
672 | /**\r | |
673 | Reads a bit field of a PCI configuration register.\r | |
674 | \r | |
675 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
676 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
677 | returned.\r | |
678 | \r | |
679 | If any reserved bits in Address are set, then ASSERT().\r | |
680 | If StartBit is greater than 15, then ASSERT().\r | |
681 | If EndBit is greater than 15, then ASSERT().\r | |
682 | If EndBit is less than StartBit, then ASSERT().\r | |
683 | \r | |
684 | @param Address PCI configuration register to read.\r | |
685 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
686 | Range 0..15.\r | |
687 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
688 | Range 0..15.\r | |
689 | \r | |
690 | @return The value of the bit field read from the PCI configuration register.\r | |
691 | \r | |
692 | **/\r | |
693 | UINT16\r | |
694 | EFIAPI\r | |
695 | PciSegmentBitFieldRead16 (\r | |
696 | IN UINT64 Address,\r | |
697 | IN UINTN StartBit,\r | |
698 | IN UINTN EndBit\r | |
699 | )\r | |
700 | {\r | |
701 | return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);\r | |
702 | }\r | |
703 | \r | |
704 | /**\r | |
705 | Writes a bit field to a PCI configuration register.\r | |
706 | \r | |
707 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
708 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
709 | destination PCI configuration register are preserved. The new value of the\r | |
710 | 16-bit register is returned.\r | |
711 | \r | |
712 | If any reserved bits in Address are set, then ASSERT().\r | |
713 | If StartBit is greater than 15, then ASSERT().\r | |
714 | If EndBit is greater than 15, then ASSERT().\r | |
715 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 716 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
863be5d0 | 717 | \r |
718 | @param Address PCI configuration register to write.\r | |
719 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
720 | Range 0..15.\r | |
721 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
722 | Range 0..15.\r | |
723 | @param Value New value of the bit field.\r | |
724 | \r | |
725 | @return The value written back to the PCI configuration register.\r | |
726 | \r | |
727 | **/\r | |
728 | UINT16\r | |
729 | EFIAPI\r | |
730 | PciSegmentBitFieldWrite16 (\r | |
731 | IN UINT64 Address,\r | |
732 | IN UINTN StartBit,\r | |
733 | IN UINTN EndBit,\r | |
734 | IN UINT16 Value\r | |
735 | )\r | |
736 | {\r | |
737 | return PciSegmentWrite16 (\r | |
738 | Address,\r | |
739 | BitFieldWrite16 (PciSegmentRead16 (Address), StartBit, EndBit, Value)\r | |
740 | );\r | |
741 | }\r | |
742 | \r | |
743 | /**\r | |
744 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
745 | writes the result back to the bit field in the 16-bit port.\r | |
746 | \r | |
747 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
748 | bitwise OR between the read result and the value specified by\r | |
749 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
750 | specified by Address. The value written to the PCI configuration register is\r | |
751 | returned. This function must guarantee that all PCI read and write operations\r | |
752 | are serialized. Extra left bits in OrData are stripped.\r | |
753 | \r | |
754 | If any reserved bits in Address are set, then ASSERT().\r | |
755 | If StartBit is greater than 15, then ASSERT().\r | |
756 | If EndBit is greater than 15, then ASSERT().\r | |
757 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 758 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
863be5d0 | 759 | \r |
760 | @param Address PCI configuration register to write.\r | |
761 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
762 | Range 0..15.\r | |
763 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
764 | Range 0..15.\r | |
765 | @param OrData The value to OR with the PCI configuration register.\r | |
766 | \r | |
767 | @return The value written back to the PCI configuration register.\r | |
768 | \r | |
769 | **/\r | |
770 | UINT16\r | |
771 | EFIAPI\r | |
772 | PciSegmentBitFieldOr16 (\r | |
773 | IN UINT64 Address,\r | |
774 | IN UINTN StartBit,\r | |
775 | IN UINTN EndBit,\r | |
776 | IN UINT16 OrData\r | |
777 | )\r | |
778 | {\r | |
779 | return PciSegmentWrite16 (\r | |
780 | Address,\r | |
781 | BitFieldOr16 (PciSegmentRead16 (Address), StartBit, EndBit, OrData)\r | |
782 | );\r | |
783 | }\r | |
784 | \r | |
785 | /**\r | |
786 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
787 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
788 | \r | |
789 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
790 | bitwise AND between the read result and the value specified by AndData, and\r | |
791 | writes the result to the 16-bit PCI configuration register specified by\r | |
792 | Address. The value written to the PCI configuration register is returned.\r | |
793 | This function must guarantee that all PCI read and write operations are\r | |
794 | serialized. Extra left bits in AndData are stripped.\r | |
795 | \r | |
796 | If any reserved bits in Address are set, then ASSERT().\r | |
797 | If StartBit is greater than 15, then ASSERT().\r | |
798 | If EndBit is greater than 15, then ASSERT().\r | |
799 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 800 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
863be5d0 | 801 | \r |
802 | @param Address PCI configuration register to write.\r | |
803 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
804 | Range 0..15.\r | |
805 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
806 | Range 0..15.\r | |
807 | @param AndData The value to AND with the PCI configuration register.\r | |
808 | \r | |
809 | @return The value written back to the PCI configuration register.\r | |
810 | \r | |
811 | **/\r | |
812 | UINT16\r | |
813 | EFIAPI\r | |
814 | PciSegmentBitFieldAnd16 (\r | |
815 | IN UINT64 Address,\r | |
816 | IN UINTN StartBit,\r | |
817 | IN UINTN EndBit,\r | |
818 | IN UINT16 AndData\r | |
819 | )\r | |
820 | {\r | |
821 | return PciSegmentWrite16 (\r | |
822 | Address,\r | |
823 | BitFieldAnd16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData)\r | |
824 | );\r | |
825 | }\r | |
826 | \r | |
827 | /**\r | |
828 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
829 | bitwise OR, and writes the result back to the bit field in the\r | |
830 | 16-bit port.\r | |
831 | \r | |
832 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
833 | bitwise AND followed by a bitwise OR between the read result and\r | |
834 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
835 | configuration register specified by Address. The value written to the PCI\r | |
836 | configuration register is returned. This function must guarantee that all PCI\r | |
837 | read and write operations are serialized. Extra left bits in both AndData and\r | |
838 | OrData are stripped.\r | |
839 | \r | |
840 | If any reserved bits in Address are set, then ASSERT().\r | |
841 | If StartBit is greater than 15, then ASSERT().\r | |
842 | If EndBit is greater than 15, then ASSERT().\r | |
843 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
844 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
845 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
863be5d0 | 846 | \r |
847 | @param Address PCI configuration register to write.\r | |
848 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
849 | Range 0..15.\r | |
850 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
851 | Range 0..15.\r | |
852 | @param AndData The value to AND with the PCI configuration register.\r | |
853 | @param OrData The value to OR with the result of the AND operation.\r | |
854 | \r | |
855 | @return The value written back to the PCI configuration register.\r | |
856 | \r | |
857 | **/\r | |
858 | UINT16\r | |
859 | EFIAPI\r | |
860 | PciSegmentBitFieldAndThenOr16 (\r | |
861 | IN UINT64 Address,\r | |
862 | IN UINTN StartBit,\r | |
863 | IN UINTN EndBit,\r | |
864 | IN UINT16 AndData,\r | |
865 | IN UINT16 OrData\r | |
866 | )\r | |
867 | {\r | |
868 | return PciSegmentWrite16 (\r | |
869 | Address,\r | |
870 | BitFieldAndThenOr16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData, OrData)\r | |
871 | );\r | |
872 | }\r | |
873 | \r | |
874 | /**\r | |
875 | Reads a 32-bit PCI configuration register.\r | |
876 | \r | |
877 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
878 | This function must guarantee that all PCI read and write operations are\r | |
879 | serialized.\r | |
880 | \r | |
881 | If any reserved bits in Address are set, then ASSERT().\r | |
882 | \r | |
883 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
884 | Register.\r | |
885 | \r | |
886 | @return The value read from the PCI configuration register.\r | |
887 | \r | |
888 | **/\r | |
889 | UINT32\r | |
890 | EFIAPI\r | |
891 | PciSegmentRead32 (\r | |
892 | IN UINT64 Address\r | |
893 | )\r | |
894 | {\r | |
895 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);\r | |
896 | \r | |
897 | return DxePciSegmentLibEsalReadWorker (Address, 4);\r | |
898 | }\r | |
899 | \r | |
900 | /**\r | |
901 | Writes a 32-bit PCI configuration register.\r | |
902 | \r | |
903 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
904 | value specified by Value. Value is returned. This function must guarantee\r | |
905 | that all PCI read and write operations are serialized.\r | |
906 | \r | |
907 | If any reserved bits in Address are set, then ASSERT().\r | |
908 | \r | |
909 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
910 | Register.\r | |
911 | @param Data The value to write.\r | |
912 | \r | |
913 | @return The value written to the PCI configuration register.\r | |
914 | \r | |
915 | **/\r | |
916 | UINT32\r | |
917 | EFIAPI\r | |
918 | PciSegmentWrite32 (\r | |
919 | IN UINT64 Address,\r | |
920 | IN UINT32 Data\r | |
921 | )\r | |
922 | {\r | |
923 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);\r | |
924 | \r | |
925 | return DxePciSegmentLibEsalWriteWorker (Address, 4, Data);\r | |
926 | }\r | |
927 | \r | |
928 | /**\r | |
929 | Performs a bitwise OR of a 32-bit PCI configuration register with\r | |
930 | a 32-bit value.\r | |
931 | \r | |
932 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
933 | bitwise OR between the read result and the value specified by\r | |
934 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
935 | specified by Address. The value written to the PCI configuration register is\r | |
936 | returned. This function must guarantee that all PCI read and write operations\r | |
937 | are serialized.\r | |
938 | \r | |
939 | If any reserved bits in Address are set, then ASSERT().\r | |
940 | \r | |
941 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
942 | Register.\r | |
943 | @param OrData The value to OR with the PCI configuration register.\r | |
944 | \r | |
945 | @return The value written back to the PCI configuration register.\r | |
946 | \r | |
947 | **/\r | |
948 | UINT32\r | |
949 | EFIAPI\r | |
950 | PciSegmentOr32 (\r | |
951 | IN UINT64 Address,\r | |
952 | IN UINT32 OrData\r | |
953 | )\r | |
954 | {\r | |
955 | return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);\r | |
956 | }\r | |
957 | \r | |
958 | /**\r | |
959 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
960 | value.\r | |
961 | \r | |
962 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
963 | bitwise AND between the read result and the value specified by AndData, and\r | |
964 | writes the result to the 32-bit PCI configuration register specified by\r | |
965 | Address. The value written to the PCI configuration register is returned.\r | |
966 | This function must guarantee that all PCI read and write operations are\r | |
967 | serialized.\r | |
968 | \r | |
969 | If any reserved bits in Address are set, then ASSERT().\r | |
970 | \r | |
971 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
972 | Register.\r | |
973 | @param AndData The value to AND with the PCI configuration register.\r | |
974 | \r | |
975 | @return The value written back to the PCI configuration register.\r | |
976 | \r | |
977 | **/\r | |
978 | UINT32\r | |
979 | EFIAPI\r | |
980 | PciSegmentAnd32 (\r | |
981 | IN UINT64 Address,\r | |
982 | IN UINT32 AndData\r | |
983 | )\r | |
984 | {\r | |
985 | return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);\r | |
986 | }\r | |
987 | \r | |
988 | /**\r | |
989 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
990 | value, followed a bitwise OR with another 32-bit value.\r | |
991 | \r | |
992 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
993 | bitwise AND between the read result and the value specified by AndData,\r | |
994 | performs a bitwise OR between the result of the AND operation and\r | |
995 | the value specified by OrData, and writes the result to the 32-bit PCI\r | |
996 | configuration register specified by Address. The value written to the PCI\r | |
997 | configuration register is returned. This function must guarantee that all PCI\r | |
998 | read and write operations are serialized.\r | |
999 | \r | |
1000 | If any reserved bits in Address are set, then ASSERT().\r | |
1001 | \r | |
1002 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
1003 | Register.\r | |
1004 | @param AndData The value to AND with the PCI configuration register.\r | |
1005 | @param OrData The value to OR with the result of the AND operation.\r | |
1006 | \r | |
1007 | @return The value written back to the PCI configuration register.\r | |
1008 | \r | |
1009 | **/\r | |
1010 | UINT32\r | |
1011 | EFIAPI\r | |
1012 | PciSegmentAndThenOr32 (\r | |
1013 | IN UINT64 Address,\r | |
1014 | IN UINT32 AndData,\r | |
1015 | IN UINT32 OrData\r | |
1016 | )\r | |
1017 | {\r | |
1018 | return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData);\r | |
1019 | }\r | |
1020 | \r | |
1021 | /**\r | |
1022 | Reads a bit field of a PCI configuration register.\r | |
1023 | \r | |
1024 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
1025 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
1026 | returned.\r | |
1027 | \r | |
1028 | If any reserved bits in Address are set, then ASSERT().\r | |
1029 | If StartBit is greater than 31, then ASSERT().\r | |
1030 | If EndBit is greater than 31, then ASSERT().\r | |
1031 | If EndBit is less than StartBit, then ASSERT().\r | |
1032 | \r | |
1033 | @param Address PCI configuration register to read.\r | |
1034 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1035 | Range 0..31.\r | |
1036 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1037 | Range 0..31.\r | |
1038 | \r | |
1039 | @return The value of the bit field read from the PCI configuration register.\r | |
1040 | \r | |
1041 | **/\r | |
1042 | UINT32\r | |
1043 | EFIAPI\r | |
1044 | PciSegmentBitFieldRead32 (\r | |
1045 | IN UINT64 Address,\r | |
1046 | IN UINTN StartBit,\r | |
1047 | IN UINTN EndBit\r | |
1048 | )\r | |
1049 | {\r | |
1050 | return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);\r | |
1051 | }\r | |
1052 | \r | |
1053 | /**\r | |
1054 | Writes a bit field to a PCI configuration register.\r | |
1055 | \r | |
1056 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
1057 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
1058 | destination PCI configuration register are preserved. The new value of the\r | |
1059 | 32-bit register is returned.\r | |
1060 | \r | |
1061 | If any reserved bits in Address are set, then ASSERT().\r | |
1062 | If StartBit is greater than 31, then ASSERT().\r | |
1063 | If EndBit is greater than 31, then ASSERT().\r | |
1064 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 1065 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
863be5d0 | 1066 | \r |
1067 | @param Address PCI configuration register to write.\r | |
1068 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1069 | Range 0..31.\r | |
1070 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1071 | Range 0..31.\r | |
1072 | @param Value New value of the bit field.\r | |
1073 | \r | |
1074 | @return The value written back to the PCI configuration register.\r | |
1075 | \r | |
1076 | **/\r | |
1077 | UINT32\r | |
1078 | EFIAPI\r | |
1079 | PciSegmentBitFieldWrite32 (\r | |
1080 | IN UINT64 Address,\r | |
1081 | IN UINTN StartBit,\r | |
1082 | IN UINTN EndBit,\r | |
1083 | IN UINT32 Value\r | |
1084 | )\r | |
1085 | {\r | |
1086 | return PciSegmentWrite32 (\r | |
1087 | Address,\r | |
1088 | BitFieldWrite32 (PciSegmentRead32 (Address), StartBit, EndBit, Value)\r | |
1089 | );\r | |
1090 | }\r | |
1091 | \r | |
1092 | /**\r | |
1093 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
1094 | writes the result back to the bit field in the 32-bit port.\r | |
1095 | \r | |
1096 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1097 | bitwise OR between the read result and the value specified by\r | |
1098 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
1099 | specified by Address. The value written to the PCI configuration register is\r | |
1100 | returned. This function must guarantee that all PCI read and write operations\r | |
1101 | are serialized. Extra left bits in OrData are stripped.\r | |
1102 | \r | |
1103 | If any reserved bits in Address are set, then ASSERT().\r | |
1104 | If StartBit is greater than 31, then ASSERT().\r | |
1105 | If EndBit is greater than 31, then ASSERT().\r | |
1106 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 1107 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
863be5d0 | 1108 | \r |
1109 | @param Address PCI configuration register to write.\r | |
1110 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1111 | Range 0..31.\r | |
1112 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1113 | Range 0..31.\r | |
1114 | @param OrData The value to OR with the PCI configuration register.\r | |
1115 | \r | |
1116 | @return The value written back to the PCI configuration register.\r | |
1117 | \r | |
1118 | **/\r | |
1119 | UINT32\r | |
1120 | EFIAPI\r | |
1121 | PciSegmentBitFieldOr32 (\r | |
1122 | IN UINT64 Address,\r | |
1123 | IN UINTN StartBit,\r | |
1124 | IN UINTN EndBit,\r | |
1125 | IN UINT32 OrData\r | |
1126 | )\r | |
1127 | {\r | |
1128 | return PciSegmentWrite32 (\r | |
1129 | Address,\r | |
1130 | BitFieldOr32 (PciSegmentRead32 (Address), StartBit, EndBit, OrData)\r | |
1131 | );\r | |
1132 | }\r | |
1133 | \r | |
1134 | /**\r | |
1135 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
1136 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
1137 | \r | |
1138 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1139 | bitwise AND between the read result and the value specified by AndData, and\r | |
1140 | writes the result to the 32-bit PCI configuration register specified by\r | |
1141 | Address. The value written to the PCI configuration register is returned.\r | |
1142 | This function must guarantee that all PCI read and write operations are\r | |
1143 | serialized. Extra left bits in AndData are stripped.\r | |
1144 | \r | |
1145 | If any reserved bits in Address are set, then ASSERT().\r | |
1146 | If StartBit is greater than 31, then ASSERT().\r | |
1147 | If EndBit is greater than 31, then ASSERT().\r | |
1148 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 1149 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
863be5d0 | 1150 | \r |
1151 | @param Address PCI configuration register to write.\r | |
1152 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1153 | Range 0..31.\r | |
1154 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1155 | Range 0..31.\r | |
1156 | @param AndData The value to AND with the PCI configuration register.\r | |
1157 | \r | |
1158 | @return The value written back to the PCI configuration register.\r | |
1159 | \r | |
1160 | **/\r | |
1161 | UINT32\r | |
1162 | EFIAPI\r | |
1163 | PciSegmentBitFieldAnd32 (\r | |
1164 | IN UINT64 Address,\r | |
1165 | IN UINTN StartBit,\r | |
1166 | IN UINTN EndBit,\r | |
1167 | IN UINT32 AndData\r | |
1168 | )\r | |
1169 | {\r | |
1170 | return PciSegmentWrite32 (\r | |
1171 | Address,\r | |
1172 | BitFieldAnd32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData)\r | |
1173 | );\r | |
1174 | }\r | |
1175 | \r | |
1176 | /**\r | |
1177 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
1178 | bitwise OR, and writes the result back to the bit field in the\r | |
1179 | 32-bit port.\r | |
1180 | \r | |
1181 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1182 | bitwise AND followed by a bitwise OR between the read result and\r | |
1183 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
1184 | configuration register specified by Address. The value written to the PCI\r | |
1185 | configuration register is returned. This function must guarantee that all PCI\r | |
1186 | read and write operations are serialized. Extra left bits in both AndData and\r | |
1187 | OrData are stripped.\r | |
1188 | \r | |
1189 | If any reserved bits in Address are set, then ASSERT().\r | |
1190 | If StartBit is greater than 31, then ASSERT().\r | |
1191 | If EndBit is greater than 31, then ASSERT().\r | |
1192 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
1193 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1194 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
863be5d0 | 1195 | \r |
1196 | @param Address PCI configuration register to write.\r | |
1197 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1198 | Range 0..31.\r | |
1199 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1200 | Range 0..31.\r | |
1201 | @param AndData The value to AND with the PCI configuration register.\r | |
1202 | @param OrData The value to OR with the result of the AND operation.\r | |
1203 | \r | |
1204 | @return The value written back to the PCI configuration register.\r | |
1205 | \r | |
1206 | **/\r | |
1207 | UINT32\r | |
1208 | EFIAPI\r | |
1209 | PciSegmentBitFieldAndThenOr32 (\r | |
1210 | IN UINT64 Address,\r | |
1211 | IN UINTN StartBit,\r | |
1212 | IN UINTN EndBit,\r | |
1213 | IN UINT32 AndData,\r | |
1214 | IN UINT32 OrData\r | |
1215 | )\r | |
1216 | {\r | |
1217 | return PciSegmentWrite32 (\r | |
1218 | Address,\r | |
1219 | BitFieldAndThenOr32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData, OrData)\r | |
1220 | );\r | |
1221 | }\r | |
1222 | \r | |
1223 | /**\r | |
1224 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
1225 | \r | |
1226 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
1227 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1228 | configuration registers from a single PCI function to be read. Size is\r | |
1229 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
1230 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
1231 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
1232 | end of the range.\r | |
1233 | \r | |
1234 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1235 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1236 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1237 | \r | |
1238 | @param StartAddress Starting Address that encodes the PCI Segment, Bus, Device,\r | |
1239 | Function and Register.\r | |
1240 | @param Size Size in bytes of the transfer.\r | |
1241 | @param Buffer Pointer to a buffer receiving the data read.\r | |
1242 | \r | |
1243 | @return Size\r | |
1244 | \r | |
1245 | **/\r | |
1246 | UINTN\r | |
1247 | EFIAPI\r | |
1248 | PciSegmentReadBuffer (\r | |
1249 | IN UINT64 StartAddress,\r | |
1250 | IN UINTN Size,\r | |
1251 | OUT VOID *Buffer\r | |
1252 | )\r | |
1253 | {\r | |
1254 | UINTN ReturnValue;\r | |
1255 | \r | |
1256 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);\r | |
1257 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r | |
1258 | \r | |
1259 | if (Size == 0) {\r | |
1260 | return Size;\r | |
1261 | }\r | |
1262 | \r | |
1263 | ASSERT (Buffer != NULL);\r | |
1264 | \r | |
1265 | //\r | |
1266 | // Save Size for return\r | |
1267 | //\r | |
1268 | ReturnValue = Size;\r | |
1269 | \r | |
1270 | if ((StartAddress & 1) != 0) {\r | |
1271 | //\r | |
1272 | // Read a byte if StartAddress is byte aligned\r | |
1273 | //\r | |
1274 | *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);\r | |
1275 | StartAddress += sizeof (UINT8);\r | |
1276 | Size -= sizeof (UINT8);\r | |
1277 | Buffer = (UINT8*)Buffer + 1;\r | |
1278 | }\r | |
1279 | \r | |
1280 | if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r | |
1281 | //\r | |
1282 | // Read a word if StartAddress is word aligned\r | |
1283 | //\r | |
1284 | *(volatile UINT16 *)Buffer = PciSegmentRead16 (StartAddress);\r | |
1285 | StartAddress += sizeof (UINT16);\r | |
1286 | Size -= sizeof (UINT16);\r | |
1287 | Buffer = (UINT16*)Buffer + 1;\r | |
1288 | }\r | |
1289 | \r | |
1290 | while (Size >= sizeof (UINT32)) {\r | |
1291 | //\r | |
1292 | // Read as many double words as possible\r | |
1293 | //\r | |
1294 | *(volatile UINT32 *)Buffer = PciSegmentRead32 (StartAddress);\r | |
1295 | StartAddress += sizeof (UINT32);\r | |
1296 | Size -= sizeof (UINT32);\r | |
1297 | Buffer = (UINT32*)Buffer + 1;\r | |
1298 | }\r | |
1299 | \r | |
1300 | if (Size >= sizeof (UINT16)) {\r | |
1301 | //\r | |
1302 | // Read the last remaining word if exist\r | |
1303 | //\r | |
1304 | *(volatile UINT16 *)Buffer = PciSegmentRead16 (StartAddress);\r | |
1305 | StartAddress += sizeof (UINT16);\r | |
1306 | Size -= sizeof (UINT16);\r | |
1307 | Buffer = (UINT16*)Buffer + 1;\r | |
1308 | }\r | |
1309 | \r | |
1310 | if (Size >= sizeof (UINT8)) {\r | |
1311 | //\r | |
1312 | // Read the last remaining byte if exist\r | |
1313 | //\r | |
1314 | *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);\r | |
1315 | }\r | |
1316 | \r | |
1317 | return ReturnValue;\r | |
1318 | }\r | |
1319 | \r | |
1320 | /**\r | |
1321 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1322 | configuration space.\r | |
1323 | \r | |
1324 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1325 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1326 | configuration registers from a single PCI function to be written. Size is\r | |
1327 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1328 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1329 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1330 | and the end of the range.\r | |
1331 | \r | |
1332 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1333 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1334 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1335 | \r | |
1336 | @param StartAddress Starting Address that encodes the PCI Segment, Bus, Device,\r | |
1337 | Function and Register.\r | |
1338 | @param Size Size in bytes of the transfer.\r | |
1339 | @param Buffer Pointer to a buffer containing the data to write.\r | |
1340 | \r | |
1341 | @return Size\r | |
1342 | \r | |
1343 | **/\r | |
1344 | UINTN\r | |
1345 | EFIAPI\r | |
1346 | PciSegmentWriteBuffer (\r | |
1347 | IN UINT64 StartAddress,\r | |
1348 | IN UINTN Size,\r | |
1349 | IN VOID *Buffer\r | |
1350 | )\r | |
1351 | {\r | |
1352 | UINTN ReturnValue;\r | |
1353 | \r | |
1354 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);\r | |
1355 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r | |
1356 | \r | |
1357 | if (Size == 0) {\r | |
1358 | return 0;\r | |
1359 | }\r | |
1360 | \r | |
1361 | ASSERT (Buffer != NULL);\r | |
1362 | \r | |
1363 | //\r | |
1364 | // Save Size for return\r | |
1365 | //\r | |
1366 | ReturnValue = Size;\r | |
1367 | \r | |
1368 | if ((StartAddress & 1) != 0) {\r | |
1369 | //\r | |
1370 | // Write a byte if StartAddress is byte aligned\r | |
1371 | //\r | |
1372 | PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1373 | StartAddress += sizeof (UINT8);\r | |
1374 | Size -= sizeof (UINT8);\r | |
1375 | Buffer = (UINT8*)Buffer + 1;\r | |
1376 | }\r | |
1377 | \r | |
1378 | if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r | |
1379 | //\r | |
1380 | // Write a word if StartAddress is word aligned\r | |
1381 | //\r | |
1382 | PciSegmentWrite16 (StartAddress, *(UINT16*)Buffer);\r | |
1383 | StartAddress += sizeof (UINT16);\r | |
1384 | Size -= sizeof (UINT16);\r | |
1385 | Buffer = (UINT16*)Buffer + 1;\r | |
1386 | }\r | |
1387 | \r | |
1388 | while (Size >= sizeof (UINT32)) {\r | |
1389 | //\r | |
1390 | // Write as many double words as possible\r | |
1391 | //\r | |
1392 | PciSegmentWrite32 (StartAddress, *(UINT32*)Buffer);\r | |
1393 | StartAddress += sizeof (UINT32);\r | |
1394 | Size -= sizeof (UINT32);\r | |
1395 | Buffer = (UINT32*)Buffer + 1;\r | |
1396 | }\r | |
1397 | \r | |
1398 | if (Size >= sizeof (UINT16)) {\r | |
1399 | //\r | |
1400 | // Write the last remaining word if exist\r | |
1401 | //\r | |
1402 | PciSegmentWrite16 (StartAddress, *(UINT16*)Buffer);\r | |
1403 | StartAddress += sizeof (UINT16);\r | |
1404 | Size -= sizeof (UINT16);\r | |
1405 | Buffer = (UINT16*)Buffer + 1;\r | |
1406 | }\r | |
1407 | \r | |
1408 | if (Size >= sizeof (UINT8)) {\r | |
1409 | //\r | |
1410 | // Write the last remaining byte if exist\r | |
1411 | //\r | |
1412 | PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1413 | }\r | |
1414 | \r | |
1415 | return ReturnValue;\r | |
1416 | }\r |