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1a3eaf06 | 1 | /** @file\r |
2 | PCI Library using PCI CFG2 PPI.\r | |
3 | \r | |
94952554 | 4 | Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>\r |
19388d29 | 5 | This program and the accompanying materials are\r |
1a3eaf06 | 6 | licensed and made available under the terms and conditions of\r |
7 | the BSD License which accompanies this distribution. The full\r | |
8 | text of the license may be found at\r | |
2fc59a00 | 9 | http://opensource.org/licenses/bsd-license.php.\r |
1a3eaf06 | 10 | \r |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #include <PiPei.h>\r | |
17 | \r | |
18 | #include <Ppi/PciCfg2.h>\r | |
19 | \r | |
20 | #include <Library/PciLib.h>\r | |
21 | #include <Library/BaseLib.h>\r | |
22 | #include <Library/PeiServicesTablePointerLib.h>\r | |
23 | #include <Library/DebugLib.h>\r | |
24 | #include <Library/PeiServicesLib.h>\r | |
25 | \r | |
26 | /**\r | |
27 | Assert the validity of a PCI address. A valid PCI address should contain 1's\r | |
28 | only in the low 28 bits.\r | |
29 | \r | |
30 | @param A The address to validate.\r | |
31 | @param M Additional bits to assert to be zero.\r | |
32 | \r | |
33 | **/\r | |
34 | #define ASSERT_INVALID_PCI_ADDRESS(A,M) \\r | |
35 | ASSERT (((A) & (~0xfffffff | (M))) == 0)\r | |
36 | \r | |
37 | /**\r | |
38 | Translate PCI Lib address into format of PCI CFG2 PPI.\r | |
39 | \r | |
2fc59a00 | 40 | @param A The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 41 | Register.\r |
42 | \r | |
43 | **/\r | |
44 | #define PCI_TO_PCICFG2_ADDRESS(A) \\r | |
e43e4b3e | 45 | ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))\r |
1a3eaf06 | 46 | \r |
47 | /**\r | |
48 | Internal worker function to read a PCI configuration register.\r | |
49 | \r | |
50 | This function wraps EFI_PEI_PCI_CFG2_PPI.Read() service.\r | |
51 | It reads and returns the PCI configuration register specified by Address,\r | |
52 | the width of data is specified by Width.\r | |
53 | \r | |
2fc59a00 | 54 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 55 | Register.\r |
58380e9c | 56 | @param Width The width of data to read\r |
1a3eaf06 | 57 | \r |
58 | @return The value read from the PCI configuration register.\r | |
59 | \r | |
60 | **/\r | |
61 | UINT32\r | |
62 | PeiPciLibPciCfg2ReadWorker (\r | |
63 | IN UINTN Address,\r | |
64 | IN EFI_PEI_PCI_CFG_PPI_WIDTH Width\r | |
65 | )\r | |
66 | {\r | |
67 | EFI_STATUS Status;\r | |
68 | UINT32 Data;\r | |
69 | CONST EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r | |
43fe5cdc | 70 | UINT64 PciCfg2Address;\r |
1a3eaf06 | 71 | \r |
72 | Status = PeiServicesLocatePpi (&gEfiPciCfg2PpiGuid, 0, NULL, (VOID **) &PciCfg2Ppi);\r | |
73 | ASSERT_EFI_ERROR (Status);\r | |
74 | ASSERT (PciCfg2Ppi != NULL);\r | |
75 | \r | |
43fe5cdc | 76 | PciCfg2Address = PCI_TO_PCICFG2_ADDRESS (Address);\r |
1a3eaf06 | 77 | PciCfg2Ppi->Read (\r |
78 | GetPeiServicesTablePointer (),\r | |
79 | PciCfg2Ppi,\r | |
80 | Width,\r | |
43fe5cdc | 81 | PciCfg2Address,\r |
1a3eaf06 | 82 | &Data\r |
83 | );\r | |
84 | \r | |
85 | return Data;\r | |
86 | }\r | |
87 | \r | |
88 | /**\r | |
89 | Internal worker function to writes a PCI configuration register.\r | |
90 | \r | |
91 | This function wraps EFI_PEI_PCI_CFG2_PPI.Write() service.\r | |
92 | It writes the PCI configuration register specified by Address with the\r | |
93 | value specified by Data. The width of data is specifed by Width.\r | |
94 | Data is returned.\r | |
95 | \r | |
2fc59a00 | 96 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 97 | Register.\r |
58380e9c | 98 | @param Width The width of data to write\r |
1a3eaf06 | 99 | @param Data The value to write.\r |
100 | \r | |
101 | @return The value written to the PCI configuration register.\r | |
102 | \r | |
103 | **/\r | |
104 | UINT32\r | |
105 | PeiPciLibPciCfg2WriteWorker (\r | |
106 | IN UINTN Address,\r | |
107 | IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r | |
108 | IN UINT32 Data\r | |
109 | )\r | |
110 | {\r | |
111 | EFI_STATUS Status;\r | |
112 | CONST EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r | |
43fe5cdc | 113 | UINT64 PciCfg2Address;\r |
1a3eaf06 | 114 | \r |
115 | Status = PeiServicesLocatePpi (&gEfiPciCfg2PpiGuid, 0, NULL, (VOID **) &PciCfg2Ppi);\r | |
116 | ASSERT_EFI_ERROR (Status);\r | |
117 | ASSERT (PciCfg2Ppi != NULL);\r | |
118 | \r | |
43fe5cdc | 119 | PciCfg2Address = PCI_TO_PCICFG2_ADDRESS (Address);\r |
1a3eaf06 | 120 | PciCfg2Ppi->Write (\r |
121 | GetPeiServicesTablePointer (),\r | |
122 | PciCfg2Ppi,\r | |
123 | Width,\r | |
43fe5cdc | 124 | PciCfg2Address,\r |
1a3eaf06 | 125 | &Data\r |
126 | );\r | |
127 | \r | |
128 | return Data;\r | |
129 | }\r | |
130 | \r | |
3e3ae634 | 131 | /**\r |
d11195a3 | 132 | Registers a PCI device so PCI configuration registers may be accessed after \r |
3e3ae634 | 133 | SetVirtualAddressMap().\r |
134 | \r | |
d11195a3 | 135 | Registers the PCI device specified by Address so all the PCI configuration registers \r |
136 | associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r | |
137 | \r | |
3e3ae634 | 138 | If Address > 0x0FFFFFFF, then ASSERT().\r |
139 | \r | |
2fc59a00 | 140 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
3e3ae634 | 141 | Register.\r |
142 | \r | |
143 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r | |
144 | @retval RETURN_UNSUPPORTED An attempt was made to call this function \r | |
145 | after ExitBootServices().\r | |
146 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
147 | at runtime could not be mapped.\r | |
148 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
149 | complete the registration.\r | |
150 | \r | |
151 | **/\r | |
152 | RETURN_STATUS\r | |
153 | EFIAPI\r | |
154 | PciRegisterForRuntimeAccess (\r | |
155 | IN UINTN Address\r | |
156 | )\r | |
157 | {\r | |
59ceeabe | 158 | ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r |
3e3ae634 | 159 | return RETURN_UNSUPPORTED;\r |
160 | }\r | |
161 | \r | |
1a3eaf06 | 162 | /**\r |
163 | Reads an 8-bit PCI configuration register.\r | |
164 | \r | |
165 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
166 | This function must guarantee that all PCI read and write operations are\r | |
167 | serialized.\r | |
168 | \r | |
169 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
170 | \r | |
2fc59a00 | 171 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 172 | Register.\r |
173 | \r | |
0c3437e0 | 174 | @return The read value from the PCI configuration register.\r |
1a3eaf06 | 175 | \r |
176 | **/\r | |
177 | UINT8\r | |
178 | EFIAPI\r | |
179 | PciRead8 (\r | |
180 | IN UINTN Address\r | |
181 | )\r | |
182 | {\r | |
183 | ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r | |
184 | \r | |
185 | return (UINT8) PeiPciLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint8);\r | |
186 | }\r | |
187 | \r | |
188 | /**\r | |
189 | Writes an 8-bit PCI configuration register.\r | |
190 | \r | |
191 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
192 | value specified by Value. Value is returned. This function must guarantee\r | |
193 | that all PCI read and write operations are serialized.\r | |
194 | \r | |
195 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
196 | \r | |
2fc59a00 | 197 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 198 | Register.\r |
0c3437e0 | 199 | @param Value The value to write.\r |
1a3eaf06 | 200 | \r |
201 | @return The value written to the PCI configuration register.\r | |
202 | \r | |
203 | **/\r | |
204 | UINT8\r | |
205 | EFIAPI\r | |
206 | PciWrite8 (\r | |
207 | IN UINTN Address,\r | |
0c3437e0 | 208 | IN UINT8 Value\r |
1a3eaf06 | 209 | )\r |
210 | {\r | |
211 | ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r | |
212 | \r | |
0c3437e0 | 213 | return (UINT8) PeiPciLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint8, Value);\r |
1a3eaf06 | 214 | }\r |
215 | \r | |
216 | /**\r | |
62991af2 | 217 | Performs a bitwise OR of an 8-bit PCI configuration register with\r |
1a3eaf06 | 218 | an 8-bit value.\r |
219 | \r | |
220 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 221 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 222 | OrData, and writes the result to the 8-bit PCI configuration register\r |
223 | specified by Address. The value written to the PCI configuration register is\r | |
224 | returned. This function must guarantee that all PCI read and write operations\r | |
225 | are serialized.\r | |
226 | \r | |
227 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
228 | \r | |
2fc59a00 | 229 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 230 | Register.\r |
231 | @param OrData The value to OR with the PCI configuration register.\r | |
232 | \r | |
233 | @return The value written back to the PCI configuration register.\r | |
234 | \r | |
235 | **/\r | |
236 | UINT8\r | |
237 | EFIAPI\r | |
238 | PciOr8 (\r | |
239 | IN UINTN Address,\r | |
240 | IN UINT8 OrData\r | |
241 | )\r | |
242 | {\r | |
243 | return PciWrite8 (Address, (UINT8) (PciRead8 (Address) | OrData));\r | |
244 | }\r | |
245 | \r | |
246 | /**\r | |
247 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
248 | value.\r | |
249 | \r | |
250 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
251 | bitwise AND between the read result and the value specified by AndData, and\r | |
252 | writes the result to the 8-bit PCI configuration register specified by\r | |
253 | Address. The value written to the PCI configuration register is returned.\r | |
254 | This function must guarantee that all PCI read and write operations are\r | |
255 | serialized.\r | |
256 | \r | |
257 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
258 | \r | |
2fc59a00 | 259 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 260 | Register.\r |
261 | @param AndData The value to AND with the PCI configuration register.\r | |
262 | \r | |
263 | @return The value written back to the PCI configuration register.\r | |
264 | \r | |
265 | **/\r | |
266 | UINT8\r | |
267 | EFIAPI\r | |
268 | PciAnd8 (\r | |
269 | IN UINTN Address,\r | |
270 | IN UINT8 AndData\r | |
271 | )\r | |
272 | {\r | |
273 | return PciWrite8 (Address, (UINT8) (PciRead8 (Address) & AndData));\r | |
274 | }\r | |
275 | \r | |
276 | /**\r | |
277 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
62991af2 | 278 | value, followed a bitwise OR with another 8-bit value.\r |
1a3eaf06 | 279 | \r |
280 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
281 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 282 | performs a bitwise OR between the result of the AND operation and\r |
1a3eaf06 | 283 | the value specified by OrData, and writes the result to the 8-bit PCI\r |
284 | configuration register specified by Address. The value written to the PCI\r | |
285 | configuration register is returned. This function must guarantee that all PCI\r | |
286 | read and write operations are serialized.\r | |
287 | \r | |
288 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
289 | \r | |
2fc59a00 | 290 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 291 | Register.\r |
292 | @param AndData The value to AND with the PCI configuration register.\r | |
293 | @param OrData The value to OR with the result of the AND operation.\r | |
294 | \r | |
295 | @return The value written back to the PCI configuration register.\r | |
296 | \r | |
297 | **/\r | |
298 | UINT8\r | |
299 | EFIAPI\r | |
300 | PciAndThenOr8 (\r | |
301 | IN UINTN Address,\r | |
302 | IN UINT8 AndData,\r | |
303 | IN UINT8 OrData\r | |
304 | )\r | |
305 | {\r | |
306 | return PciWrite8 (Address, (UINT8) ((PciRead8 (Address) & AndData) | OrData));\r | |
307 | }\r | |
308 | \r | |
309 | /**\r | |
310 | Reads a bit field of a PCI configuration register.\r | |
311 | \r | |
312 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
313 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
314 | returned.\r | |
315 | \r | |
316 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
317 | If StartBit is greater than 7, then ASSERT().\r | |
318 | If EndBit is greater than 7, then ASSERT().\r | |
319 | If EndBit is less than StartBit, then ASSERT().\r | |
320 | \r | |
2fc59a00 | 321 | @param Address The PCI configuration register to read.\r |
1a3eaf06 | 322 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
323 | Range 0..7.\r | |
324 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
325 | Range 0..7.\r | |
326 | \r | |
327 | @return The value of the bit field read from the PCI configuration register.\r | |
328 | \r | |
329 | **/\r | |
330 | UINT8\r | |
331 | EFIAPI\r | |
332 | PciBitFieldRead8 (\r | |
333 | IN UINTN Address,\r | |
334 | IN UINTN StartBit,\r | |
335 | IN UINTN EndBit\r | |
336 | )\r | |
337 | {\r | |
338 | return BitFieldRead8 (PciRead8 (Address), StartBit, EndBit);\r | |
339 | }\r | |
340 | \r | |
341 | /**\r | |
342 | Writes a bit field to a PCI configuration register.\r | |
343 | \r | |
344 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
345 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
346 | destination PCI configuration register are preserved. The new value of the\r | |
347 | 8-bit register is returned.\r | |
348 | \r | |
349 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
350 | If StartBit is greater than 7, then ASSERT().\r | |
351 | If EndBit is greater than 7, then ASSERT().\r | |
352 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 353 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1a3eaf06 | 354 | \r |
2fc59a00 | 355 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 356 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
357 | Range 0..7.\r | |
358 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
359 | Range 0..7.\r | |
2fc59a00 | 360 | @param Value The new value of the bit field.\r |
1a3eaf06 | 361 | \r |
362 | @return The value written back to the PCI configuration register.\r | |
363 | \r | |
364 | **/\r | |
365 | UINT8\r | |
366 | EFIAPI\r | |
367 | PciBitFieldWrite8 (\r | |
368 | IN UINTN Address,\r | |
369 | IN UINTN StartBit,\r | |
370 | IN UINTN EndBit,\r | |
371 | IN UINT8 Value\r | |
372 | )\r | |
373 | {\r | |
374 | return PciWrite8 (\r | |
375 | Address,\r | |
376 | BitFieldWrite8 (PciRead8 (Address), StartBit, EndBit, Value)\r | |
377 | );\r | |
378 | }\r | |
379 | \r | |
380 | /**\r | |
381 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
382 | writes the result back to the bit field in the 8-bit port.\r | |
383 | \r | |
384 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 385 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 386 | OrData, and writes the result to the 8-bit PCI configuration register\r |
387 | specified by Address. The value written to the PCI configuration register is\r | |
388 | returned. This function must guarantee that all PCI read and write operations\r | |
389 | are serialized. Extra left bits in OrData are stripped.\r | |
390 | \r | |
391 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
392 | If StartBit is greater than 7, then ASSERT().\r | |
393 | If EndBit is greater than 7, then ASSERT().\r | |
394 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 395 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1a3eaf06 | 396 | \r |
2fc59a00 | 397 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 398 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
399 | Range 0..7.\r | |
400 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
401 | Range 0..7.\r | |
402 | @param OrData The value to OR with the PCI configuration register.\r | |
403 | \r | |
404 | @return The value written back to the PCI configuration register.\r | |
405 | \r | |
406 | **/\r | |
407 | UINT8\r | |
408 | EFIAPI\r | |
409 | PciBitFieldOr8 (\r | |
410 | IN UINTN Address,\r | |
411 | IN UINTN StartBit,\r | |
412 | IN UINTN EndBit,\r | |
413 | IN UINT8 OrData\r | |
414 | )\r | |
415 | {\r | |
416 | return PciWrite8 (\r | |
417 | Address,\r | |
418 | BitFieldOr8 (PciRead8 (Address), StartBit, EndBit, OrData)\r | |
419 | );\r | |
420 | }\r | |
421 | \r | |
422 | /**\r | |
423 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
424 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
425 | \r | |
426 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
427 | bitwise AND between the read result and the value specified by AndData, and\r | |
428 | writes the result to the 8-bit PCI configuration register specified by\r | |
429 | Address. The value written to the PCI configuration register is returned.\r | |
430 | This function must guarantee that all PCI read and write operations are\r | |
431 | serialized. Extra left bits in AndData are stripped.\r | |
432 | \r | |
433 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
434 | If StartBit is greater than 7, then ASSERT().\r | |
435 | If EndBit is greater than 7, then ASSERT().\r | |
436 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 437 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1a3eaf06 | 438 | \r |
2fc59a00 | 439 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 440 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
441 | Range 0..7.\r | |
442 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
443 | Range 0..7.\r | |
444 | @param AndData The value to AND with the PCI configuration register.\r | |
445 | \r | |
446 | @return The value written back to the PCI configuration register.\r | |
447 | \r | |
448 | **/\r | |
449 | UINT8\r | |
450 | EFIAPI\r | |
451 | PciBitFieldAnd8 (\r | |
452 | IN UINTN Address,\r | |
453 | IN UINTN StartBit,\r | |
454 | IN UINTN EndBit,\r | |
455 | IN UINT8 AndData\r | |
456 | )\r | |
457 | {\r | |
458 | return PciWrite8 (\r | |
459 | Address,\r | |
460 | BitFieldAnd8 (PciRead8 (Address), StartBit, EndBit, AndData)\r | |
461 | );\r | |
462 | }\r | |
463 | \r | |
464 | /**\r | |
465 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 466 | bitwise OR, and writes the result back to the bit field in the\r |
1a3eaf06 | 467 | 8-bit port.\r |
468 | \r | |
469 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 470 | bitwise AND followed by a bitwise OR between the read result and\r |
1a3eaf06 | 471 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
472 | configuration register specified by Address. The value written to the PCI\r | |
473 | configuration register is returned. This function must guarantee that all PCI\r | |
474 | read and write operations are serialized. Extra left bits in both AndData and\r | |
475 | OrData are stripped.\r | |
476 | \r | |
477 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
478 | If StartBit is greater than 7, then ASSERT().\r | |
479 | If EndBit is greater than 7, then ASSERT().\r | |
480 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
481 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
482 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1a3eaf06 | 483 | \r |
2fc59a00 | 484 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 485 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
486 | Range 0..7.\r | |
487 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
488 | Range 0..7.\r | |
489 | @param AndData The value to AND with the PCI configuration register.\r | |
490 | @param OrData The value to OR with the result of the AND operation.\r | |
491 | \r | |
492 | @return The value written back to the PCI configuration register.\r | |
493 | \r | |
494 | **/\r | |
495 | UINT8\r | |
496 | EFIAPI\r | |
497 | PciBitFieldAndThenOr8 (\r | |
498 | IN UINTN Address,\r | |
499 | IN UINTN StartBit,\r | |
500 | IN UINTN EndBit,\r | |
501 | IN UINT8 AndData,\r | |
502 | IN UINT8 OrData\r | |
503 | )\r | |
504 | {\r | |
505 | return PciWrite8 (\r | |
506 | Address,\r | |
507 | BitFieldAndThenOr8 (PciRead8 (Address), StartBit, EndBit, AndData, OrData)\r | |
508 | );\r | |
509 | }\r | |
510 | \r | |
511 | /**\r | |
512 | Reads a 16-bit PCI configuration register.\r | |
513 | \r | |
514 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
515 | This function must guarantee that all PCI read and write operations are\r | |
516 | serialized.\r | |
517 | \r | |
518 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
519 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
520 | \r | |
2fc59a00 | 521 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 522 | Register.\r |
523 | \r | |
9638ba6d | 524 | @return The read value from the PCI configuration register.\r |
1a3eaf06 | 525 | \r |
526 | **/\r | |
527 | UINT16\r | |
528 | EFIAPI\r | |
529 | PciRead16 (\r | |
530 | IN UINTN Address\r | |
531 | )\r | |
532 | {\r | |
533 | ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r | |
534 | \r | |
535 | return (UINT16) PeiPciLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint16);\r | |
536 | }\r | |
537 | \r | |
538 | /**\r | |
539 | Writes a 16-bit PCI configuration register.\r | |
540 | \r | |
541 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
542 | value specified by Value. Value is returned. This function must guarantee\r | |
543 | that all PCI read and write operations are serialized.\r | |
544 | \r | |
545 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
546 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
547 | \r | |
2fc59a00 | 548 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 549 | Register.\r |
9638ba6d | 550 | @param Value The value to write.\r |
1a3eaf06 | 551 | \r |
552 | @return The value written to the PCI configuration register.\r | |
553 | \r | |
554 | **/\r | |
555 | UINT16\r | |
556 | EFIAPI\r | |
557 | PciWrite16 (\r | |
558 | IN UINTN Address,\r | |
0c3437e0 | 559 | IN UINT16 Value\r |
1a3eaf06 | 560 | )\r |
561 | {\r | |
562 | ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r | |
563 | \r | |
0c3437e0 | 564 | return (UINT16) PeiPciLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint16, Value);\r |
1a3eaf06 | 565 | }\r |
566 | \r | |
567 | /**\r | |
62991af2 | 568 | Performs a bitwise OR of a 16-bit PCI configuration register with\r |
1a3eaf06 | 569 | a 16-bit value.\r |
570 | \r | |
571 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 572 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 573 | OrData, and writes the result to the 16-bit PCI configuration register\r |
574 | specified by Address. The value written to the PCI configuration register is\r | |
575 | returned. This function must guarantee that all PCI read and write operations\r | |
576 | are serialized.\r | |
577 | \r | |
578 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
579 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
580 | \r | |
2fc59a00 | 581 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 582 | Register.\r |
583 | @param OrData The value to OR with the PCI configuration register.\r | |
584 | \r | |
585 | @return The value written back to the PCI configuration register.\r | |
586 | \r | |
587 | **/\r | |
588 | UINT16\r | |
589 | EFIAPI\r | |
590 | PciOr16 (\r | |
591 | IN UINTN Address,\r | |
592 | IN UINT16 OrData\r | |
593 | )\r | |
594 | {\r | |
595 | return PciWrite16 (Address, (UINT16) (PciRead16 (Address) | OrData));\r | |
596 | }\r | |
597 | \r | |
598 | /**\r | |
599 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
600 | value.\r | |
601 | \r | |
602 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
603 | bitwise AND between the read result and the value specified by AndData, and\r | |
604 | writes the result to the 16-bit PCI configuration register specified by\r | |
605 | Address. The value written to the PCI configuration register is returned.\r | |
606 | This function must guarantee that all PCI read and write operations are\r | |
607 | serialized.\r | |
608 | \r | |
609 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
610 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
611 | \r | |
2fc59a00 | 612 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 613 | Register.\r |
614 | @param AndData The value to AND with the PCI configuration register.\r | |
615 | \r | |
616 | @return The value written back to the PCI configuration register.\r | |
617 | \r | |
618 | **/\r | |
619 | UINT16\r | |
620 | EFIAPI\r | |
621 | PciAnd16 (\r | |
622 | IN UINTN Address,\r | |
623 | IN UINT16 AndData\r | |
624 | )\r | |
625 | {\r | |
626 | return PciWrite16 (Address, (UINT16) (PciRead16 (Address) & AndData));\r | |
627 | }\r | |
628 | \r | |
629 | /**\r | |
630 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
62991af2 | 631 | value, followed a bitwise OR with another 16-bit value.\r |
1a3eaf06 | 632 | \r |
633 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
634 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 635 | performs a bitwise OR between the result of the AND operation and\r |
1a3eaf06 | 636 | the value specified by OrData, and writes the result to the 16-bit PCI\r |
637 | configuration register specified by Address. The value written to the PCI\r | |
638 | configuration register is returned. This function must guarantee that all PCI\r | |
639 | read and write operations are serialized.\r | |
640 | \r | |
641 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
642 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
643 | \r | |
2fc59a00 | 644 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 645 | Register.\r |
646 | @param AndData The value to AND with the PCI configuration register.\r | |
647 | @param OrData The value to OR with the result of the AND operation.\r | |
648 | \r | |
649 | @return The value written back to the PCI configuration register.\r | |
650 | \r | |
651 | **/\r | |
652 | UINT16\r | |
653 | EFIAPI\r | |
654 | PciAndThenOr16 (\r | |
655 | IN UINTN Address,\r | |
656 | IN UINT16 AndData,\r | |
657 | IN UINT16 OrData\r | |
658 | )\r | |
659 | {\r | |
660 | return PciWrite16 (Address, (UINT16) ((PciRead16 (Address) & AndData) | OrData));\r | |
661 | }\r | |
662 | \r | |
663 | /**\r | |
664 | Reads a bit field of a PCI configuration register.\r | |
665 | \r | |
666 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
667 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
668 | returned.\r | |
669 | \r | |
670 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
671 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
672 | If StartBit is greater than 15, then ASSERT().\r | |
673 | If EndBit is greater than 15, then ASSERT().\r | |
674 | If EndBit is less than StartBit, then ASSERT().\r | |
675 | \r | |
2fc59a00 | 676 | @param Address The PCI configuration register to read.\r |
1a3eaf06 | 677 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
678 | Range 0..15.\r | |
679 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
680 | Range 0..15.\r | |
681 | \r | |
682 | @return The value of the bit field read from the PCI configuration register.\r | |
683 | \r | |
684 | **/\r | |
685 | UINT16\r | |
686 | EFIAPI\r | |
687 | PciBitFieldRead16 (\r | |
688 | IN UINTN Address,\r | |
689 | IN UINTN StartBit,\r | |
690 | IN UINTN EndBit\r | |
691 | )\r | |
692 | {\r | |
693 | return BitFieldRead16 (PciRead16 (Address), StartBit, EndBit);\r | |
694 | }\r | |
695 | \r | |
696 | /**\r | |
697 | Writes a bit field to a PCI configuration register.\r | |
698 | \r | |
699 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
700 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
701 | destination PCI configuration register are preserved. The new value of the\r | |
702 | 16-bit register is returned.\r | |
703 | \r | |
704 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
705 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
706 | If StartBit is greater than 15, then ASSERT().\r | |
707 | If EndBit is greater than 15, then ASSERT().\r | |
708 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 709 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1a3eaf06 | 710 | \r |
2fc59a00 | 711 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 712 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
713 | Range 0..15.\r | |
714 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
715 | Range 0..15.\r | |
2fc59a00 | 716 | @param Value The new value of the bit field.\r |
1a3eaf06 | 717 | \r |
718 | @return The value written back to the PCI configuration register.\r | |
719 | \r | |
720 | **/\r | |
721 | UINT16\r | |
722 | EFIAPI\r | |
723 | PciBitFieldWrite16 (\r | |
724 | IN UINTN Address,\r | |
725 | IN UINTN StartBit,\r | |
726 | IN UINTN EndBit,\r | |
727 | IN UINT16 Value\r | |
728 | )\r | |
729 | {\r | |
730 | return PciWrite16 (\r | |
731 | Address,\r | |
732 | BitFieldWrite16 (PciRead16 (Address), StartBit, EndBit, Value)\r | |
733 | );\r | |
734 | }\r | |
735 | \r | |
736 | /**\r | |
737 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
738 | writes the result back to the bit field in the 16-bit port.\r | |
739 | \r | |
740 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 741 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 742 | OrData, and writes the result to the 16-bit PCI configuration register\r |
743 | specified by Address. The value written to the PCI configuration register is\r | |
744 | returned. This function must guarantee that all PCI read and write operations\r | |
745 | are serialized. Extra left bits in OrData are stripped.\r | |
746 | \r | |
747 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
748 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
749 | If StartBit is greater than 15, then ASSERT().\r | |
750 | If EndBit is greater than 15, then ASSERT().\r | |
751 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 752 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1a3eaf06 | 753 | \r |
2fc59a00 | 754 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 755 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
756 | Range 0..15.\r | |
757 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
758 | Range 0..15.\r | |
759 | @param OrData The value to OR with the PCI configuration register.\r | |
760 | \r | |
761 | @return The value written back to the PCI configuration register.\r | |
762 | \r | |
763 | **/\r | |
764 | UINT16\r | |
765 | EFIAPI\r | |
766 | PciBitFieldOr16 (\r | |
767 | IN UINTN Address,\r | |
768 | IN UINTN StartBit,\r | |
769 | IN UINTN EndBit,\r | |
770 | IN UINT16 OrData\r | |
771 | )\r | |
772 | {\r | |
773 | return PciWrite16 (\r | |
774 | Address,\r | |
775 | BitFieldOr16 (PciRead16 (Address), StartBit, EndBit, OrData)\r | |
776 | );\r | |
777 | }\r | |
778 | \r | |
779 | /**\r | |
780 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
781 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
782 | \r | |
783 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
784 | bitwise AND between the read result and the value specified by AndData, and\r | |
785 | writes the result to the 16-bit PCI configuration register specified by\r | |
786 | Address. The value written to the PCI configuration register is returned.\r | |
787 | This function must guarantee that all PCI read and write operations are\r | |
788 | serialized. Extra left bits in AndData are stripped.\r | |
789 | \r | |
790 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
791 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
792 | If StartBit is greater than 15, then ASSERT().\r | |
793 | If EndBit is greater than 15, then ASSERT().\r | |
794 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 795 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1a3eaf06 | 796 | \r |
2fc59a00 | 797 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 798 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
799 | Range 0..15.\r | |
800 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
801 | Range 0..15.\r | |
802 | @param AndData The value to AND with the PCI configuration register.\r | |
803 | \r | |
804 | @return The value written back to the PCI configuration register.\r | |
805 | \r | |
806 | **/\r | |
807 | UINT16\r | |
808 | EFIAPI\r | |
809 | PciBitFieldAnd16 (\r | |
810 | IN UINTN Address,\r | |
811 | IN UINTN StartBit,\r | |
812 | IN UINTN EndBit,\r | |
813 | IN UINT16 AndData\r | |
814 | )\r | |
815 | {\r | |
816 | return PciWrite16 (\r | |
817 | Address,\r | |
818 | BitFieldAnd16 (PciRead16 (Address), StartBit, EndBit, AndData)\r | |
819 | );\r | |
820 | }\r | |
821 | \r | |
822 | /**\r | |
823 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 824 | bitwise OR, and writes the result back to the bit field in the\r |
1a3eaf06 | 825 | 16-bit port.\r |
826 | \r | |
827 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 828 | bitwise AND followed by a bitwise OR between the read result and\r |
1a3eaf06 | 829 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
830 | configuration register specified by Address. The value written to the PCI\r | |
831 | configuration register is returned. This function must guarantee that all PCI\r | |
832 | read and write operations are serialized. Extra left bits in both AndData and\r | |
833 | OrData are stripped.\r | |
834 | \r | |
835 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
836 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
837 | If StartBit is greater than 15, then ASSERT().\r | |
838 | If EndBit is greater than 15, then ASSERT().\r | |
839 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
840 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
841 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1a3eaf06 | 842 | \r |
2fc59a00 | 843 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 844 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
845 | Range 0..15.\r | |
846 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
847 | Range 0..15.\r | |
848 | @param AndData The value to AND with the PCI configuration register.\r | |
849 | @param OrData The value to OR with the result of the AND operation.\r | |
850 | \r | |
851 | @return The value written back to the PCI configuration register.\r | |
852 | \r | |
853 | **/\r | |
854 | UINT16\r | |
855 | EFIAPI\r | |
856 | PciBitFieldAndThenOr16 (\r | |
857 | IN UINTN Address,\r | |
858 | IN UINTN StartBit,\r | |
859 | IN UINTN EndBit,\r | |
860 | IN UINT16 AndData,\r | |
861 | IN UINT16 OrData\r | |
862 | )\r | |
863 | {\r | |
864 | return PciWrite16 (\r | |
865 | Address,\r | |
866 | BitFieldAndThenOr16 (PciRead16 (Address), StartBit, EndBit, AndData, OrData)\r | |
867 | );\r | |
868 | }\r | |
869 | \r | |
870 | /**\r | |
871 | Reads a 32-bit PCI configuration register.\r | |
872 | \r | |
873 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
874 | This function must guarantee that all PCI read and write operations are\r | |
875 | serialized.\r | |
876 | \r | |
877 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
878 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
879 | \r | |
2fc59a00 | 880 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 881 | Register.\r |
882 | \r | |
9638ba6d | 883 | @return The read value from the PCI configuration register.\r |
1a3eaf06 | 884 | \r |
885 | **/\r | |
886 | UINT32\r | |
887 | EFIAPI\r | |
888 | PciRead32 (\r | |
889 | IN UINTN Address\r | |
890 | )\r | |
891 | {\r | |
892 | ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r | |
893 | \r | |
894 | return PeiPciLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint32);\r | |
895 | }\r | |
896 | \r | |
897 | /**\r | |
898 | Writes a 32-bit PCI configuration register.\r | |
899 | \r | |
900 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
901 | value specified by Value. Value is returned. This function must guarantee\r | |
902 | that all PCI read and write operations are serialized.\r | |
903 | \r | |
904 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
905 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
906 | \r | |
2fc59a00 | 907 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 908 | Register.\r |
9638ba6d | 909 | @param Value The value to write.\r |
1a3eaf06 | 910 | \r |
911 | @return The value written to the PCI configuration register.\r | |
912 | \r | |
913 | **/\r | |
914 | UINT32\r | |
915 | EFIAPI\r | |
916 | PciWrite32 (\r | |
917 | IN UINTN Address,\r | |
0c3437e0 | 918 | IN UINT32 Value\r |
1a3eaf06 | 919 | )\r |
920 | {\r | |
921 | ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r | |
922 | \r | |
0c3437e0 | 923 | return PeiPciLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint32, Value);\r |
1a3eaf06 | 924 | }\r |
925 | \r | |
926 | /**\r | |
62991af2 | 927 | Performs a bitwise OR of a 32-bit PCI configuration register with\r |
1a3eaf06 | 928 | a 32-bit value.\r |
929 | \r | |
930 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 931 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 932 | OrData, and writes the result to the 32-bit PCI configuration register\r |
933 | specified by Address. The value written to the PCI configuration register is\r | |
934 | returned. This function must guarantee that all PCI read and write operations\r | |
935 | are serialized.\r | |
936 | \r | |
937 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
938 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
939 | \r | |
2fc59a00 | 940 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 941 | Register.\r |
942 | @param OrData The value to OR with the PCI configuration register.\r | |
943 | \r | |
944 | @return The value written back to the PCI configuration register.\r | |
945 | \r | |
946 | **/\r | |
947 | UINT32\r | |
948 | EFIAPI\r | |
949 | PciOr32 (\r | |
950 | IN UINTN Address,\r | |
951 | IN UINT32 OrData\r | |
952 | )\r | |
953 | {\r | |
954 | return PciWrite32 (Address, PciRead32 (Address) | OrData);\r | |
955 | }\r | |
956 | \r | |
957 | /**\r | |
958 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
959 | value.\r | |
960 | \r | |
961 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
962 | bitwise AND between the read result and the value specified by AndData, and\r | |
963 | writes the result to the 32-bit PCI configuration register specified by\r | |
964 | Address. The value written to the PCI configuration register is returned.\r | |
965 | This function must guarantee that all PCI read and write operations are\r | |
966 | serialized.\r | |
967 | \r | |
968 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
969 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
970 | \r | |
2fc59a00 | 971 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 972 | Register.\r |
973 | @param AndData The value to AND with the PCI configuration register.\r | |
974 | \r | |
975 | @return The value written back to the PCI configuration register.\r | |
976 | \r | |
977 | **/\r | |
978 | UINT32\r | |
979 | EFIAPI\r | |
980 | PciAnd32 (\r | |
981 | IN UINTN Address,\r | |
982 | IN UINT32 AndData\r | |
983 | )\r | |
984 | {\r | |
985 | return PciWrite32 (Address, PciRead32 (Address) & AndData);\r | |
986 | }\r | |
987 | \r | |
988 | /**\r | |
989 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
62991af2 | 990 | value, followed a bitwise OR with another 32-bit value.\r |
1a3eaf06 | 991 | \r |
992 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
993 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 994 | performs a bitwise OR between the result of the AND operation and\r |
1a3eaf06 | 995 | the value specified by OrData, and writes the result to the 32-bit PCI\r |
996 | configuration register specified by Address. The value written to the PCI\r | |
997 | configuration register is returned. This function must guarantee that all PCI\r | |
998 | read and write operations are serialized.\r | |
999 | \r | |
1000 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1001 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1002 | \r | |
2fc59a00 | 1003 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 1004 | Register.\r |
1005 | @param AndData The value to AND with the PCI configuration register.\r | |
1006 | @param OrData The value to OR with the result of the AND operation.\r | |
1007 | \r | |
1008 | @return The value written back to the PCI configuration register.\r | |
1009 | \r | |
1010 | **/\r | |
1011 | UINT32\r | |
1012 | EFIAPI\r | |
1013 | PciAndThenOr32 (\r | |
1014 | IN UINTN Address,\r | |
1015 | IN UINT32 AndData,\r | |
1016 | IN UINT32 OrData\r | |
1017 | )\r | |
1018 | {\r | |
1019 | return PciWrite32 (Address, (PciRead32 (Address) & AndData) | OrData);\r | |
1020 | }\r | |
1021 | \r | |
1022 | /**\r | |
1023 | Reads a bit field of a PCI configuration register.\r | |
1024 | \r | |
1025 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
1026 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
1027 | returned.\r | |
1028 | \r | |
1029 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1030 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1031 | If StartBit is greater than 31, then ASSERT().\r | |
1032 | If EndBit is greater than 31, then ASSERT().\r | |
1033 | If EndBit is less than StartBit, then ASSERT().\r | |
1034 | \r | |
2fc59a00 | 1035 | @param Address The PCI configuration register to read.\r |
1a3eaf06 | 1036 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1037 | Range 0..31.\r | |
1038 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1039 | Range 0..31.\r | |
1040 | \r | |
1041 | @return The value of the bit field read from the PCI configuration register.\r | |
1042 | \r | |
1043 | **/\r | |
1044 | UINT32\r | |
1045 | EFIAPI\r | |
1046 | PciBitFieldRead32 (\r | |
1047 | IN UINTN Address,\r | |
1048 | IN UINTN StartBit,\r | |
1049 | IN UINTN EndBit\r | |
1050 | )\r | |
1051 | {\r | |
1052 | return BitFieldRead32 (PciRead32 (Address), StartBit, EndBit);\r | |
1053 | }\r | |
1054 | \r | |
1055 | /**\r | |
1056 | Writes a bit field to a PCI configuration register.\r | |
1057 | \r | |
1058 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
1059 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
1060 | destination PCI configuration register are preserved. The new value of the\r | |
1061 | 32-bit register is returned.\r | |
1062 | \r | |
1063 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1064 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1065 | If StartBit is greater than 31, then ASSERT().\r | |
1066 | If EndBit is greater than 31, then ASSERT().\r | |
1067 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 1068 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1a3eaf06 | 1069 | \r |
2fc59a00 | 1070 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 1071 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1072 | Range 0..31.\r | |
1073 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1074 | Range 0..31.\r | |
2fc59a00 | 1075 | @param Value The new value of the bit field.\r |
1a3eaf06 | 1076 | \r |
1077 | @return The value written back to the PCI configuration register.\r | |
1078 | \r | |
1079 | **/\r | |
1080 | UINT32\r | |
1081 | EFIAPI\r | |
1082 | PciBitFieldWrite32 (\r | |
1083 | IN UINTN Address,\r | |
1084 | IN UINTN StartBit,\r | |
1085 | IN UINTN EndBit,\r | |
1086 | IN UINT32 Value\r | |
1087 | )\r | |
1088 | {\r | |
1089 | return PciWrite32 (\r | |
1090 | Address,\r | |
1091 | BitFieldWrite32 (PciRead32 (Address), StartBit, EndBit, Value)\r | |
1092 | );\r | |
1093 | }\r | |
1094 | \r | |
1095 | /**\r | |
1096 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
1097 | writes the result back to the bit field in the 32-bit port.\r | |
1098 | \r | |
1099 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 1100 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 1101 | OrData, and writes the result to the 32-bit PCI configuration register\r |
1102 | specified by Address. The value written to the PCI configuration register is\r | |
1103 | returned. This function must guarantee that all PCI read and write operations\r | |
1104 | are serialized. Extra left bits in OrData are stripped.\r | |
1105 | \r | |
1106 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1107 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1108 | If StartBit is greater than 31, then ASSERT().\r | |
1109 | If EndBit is greater than 31, then ASSERT().\r | |
1110 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 1111 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1a3eaf06 | 1112 | \r |
2fc59a00 | 1113 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 1114 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1115 | Range 0..31.\r | |
1116 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1117 | Range 0..31.\r | |
1118 | @param OrData The value to OR with the PCI configuration register.\r | |
1119 | \r | |
1120 | @return The value written back to the PCI configuration register.\r | |
1121 | \r | |
1122 | **/\r | |
1123 | UINT32\r | |
1124 | EFIAPI\r | |
1125 | PciBitFieldOr32 (\r | |
1126 | IN UINTN Address,\r | |
1127 | IN UINTN StartBit,\r | |
1128 | IN UINTN EndBit,\r | |
1129 | IN UINT32 OrData\r | |
1130 | )\r | |
1131 | {\r | |
1132 | return PciWrite32 (\r | |
1133 | Address,\r | |
1134 | BitFieldOr32 (PciRead32 (Address), StartBit, EndBit, OrData)\r | |
1135 | );\r | |
1136 | }\r | |
1137 | \r | |
1138 | /**\r | |
1139 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
1140 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
1141 | \r | |
1142 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1143 | bitwise AND between the read result and the value specified by AndData, and\r | |
1144 | writes the result to the 32-bit PCI configuration register specified by\r | |
1145 | Address. The value written to the PCI configuration register is returned.\r | |
1146 | This function must guarantee that all PCI read and write operations are\r | |
1147 | serialized. Extra left bits in AndData are stripped.\r | |
1148 | \r | |
1149 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1150 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1151 | If StartBit is greater than 31, then ASSERT().\r | |
1152 | If EndBit is greater than 31, then ASSERT().\r | |
1153 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 1154 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1a3eaf06 | 1155 | \r |
2fc59a00 | 1156 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 1157 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1158 | Range 0..31.\r | |
1159 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1160 | Range 0..31.\r | |
1161 | @param AndData The value to AND with the PCI configuration register.\r | |
1162 | \r | |
1163 | @return The value written back to the PCI configuration register.\r | |
1164 | \r | |
1165 | **/\r | |
1166 | UINT32\r | |
1167 | EFIAPI\r | |
1168 | PciBitFieldAnd32 (\r | |
1169 | IN UINTN Address,\r | |
1170 | IN UINTN StartBit,\r | |
1171 | IN UINTN EndBit,\r | |
1172 | IN UINT32 AndData\r | |
1173 | )\r | |
1174 | {\r | |
1175 | return PciWrite32 (\r | |
1176 | Address,\r | |
1177 | BitFieldAnd32 (PciRead32 (Address), StartBit, EndBit, AndData)\r | |
1178 | );\r | |
1179 | }\r | |
1180 | \r | |
1181 | /**\r | |
1182 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 1183 | bitwise OR, and writes the result back to the bit field in the\r |
1a3eaf06 | 1184 | 32-bit port.\r |
1185 | \r | |
1186 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 1187 | bitwise AND followed by a bitwise OR between the read result and\r |
1a3eaf06 | 1188 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
1189 | configuration register specified by Address. The value written to the PCI\r | |
1190 | configuration register is returned. This function must guarantee that all PCI\r | |
1191 | read and write operations are serialized. Extra left bits in both AndData and\r | |
1192 | OrData are stripped.\r | |
1193 | \r | |
1194 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1195 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1196 | If StartBit is greater than 31, then ASSERT().\r | |
1197 | If EndBit is greater than 31, then ASSERT().\r | |
1198 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
1199 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1200 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1a3eaf06 | 1201 | \r |
2fc59a00 | 1202 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 1203 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1204 | Range 0..31.\r | |
1205 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1206 | Range 0..31.\r | |
1207 | @param AndData The value to AND with the PCI configuration register.\r | |
1208 | @param OrData The value to OR with the result of the AND operation.\r | |
1209 | \r | |
1210 | @return The value written back to the PCI configuration register.\r | |
1211 | \r | |
1212 | **/\r | |
1213 | UINT32\r | |
1214 | EFIAPI\r | |
1215 | PciBitFieldAndThenOr32 (\r | |
1216 | IN UINTN Address,\r | |
1217 | IN UINTN StartBit,\r | |
1218 | IN UINTN EndBit,\r | |
1219 | IN UINT32 AndData,\r | |
1220 | IN UINT32 OrData\r | |
1221 | )\r | |
1222 | {\r | |
1223 | return PciWrite32 (\r | |
1224 | Address,\r | |
1225 | BitFieldAndThenOr32 (PciRead32 (Address), StartBit, EndBit, AndData, OrData)\r | |
1226 | );\r | |
1227 | }\r | |
1228 | \r | |
1229 | /**\r | |
1230 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
1231 | \r | |
1232 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
1233 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1234 | configuration registers from a single PCI function to be read. Size is\r | |
1235 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
1236 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
1237 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
1238 | end of the range.\r | |
1239 | \r | |
1240 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1241 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1242 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1243 | \r | |
2fc59a00 | 1244 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r |
1a3eaf06 | 1245 | Function and Register.\r |
2fc59a00 | 1246 | @param Size The size in bytes of the transfer.\r |
1247 | @param Buffer The pointer to a buffer receiving the data read.\r | |
1a3eaf06 | 1248 | \r |
1249 | @return Size\r | |
1250 | \r | |
1251 | **/\r | |
1252 | UINTN\r | |
1253 | EFIAPI\r | |
1254 | PciReadBuffer (\r | |
1255 | IN UINTN StartAddress,\r | |
1256 | IN UINTN Size,\r | |
1257 | OUT VOID *Buffer\r | |
1258 | )\r | |
1259 | {\r | |
1260 | UINTN ReturnValue;\r | |
1261 | \r | |
1262 | ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r | |
e43e4b3e | 1263 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r |
1a3eaf06 | 1264 | \r |
1265 | if (Size == 0) {\r | |
1266 | return Size;\r | |
1267 | }\r | |
1268 | \r | |
1269 | ASSERT (Buffer != NULL);\r | |
1270 | \r | |
1271 | //\r | |
1272 | // Save Size for return\r | |
1273 | //\r | |
1274 | ReturnValue = Size;\r | |
1275 | \r | |
e43e4b3e | 1276 | if ((StartAddress & BIT0) != 0) {\r |
1a3eaf06 | 1277 | //\r |
1278 | // Read a byte if StartAddress is byte aligned\r | |
1279 | //\r | |
1280 | *(volatile UINT8 *)Buffer = PciRead8 (StartAddress);\r | |
1281 | StartAddress += sizeof (UINT8);\r | |
1282 | Size -= sizeof (UINT8);\r | |
1283 | Buffer = (UINT8*)Buffer + 1;\r | |
1284 | }\r | |
1285 | \r | |
e43e4b3e | 1286 | if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r |
1a3eaf06 | 1287 | //\r |
1288 | // Read a word if StartAddress is word aligned\r | |
1289 | //\r | |
5dc4fd78 | 1290 | WriteUnaligned16 (Buffer, PciRead16 (StartAddress));\r |
1a3eaf06 | 1291 | StartAddress += sizeof (UINT16);\r |
1292 | Size -= sizeof (UINT16);\r | |
1293 | Buffer = (UINT16*)Buffer + 1;\r | |
1294 | }\r | |
1295 | \r | |
1296 | while (Size >= sizeof (UINT32)) {\r | |
1297 | //\r | |
1298 | // Read as many double words as possible\r | |
1299 | //\r | |
5dc4fd78 | 1300 | WriteUnaligned32 (Buffer, PciRead32 (StartAddress));\r |
1a3eaf06 | 1301 | StartAddress += sizeof (UINT32);\r |
1302 | Size -= sizeof (UINT32);\r | |
1303 | Buffer = (UINT32*)Buffer + 1;\r | |
1304 | }\r | |
1305 | \r | |
1306 | if (Size >= sizeof (UINT16)) {\r | |
1307 | //\r | |
1308 | // Read the last remaining word if exist\r | |
1309 | //\r | |
5dc4fd78 | 1310 | WriteUnaligned16 (Buffer, PciRead16 (StartAddress));\r |
1a3eaf06 | 1311 | StartAddress += sizeof (UINT16);\r |
1312 | Size -= sizeof (UINT16);\r | |
1313 | Buffer = (UINT16*)Buffer + 1;\r | |
1314 | }\r | |
1315 | \r | |
1316 | if (Size >= sizeof (UINT8)) {\r | |
1317 | //\r | |
1318 | // Read the last remaining byte if exist\r | |
1319 | //\r | |
1320 | *(volatile UINT8 *)Buffer = PciRead8 (StartAddress);\r | |
1321 | }\r | |
1322 | \r | |
1323 | return ReturnValue;\r | |
1324 | }\r | |
1325 | \r | |
1326 | /**\r | |
1327 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1328 | configuration space.\r | |
1329 | \r | |
1330 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1331 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1332 | configuration registers from a single PCI function to be written. Size is\r | |
1333 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1334 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1335 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1336 | and the end of the range.\r | |
1337 | \r | |
1338 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1339 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1340 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1341 | \r | |
2fc59a00 | 1342 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r |
1a3eaf06 | 1343 | Function and Register.\r |
2fc59a00 | 1344 | @param Size The size in bytes of the transfer.\r |
1345 | @param Buffer The pointer to a buffer containing the data to write.\r | |
1a3eaf06 | 1346 | \r |
0c3437e0 | 1347 | @return Size written to StartAddress.\r |
1a3eaf06 | 1348 | \r |
1349 | **/\r | |
1350 | UINTN\r | |
1351 | EFIAPI\r | |
1352 | PciWriteBuffer (\r | |
1353 | IN UINTN StartAddress,\r | |
1354 | IN UINTN Size,\r | |
1355 | IN VOID *Buffer\r | |
1356 | )\r | |
1357 | {\r | |
1358 | UINTN ReturnValue;\r | |
1359 | \r | |
1360 | ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r | |
e43e4b3e | 1361 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r |
1a3eaf06 | 1362 | \r |
1363 | if (Size == 0) {\r | |
1364 | return 0;\r | |
1365 | }\r | |
1366 | \r | |
1367 | ASSERT (Buffer != NULL);\r | |
1368 | \r | |
1369 | //\r | |
1370 | // Save Size for return\r | |
1371 | //\r | |
1372 | ReturnValue = Size;\r | |
1373 | \r | |
e43e4b3e | 1374 | if ((StartAddress & BIT0) != 0) {\r |
1a3eaf06 | 1375 | //\r |
1376 | // Write a byte if StartAddress is byte aligned\r | |
1377 | //\r | |
1378 | PciWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1379 | StartAddress += sizeof (UINT8);\r | |
1380 | Size -= sizeof (UINT8);\r | |
1381 | Buffer = (UINT8*)Buffer + 1;\r | |
1382 | }\r | |
1383 | \r | |
e43e4b3e | 1384 | if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r |
1a3eaf06 | 1385 | //\r |
1386 | // Write a word if StartAddress is word aligned\r | |
1387 | //\r | |
5dc4fd78 | 1388 | PciWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r |
1a3eaf06 | 1389 | StartAddress += sizeof (UINT16);\r |
1390 | Size -= sizeof (UINT16);\r | |
1391 | Buffer = (UINT16*)Buffer + 1;\r | |
1392 | }\r | |
1393 | \r | |
1394 | while (Size >= sizeof (UINT32)) {\r | |
1395 | //\r | |
1396 | // Write as many double words as possible\r | |
1397 | //\r | |
5dc4fd78 | 1398 | PciWrite32 (StartAddress, ReadUnaligned32 (Buffer));\r |
1a3eaf06 | 1399 | StartAddress += sizeof (UINT32);\r |
1400 | Size -= sizeof (UINT32);\r | |
1401 | Buffer = (UINT32*)Buffer + 1;\r | |
1402 | }\r | |
1403 | \r | |
1404 | if (Size >= sizeof (UINT16)) {\r | |
1405 | //\r | |
1406 | // Write the last remaining word if exist\r | |
1407 | //\r | |
5dc4fd78 | 1408 | PciWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r |
1a3eaf06 | 1409 | StartAddress += sizeof (UINT16);\r |
1410 | Size -= sizeof (UINT16);\r | |
1411 | Buffer = (UINT16*)Buffer + 1;\r | |
1412 | }\r | |
1413 | \r | |
1414 | if (Size >= sizeof (UINT8)) {\r | |
1415 | //\r | |
1416 | // Write the last remaining byte if exist\r | |
1417 | //\r | |
1418 | PciWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1419 | }\r | |
1420 | \r | |
1421 | return ReturnValue;\r | |
1422 | }\r |