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1e57a462 | 1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
4 | \r | |
5 | This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #ifndef __OMAP3530GPMC_H__\r | |
16 | #define __OMAP3530GPMC_H__\r | |
17 | \r | |
18 | #define GPMC_BASE (0x6E000000)\r | |
19 | \r | |
20 | //GPMC NAND definitions.\r | |
21 | #define GPMC_SYSCONFIG (GPMC_BASE + 0x10)\r | |
22 | #define SMARTIDLEMODE (0x2UL << 3)\r | |
23 | \r | |
24 | #define GPMC_SYSSTATUS (GPMC_BASE + 0x14)\r | |
25 | #define GPMC_IRQSTATUS (GPMC_BASE + 0x18)\r | |
26 | #define GPMC_IRQENABLE (GPMC_BASE + 0x1C)\r | |
27 | \r | |
28 | #define GPMC_TIMEOUT_CONTROL (GPMC_BASE + 0x40)\r | |
29 | #define TIMEOUTENABLE BIT0\r | |
30 | #define TIMEOUTDISABLE (0x0UL << 0)\r | |
31 | \r | |
32 | #define GPMC_ERR_ADDRESS (GPMC_BASE + 0x44)\r | |
33 | #define GPMC_ERR_TYPE (GPMC_BASE + 0x48)\r | |
34 | \r | |
35 | #define GPMC_CONFIG (GPMC_BASE + 0x50)\r | |
36 | #define WRITEPROTECT_HIGH BIT4\r | |
37 | #define WRITEPROTECT_LOW (0x0UL << 4)\r | |
38 | \r | |
39 | #define GPMC_STATUS (GPMC_BASE + 0x54)\r | |
40 | \r | |
41 | #define GPMC_CONFIG1_0 (GPMC_BASE + 0x60)\r | |
42 | #define DEVICETYPE_NOR (0x0UL << 10)\r | |
43 | #define DEVICETYPE_NAND (0x2UL << 10)\r | |
44 | #define DEVICESIZE_X8 (0x0UL << 12)\r | |
45 | #define DEVICESIZE_X16 BIT12\r | |
46 | \r | |
47 | #define GPMC_CONFIG2_0 (GPMC_BASE + 0x64)\r | |
48 | #define CSONTIME (0x0UL << 0)\r | |
49 | #define CSRDOFFTIME (0x14UL << 8)\r | |
50 | #define CSWROFFTIME (0x14UL << 16)\r | |
51 | \r | |
52 | #define GPMC_CONFIG3_0 (GPMC_BASE + 0x68)\r | |
53 | #define ADVRDOFFTIME (0x14UL << 8)\r | |
54 | #define ADVWROFFTIME (0x14UL << 16)\r | |
55 | \r | |
56 | #define GPMC_CONFIG4_0 (GPMC_BASE + 0x6C)\r | |
57 | #define OEONTIME BIT0\r | |
58 | #define OEOFFTIME (0xFUL << 8)\r | |
59 | #define WEONTIME BIT16\r | |
60 | #define WEOFFTIME (0xFUL << 24)\r | |
61 | \r | |
62 | #define GPMC_CONFIG5_0 (GPMC_BASE + 0x70)\r | |
63 | #define RDCYCLETIME (0x14UL << 0)\r | |
64 | #define WRCYCLETIME (0x14UL << 8)\r | |
65 | #define RDACCESSTIME (0xCUL << 16)\r | |
66 | #define PAGEBURSTACCESSTIME BIT24\r | |
67 | \r | |
68 | #define GPMC_CONFIG6_0 (GPMC_BASE + 0x74)\r | |
69 | #define CYCLE2CYCLESAMECSEN BIT7\r | |
70 | #define CYCLE2CYCLEDELAY (0xAUL << 8)\r | |
71 | #define WRDATAONADMUXBUS (0xFUL << 16)\r | |
72 | #define WRACCESSTIME BIT24\r | |
73 | \r | |
74 | #define GPMC_CONFIG7_0 (GPMC_BASE + 0x78)\r | |
75 | #define BASEADDRESS (0x30UL << 0)\r | |
76 | #define CSVALID BIT6\r | |
77 | #define MASKADDRESS_128MB (0x8UL << 8)\r | |
78 | \r | |
79 | #define GPMC_NAND_COMMAND_0 (GPMC_BASE + 0x7C)\r | |
80 | #define GPMC_NAND_ADDRESS_0 (GPMC_BASE + 0x80)\r | |
81 | #define GPMC_NAND_DATA_0 (GPMC_BASE + 0x84)\r | |
82 | \r | |
83 | #define GPMC_ECC_CONFIG (GPMC_BASE + 0x1F4)\r | |
84 | #define ECCENABLE BIT0\r | |
85 | #define ECCDISABLE (0x0UL << 0)\r | |
86 | #define ECCCS_0 (0x0UL << 1)\r | |
87 | #define ECC16B BIT7\r | |
88 | \r | |
89 | #define GPMC_ECC_CONTROL (GPMC_BASE + 0x1F8)\r | |
90 | #define ECCPOINTER_REG1 BIT0\r | |
91 | #define ECCCLEAR BIT8\r | |
92 | \r | |
93 | #define GPMC_ECC_SIZE_CONFIG (GPMC_BASE + 0x1FC)\r | |
94 | #define ECCSIZE0_512BYTES (0xFFUL << 12)\r | |
95 | #define ECCSIZE1_512BYTES (0xFFUL << 22)\r | |
96 | \r | |
97 | #define GPMC_ECC1_RESULT (GPMC_BASE + 0x200)\r | |
98 | #define GPMC_ECC2_RESULT (GPMC_BASE + 0x204)\r | |
99 | #define GPMC_ECC3_RESULT (GPMC_BASE + 0x208)\r | |
100 | #define GPMC_ECC4_RESULT (GPMC_BASE + 0x20C)\r | |
101 | #define GPMC_ECC5_RESULT (GPMC_BASE + 0x210)\r | |
102 | #define GPMC_ECC6_RESULT (GPMC_BASE + 0x214)\r | |
103 | #define GPMC_ECC7_RESULT (GPMC_BASE + 0x218)\r | |
104 | #define GPMC_ECC8_RESULT (GPMC_BASE + 0x21C)\r | |
105 | #define GPMC_ECC9_RESULT (GPMC_BASE + 0x220)\r | |
106 | \r | |
107 | #endif //__OMAP3530GPMC_H__\r |