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1e57a462 | 1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
4 | \r | |
5 | This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #ifndef __OMAP3530_PAD_CONFIGURATION_H__\r | |
16 | #define __OMAP3530_PAD_CONFIGURATION_H__\r | |
17 | \r | |
18 | #define SYSTEM_CONTROL_MODULE_BASE 0x48002000\r | |
19 | \r | |
20 | //Pin definition\r | |
21 | #define SDRC_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x030)\r | |
22 | #define SDRC_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x032)\r | |
23 | #define SDRC_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x034)\r | |
24 | #define SDRC_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x036)\r | |
25 | #define SDRC_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x038)\r | |
26 | #define SDRC_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x03A)\r | |
27 | #define SDRC_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x03C)\r | |
28 | #define SDRC_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x03E)\r | |
29 | #define SDRC_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x040)\r | |
30 | #define SDRC_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x042)\r | |
31 | #define SDRC_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x044)\r | |
32 | #define SDRC_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x046)\r | |
33 | #define SDRC_D12 (SYSTEM_CONTROL_MODULE_BASE + 0x048)\r | |
34 | #define SDRC_D13 (SYSTEM_CONTROL_MODULE_BASE + 0x04A)\r | |
35 | #define SDRC_D14 (SYSTEM_CONTROL_MODULE_BASE + 0x04C)\r | |
36 | #define SDRC_D15 (SYSTEM_CONTROL_MODULE_BASE + 0x04E)\r | |
37 | #define SDRC_D16 (SYSTEM_CONTROL_MODULE_BASE + 0x050)\r | |
38 | #define SDRC_D17 (SYSTEM_CONTROL_MODULE_BASE + 0x052)\r | |
39 | #define SDRC_D18 (SYSTEM_CONTROL_MODULE_BASE + 0x054)\r | |
40 | #define SDRC_D19 (SYSTEM_CONTROL_MODULE_BASE + 0x056)\r | |
41 | #define SDRC_D20 (SYSTEM_CONTROL_MODULE_BASE + 0x058)\r | |
42 | #define SDRC_D21 (SYSTEM_CONTROL_MODULE_BASE + 0x05A)\r | |
43 | #define SDRC_D22 (SYSTEM_CONTROL_MODULE_BASE + 0x05C)\r | |
44 | #define SDRC_D23 (SYSTEM_CONTROL_MODULE_BASE + 0x05E)\r | |
45 | #define SDRC_D24 (SYSTEM_CONTROL_MODULE_BASE + 0x060)\r | |
46 | #define SDRC_D25 (SYSTEM_CONTROL_MODULE_BASE + 0x062)\r | |
47 | #define SDRC_D26 (SYSTEM_CONTROL_MODULE_BASE + 0x064)\r | |
48 | #define SDRC_D27 (SYSTEM_CONTROL_MODULE_BASE + 0x066)\r | |
49 | #define SDRC_D28 (SYSTEM_CONTROL_MODULE_BASE + 0x068)\r | |
50 | #define SDRC_D29 (SYSTEM_CONTROL_MODULE_BASE + 0x06A)\r | |
51 | #define SDRC_D30 (SYSTEM_CONTROL_MODULE_BASE + 0x06C)\r | |
52 | #define SDRC_D31 (SYSTEM_CONTROL_MODULE_BASE + 0x06E)\r | |
53 | #define SDRC_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x070)\r | |
54 | #define SDRC_DQS0 (SYSTEM_CONTROL_MODULE_BASE + 0x072)\r | |
55 | #define SDRC_CKE0 (SYSTEM_CONTROL_MODULE_BASE + 0x262)\r | |
56 | #define SDRC_CKE1 (SYSTEM_CONTROL_MODULE_BASE + 0x264)\r | |
57 | #define SDRC_DQS1 (SYSTEM_CONTROL_MODULE_BASE + 0x074)\r | |
58 | #define SDRC_DQS2 (SYSTEM_CONTROL_MODULE_BASE + 0x076)\r | |
59 | #define SDRC_DQS3 (SYSTEM_CONTROL_MODULE_BASE + 0x078)\r | |
60 | #define GPMC_A1 (SYSTEM_CONTROL_MODULE_BASE + 0x07A)\r | |
61 | #define GPMC_A2 (SYSTEM_CONTROL_MODULE_BASE + 0x07C)\r | |
62 | #define GPMC_A3 (SYSTEM_CONTROL_MODULE_BASE + 0x07E)\r | |
63 | #define GPMC_A4 (SYSTEM_CONTROL_MODULE_BASE + 0x080)\r | |
64 | #define GPMC_A5 (SYSTEM_CONTROL_MODULE_BASE + 0x082)\r | |
65 | #define GPMC_A6 (SYSTEM_CONTROL_MODULE_BASE + 0x084)\r | |
66 | #define GPMC_A7 (SYSTEM_CONTROL_MODULE_BASE + 0x086)\r | |
67 | #define GPMC_A8 (SYSTEM_CONTROL_MODULE_BASE + 0x088)\r | |
68 | #define GPMC_A9 (SYSTEM_CONTROL_MODULE_BASE + 0x08A)\r | |
69 | #define GPMC_A10 (SYSTEM_CONTROL_MODULE_BASE + 0x08C)\r | |
70 | #define GPMC_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x08E)\r | |
71 | #define GPMC_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x090)\r | |
72 | #define GPMC_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x092)\r | |
73 | #define GPMC_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x094)\r | |
74 | #define GPMC_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x096)\r | |
75 | #define GPMC_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x098)\r | |
76 | #define GPMC_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x09A)\r | |
77 | #define GPMC_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x09C)\r | |
78 | #define GPMC_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x09E)\r | |
79 | #define GPMC_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x0A0)\r | |
80 | #define GPMC_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x0A2)\r | |
81 | #define GPMC_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x0A4)\r | |
82 | #define GPMC_D12 (SYSTEM_CONTROL_MODULE_BASE + 0x0A6)\r | |
83 | #define GPMC_D13 (SYSTEM_CONTROL_MODULE_BASE + 0x0A8)\r | |
84 | #define GPMC_D14 (SYSTEM_CONTROL_MODULE_BASE + 0x0AA)\r | |
85 | #define GPMC_D15 (SYSTEM_CONTROL_MODULE_BASE + 0x0AC)\r | |
86 | #define GPMC_NCS0 (SYSTEM_CONTROL_MODULE_BASE + 0x0AE)\r | |
87 | #define GPMC_NCS1 (SYSTEM_CONTROL_MODULE_BASE + 0x0B0)\r | |
88 | #define GPMC_NCS2 (SYSTEM_CONTROL_MODULE_BASE + 0x0B2)\r | |
89 | #define GPMC_NCS3 (SYSTEM_CONTROL_MODULE_BASE + 0x0B4)\r | |
90 | #define GPMC_NCS4 (SYSTEM_CONTROL_MODULE_BASE + 0x0B6)\r | |
91 | #define GPMC_NCS5 (SYSTEM_CONTROL_MODULE_BASE + 0x0B8)\r | |
92 | #define GPMC_NCS6 (SYSTEM_CONTROL_MODULE_BASE + 0x0BA)\r | |
93 | #define GPMC_NCS7 (SYSTEM_CONTROL_MODULE_BASE + 0x0BC)\r | |
94 | #define GPMC_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x0BE)\r | |
95 | #define GPMC_NADV_ALE (SYSTEM_CONTROL_MODULE_BASE + 0x0C0)\r | |
96 | #define GPMC_NOE (SYSTEM_CONTROL_MODULE_BASE + 0x0C2)\r | |
97 | #define GPMC_NWE (SYSTEM_CONTROL_MODULE_BASE + 0x0C4)\r | |
98 | #define GPMC_NBE0_CLE (SYSTEM_CONTROL_MODULE_BASE + 0x0C6)\r | |
99 | #define GPMC_NBE1 (SYSTEM_CONTROL_MODULE_BASE + 0x0C8)\r | |
100 | #define GPMC_NWP (SYSTEM_CONTROL_MODULE_BASE + 0x0CA)\r | |
101 | #define GPMC_WAIT0 (SYSTEM_CONTROL_MODULE_BASE + 0x0CC)\r | |
102 | #define GPMC_WAIT1 (SYSTEM_CONTROL_MODULE_BASE + 0x0CE)\r | |
103 | #define GPMC_WAIT2 (SYSTEM_CONTROL_MODULE_BASE + 0x0D0)\r | |
104 | #define GPMC_WAIT3 (SYSTEM_CONTROL_MODULE_BASE + 0x0D2)\r | |
105 | #define DSS_PCLK (SYSTEM_CONTROL_MODULE_BASE + 0x0D4)\r | |
106 | #define DSS_HSYNC (SYSTEM_CONTROL_MODULE_BASE + 0x0D6)\r | |
107 | #define DSS_PSYNC (SYSTEM_CONTROL_MODULE_BASE + 0x0D8)\r | |
108 | #define DSS_ACBIAS (SYSTEM_CONTROL_MODULE_BASE + 0x0DA)\r | |
109 | #define DSS_DATA0 (SYSTEM_CONTROL_MODULE_BASE + 0x0DC)\r | |
110 | #define DSS_DATA1 (SYSTEM_CONTROL_MODULE_BASE + 0x0DE)\r | |
111 | #define DSS_DATA2 (SYSTEM_CONTROL_MODULE_BASE + 0x0E0)\r | |
112 | #define DSS_DATA3 (SYSTEM_CONTROL_MODULE_BASE + 0x0E2)\r | |
113 | #define DSS_DATA4 (SYSTEM_CONTROL_MODULE_BASE + 0x0E4)\r | |
114 | #define DSS_DATA5 (SYSTEM_CONTROL_MODULE_BASE + 0x0E6)\r | |
115 | #define DSS_DATA6 (SYSTEM_CONTROL_MODULE_BASE + 0x0E8)\r | |
116 | #define DSS_DATA7 (SYSTEM_CONTROL_MODULE_BASE + 0x0EA)\r | |
117 | #define DSS_DATA8 (SYSTEM_CONTROL_MODULE_BASE + 0x0EC)\r | |
118 | #define DSS_DATA9 (SYSTEM_CONTROL_MODULE_BASE + 0x0EE)\r | |
119 | #define DSS_DATA10 (SYSTEM_CONTROL_MODULE_BASE + 0x0F0)\r | |
120 | #define DSS_DATA11 (SYSTEM_CONTROL_MODULE_BASE + 0x0F2)\r | |
121 | #define DSS_DATA12 (SYSTEM_CONTROL_MODULE_BASE + 0x0F4)\r | |
122 | #define DSS_DATA13 (SYSTEM_CONTROL_MODULE_BASE + 0x0F6)\r | |
123 | #define DSS_DATA14 (SYSTEM_CONTROL_MODULE_BASE + 0x0F8)\r | |
124 | #define DSS_DATA15 (SYSTEM_CONTROL_MODULE_BASE + 0x0FA)\r | |
125 | #define DSS_DATA16 (SYSTEM_CONTROL_MODULE_BASE + 0x0FC)\r | |
126 | #define DSS_DATA17 (SYSTEM_CONTROL_MODULE_BASE + 0x0FE)\r | |
127 | #define DSS_DATA18 (SYSTEM_CONTROL_MODULE_BASE + 0x100)\r | |
128 | #define DSS_DATA19 (SYSTEM_CONTROL_MODULE_BASE + 0x102)\r | |
129 | #define DSS_DATA20 (SYSTEM_CONTROL_MODULE_BASE + 0x104)\r | |
130 | #define DSS_DATA21 (SYSTEM_CONTROL_MODULE_BASE + 0x106)\r | |
131 | #define DSS_DATA22 (SYSTEM_CONTROL_MODULE_BASE + 0x108)\r | |
132 | #define DSS_DATA23 (SYSTEM_CONTROL_MODULE_BASE + 0x10A)\r | |
133 | #define CAM_HS (SYSTEM_CONTROL_MODULE_BASE + 0x10C)\r | |
134 | #define CAM_VS (SYSTEM_CONTROL_MODULE_BASE + 0x10E)\r | |
135 | #define CAM_XCLKA (SYSTEM_CONTROL_MODULE_BASE + 0x110)\r | |
136 | #define CAM_PCLK (SYSTEM_CONTROL_MODULE_BASE + 0x112)\r | |
137 | #define CAM_FLD (SYSTEM_CONTROL_MODULE_BASE + 0x114)\r | |
138 | #define CAM_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x116)\r | |
139 | #define CAM_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x118)\r | |
140 | #define CAM_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x11A)\r | |
141 | #define CAM_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x11C)\r | |
142 | #define CAM_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x11E)\r | |
143 | #define CAM_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x120)\r | |
144 | #define CAM_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x122)\r | |
145 | #define CAM_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x124)\r | |
146 | #define CAM_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x126)\r | |
147 | #define CAM_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x128)\r | |
148 | #define CAM_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x12A)\r | |
149 | #define CAM_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x12C)\r | |
150 | #define CAM_XCLKB (SYSTEM_CONTROL_MODULE_BASE + 0x12E)\r | |
151 | #define CAM_WEN (SYSTEM_CONTROL_MODULE_BASE + 0x130)\r | |
152 | #define CAM_STROBE (SYSTEM_CONTROL_MODULE_BASE + 0x132)\r | |
153 | #define CSI2_DX0 (SYSTEM_CONTROL_MODULE_BASE + 0x134)\r | |
154 | #define CSI2_DY0 (SYSTEM_CONTROL_MODULE_BASE + 0x136)\r | |
155 | #define CSI2_DX1 (SYSTEM_CONTROL_MODULE_BASE + 0x138)\r | |
156 | #define CSI2_DY1 (SYSTEM_CONTROL_MODULE_BASE + 0x13A)\r | |
157 | #define MCBSP2_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x13C)\r | |
158 | #define MCBSP2_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x13E)\r | |
159 | #define MCBSP2_DR (SYSTEM_CONTROL_MODULE_BASE + 0x140)\r | |
160 | #define MCBSP2_DX (SYSTEM_CONTROL_MODULE_BASE + 0x142)\r | |
161 | #define MMC1_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x144)\r | |
162 | #define MMC1_CMD (SYSTEM_CONTROL_MODULE_BASE + 0x146)\r | |
163 | #define MMC1_DAT0 (SYSTEM_CONTROL_MODULE_BASE + 0x148)\r | |
164 | #define MMC1_DAT1 (SYSTEM_CONTROL_MODULE_BASE + 0x14A)\r | |
165 | #define MMC1_DAT2 (SYSTEM_CONTROL_MODULE_BASE + 0x14C)\r | |
166 | #define MMC1_DAT3 (SYSTEM_CONTROL_MODULE_BASE + 0x14E)\r | |
167 | #define MMC1_DAT4 (SYSTEM_CONTROL_MODULE_BASE + 0x150)\r | |
168 | #define MMC1_DAT5 (SYSTEM_CONTROL_MODULE_BASE + 0x152)\r | |
169 | #define MMC1_DAT6 (SYSTEM_CONTROL_MODULE_BASE + 0x154)\r | |
170 | #define MMC1_DAT7 (SYSTEM_CONTROL_MODULE_BASE + 0x156)\r | |
171 | #define MMC2_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x158)\r | |
172 | #define MMC2_CMD (SYSTEM_CONTROL_MODULE_BASE + 0x15A)\r | |
173 | #define MMC2_DAT0 (SYSTEM_CONTROL_MODULE_BASE + 0x15C)\r | |
174 | #define MMC2_DAT1 (SYSTEM_CONTROL_MODULE_BASE + 0x15E)\r | |
175 | #define MMC2_DAT2 (SYSTEM_CONTROL_MODULE_BASE + 0x160)\r | |
176 | #define MMC2_DAT3 (SYSTEM_CONTROL_MODULE_BASE + 0x162)\r | |
177 | #define MMC2_DAT4 (SYSTEM_CONTROL_MODULE_BASE + 0x164)\r | |
178 | #define MMC2_DAT5 (SYSTEM_CONTROL_MODULE_BASE + 0x166)\r | |
179 | #define MMC2_DAT6 (SYSTEM_CONTROL_MODULE_BASE + 0x168)\r | |
180 | #define MMC2_DAT7 (SYSTEM_CONTROL_MODULE_BASE + 0x16A)\r | |
181 | #define MCBSP3_DX (SYSTEM_CONTROL_MODULE_BASE + 0x16C)\r | |
182 | #define MCBSP3_DR (SYSTEM_CONTROL_MODULE_BASE + 0x16E)\r | |
183 | #define MCBSP3_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x170)\r | |
184 | #define MCBSP3_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x172)\r | |
185 | #define UART2_CTS (SYSTEM_CONTROL_MODULE_BASE + 0x174)\r | |
186 | #define UART2_RTS (SYSTEM_CONTROL_MODULE_BASE + 0x176)\r | |
187 | #define UART2_TX (SYSTEM_CONTROL_MODULE_BASE + 0x178)\r | |
188 | #define UART2_RX (SYSTEM_CONTROL_MODULE_BASE + 0x17A)\r | |
189 | #define UART1_TX (SYSTEM_CONTROL_MODULE_BASE + 0x17C)\r | |
190 | #define UART1_RTS (SYSTEM_CONTROL_MODULE_BASE + 0x17E)\r | |
191 | #define UART1_CTS (SYSTEM_CONTROL_MODULE_BASE + 0x180)\r | |
192 | #define UART1_RX (SYSTEM_CONTROL_MODULE_BASE + 0x182)\r | |
193 | #define MCBSP4_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x184)\r | |
194 | #define MCBSP4_DR (SYSTEM_CONTROL_MODULE_BASE + 0x186)\r | |
195 | #define MCBSP4_DX (SYSTEM_CONTROL_MODULE_BASE + 0x188)\r | |
196 | #define MCBSP4_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x18A)\r | |
197 | #define MCBSP1_CLKR (SYSTEM_CONTROL_MODULE_BASE + 0x18C)\r | |
198 | #define MCBSP1_FSR (SYSTEM_CONTROL_MODULE_BASE + 0x18E)\r | |
199 | #define MCBSP1_DX (SYSTEM_CONTROL_MODULE_BASE + 0x190)\r | |
200 | #define MCBSP1_DR (SYSTEM_CONTROL_MODULE_BASE + 0x192)\r | |
201 | #define MCBSP1_CLKS (SYSTEM_CONTROL_MODULE_BASE + 0x194)\r | |
202 | #define MCBSP1_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x196)\r | |
203 | #define MCBSP1_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x198)\r | |
204 | #define UART3_CTS_RCTX (SYSTEM_CONTROL_MODULE_BASE + 0x19A)\r | |
205 | #define UART3_RTS_SD (SYSTEM_CONTROL_MODULE_BASE + 0x19C)\r | |
206 | #define UART3_RX_IRRX (SYSTEM_CONTROL_MODULE_BASE + 0x19E)\r | |
207 | #define UART3_TX_IRTX (SYSTEM_CONTROL_MODULE_BASE + 0x1A0)\r | |
208 | #define HSUSB0_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x1A2)\r | |
209 | #define HSUSB0_STP (SYSTEM_CONTROL_MODULE_BASE + 0x1A4)\r | |
210 | #define HSUSB0_DIR (SYSTEM_CONTROL_MODULE_BASE + 0x1A6)\r | |
211 | #define HSUSB0_NXT (SYSTEM_CONTROL_MODULE_BASE + 0x1A8)\r | |
212 | #define HSUSB0_DATA0 (SYSTEM_CONTROL_MODULE_BASE + 0x1AA)\r | |
213 | #define HSUSB0_DATA1 (SYSTEM_CONTROL_MODULE_BASE + 0x1AC)\r | |
214 | #define HSUSB0_DATA2 (SYSTEM_CONTROL_MODULE_BASE + 0x1AE)\r | |
215 | #define HSUSB0_DATA3 (SYSTEM_CONTROL_MODULE_BASE + 0x1B0)\r | |
216 | #define HSUSB0_DATA4 (SYSTEM_CONTROL_MODULE_BASE + 0x1B2)\r | |
217 | #define HSUSB0_DATA5 (SYSTEM_CONTROL_MODULE_BASE + 0x1B4)\r | |
218 | #define HSUSB0_DATA6 (SYSTEM_CONTROL_MODULE_BASE + 0x1B6)\r | |
219 | #define HSUSB0_DATA7 (SYSTEM_CONTROL_MODULE_BASE + 0x1B8)\r | |
220 | #define I2C1_SCL (SYSTEM_CONTROL_MODULE_BASE + 0x1BA)\r | |
221 | #define I2C1_SDA (SYSTEM_CONTROL_MODULE_BASE + 0x1BC)\r | |
222 | #define I2C2_SCL (SYSTEM_CONTROL_MODULE_BASE + 0x1BE)\r | |
223 | #define I2C2_SDA (SYSTEM_CONTROL_MODULE_BASE + 0x1C0)\r | |
224 | #define I2C3_SCL (SYSTEM_CONTROL_MODULE_BASE + 0x1C2)\r | |
225 | #define I2C3_SDA (SYSTEM_CONTROL_MODULE_BASE + 0x1C4)\r | |
226 | #define HDQ_SIO (SYSTEM_CONTROL_MODULE_BASE + 0x1C6)\r | |
227 | #define MCSPI1_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x1C8)\r | |
228 | #define MCSPI1_SIMO (SYSTEM_CONTROL_MODULE_BASE + 0x1CA)\r | |
229 | #define MCSPI1_SOMI (SYSTEM_CONTROL_MODULE_BASE + 0x1CC)\r | |
230 | #define MCSPI1_CS0 (SYSTEM_CONTROL_MODULE_BASE + 0x1CE)\r | |
231 | #define MCSPI1_CS1 (SYSTEM_CONTROL_MODULE_BASE + 0x1D0)\r | |
232 | #define MCSPI1_CS2 (SYSTEM_CONTROL_MODULE_BASE + 0x1D2)\r | |
233 | #define MCSPI1_CS3 (SYSTEM_CONTROL_MODULE_BASE + 0x1D4)\r | |
234 | #define MCSPI2_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x1D6)\r | |
235 | #define MCSPI2_SIMO (SYSTEM_CONTROL_MODULE_BASE + 0x1D8)\r | |
236 | #define MCSPI2_SOMI (SYSTEM_CONTROL_MODULE_BASE + 0x1DA)\r | |
237 | #define MCSPI2_CS0 (SYSTEM_CONTROL_MODULE_BASE + 0x1DC)\r | |
238 | #define MCSPI2_CS1 (SYSTEM_CONTROL_MODULE_BASE + 0x1DE)\r | |
239 | #define SYS_NIRQ (SYSTEM_CONTROL_MODULE_BASE + 0x1E0)\r | |
240 | #define SYS_CLKOUT2 (SYSTEM_CONTROL_MODULE_BASE + 0x1E2)\r | |
241 | #define ETK_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x5D8)\r | |
242 | #define ETK_CTL (SYSTEM_CONTROL_MODULE_BASE + 0x5DA)\r | |
243 | #define ETK_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x5DC)\r | |
244 | #define ETK_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x5DE)\r | |
245 | #define ETK_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x5E0)\r | |
246 | #define ETK_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x5E2)\r | |
247 | #define ETK_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x5E4)\r | |
248 | #define ETK_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x5E6)\r | |
249 | #define ETK_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x5E8)\r | |
250 | #define ETK_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x5EA)\r | |
251 | #define ETK_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x5EC)\r | |
252 | #define ETK_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x5EE)\r | |
253 | #define ETK_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x5F0)\r | |
254 | #define ETK_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x5F2)\r | |
255 | #define ETK_D12 (SYSTEM_CONTROL_MODULE_BASE + 0x5F4)\r | |
256 | #define ETK_D13 (SYSTEM_CONTROL_MODULE_BASE + 0x5F6)\r | |
257 | #define ETK_D14 (SYSTEM_CONTROL_MODULE_BASE + 0x5F8)\r | |
258 | #define ETK_D15 (SYSTEM_CONTROL_MODULE_BASE + 0x5FA)\r | |
259 | #define SYS_BOOT0 (SYSTEM_CONTROL_MODULE_BASE + 0xA0A)\r | |
260 | #define SYS_BOOT1 (SYSTEM_CONTROL_MODULE_BASE + 0xA0C)\r | |
261 | #define SYS_BOOT3 (SYSTEM_CONTROL_MODULE_BASE + 0xA10)\r | |
262 | #define SYS_BOOT4 (SYSTEM_CONTROL_MODULE_BASE + 0xA12)\r | |
263 | #define SYS_BOOT5 (SYSTEM_CONTROL_MODULE_BASE + 0xA14)\r | |
264 | #define SYS_BOOT6 (SYSTEM_CONTROL_MODULE_BASE + 0xA16)\r | |
265 | \r | |
266 | //Mux modes\r | |
267 | #define MUXMODE0 (0x0UL)\r | |
268 | #define MUXMODE1 (0x1UL)\r | |
269 | #define MUXMODE2 (0x2UL)\r | |
270 | #define MUXMODE3 (0x3UL)\r | |
271 | #define MUXMODE4 (0x4UL)\r | |
272 | #define MUXMODE5 (0x5UL)\r | |
273 | #define MUXMODE6 (0x6UL)\r | |
274 | #define MUXMODE7 (0x7UL)\r | |
275 | \r | |
276 | //Pad configuration register.\r | |
277 | #define PAD_CONFIG_MASK (0xFFFFUL)\r | |
278 | #define MUXMODE_OFFSET 0\r | |
279 | #define MUXMODE_MASK (0x7UL << MUXMODE_OFFSET)\r | |
280 | #define PULL_CONFIG_OFFSET 3\r | |
281 | #define PULL_CONFIG_MASK (0x3UL << PULL_CONFIG_OFFSET)\r | |
282 | #define INPUTENABLE_OFFSET 8\r | |
283 | #define INPUTENABLE_MASK (0x1UL << INPUTENABLE_OFFSET)\r | |
284 | #define OFFMODE_VALUE_OFFSET 9\r | |
285 | #define OFFMODE_VALUE_MASK (0x1FUL << OFFMODE_VALUE_OFFSET)\r | |
286 | #define WAKEUP_OFFSET 14\r | |
287 | #define WAKEUP_MASK (0x2UL << WAKEUP_OFFSET)\r | |
288 | \r | |
289 | #define PULL_DOWN_SELECTED ((0x0UL << 1) | BIT0)\r | |
290 | #define PULL_UP_SELECTED (BIT1 | BIT0)\r | |
291 | #define PULL_DISABLED (0x0UL << 0)\r | |
292 | \r | |
293 | #define OUTPUT (0x0UL) //Pin is configured in output only mode.\r | |
294 | #define INPUT (0x1UL) //Pin is configured in bi-directional mode.\r | |
295 | \r | |
296 | typedef struct {\r | |
297 | UINTN Pin;\r | |
298 | UINTN MuxMode;\r | |
299 | UINTN PullConfig;\r | |
300 | UINTN InputEnable;\r | |
301 | } PAD_CONFIGURATION;\r | |
302 | \r | |
303 | #endif //__OMAP3530_PAD_CONFIGURATION_H__\r |