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Commit | Line | Data |
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7b202cb0 | 1 | ## @file\r |
49ba9447 | 2 | # EFI/Framework Open Virtual Machine Firmware (OVMF) platform\r |
3 | #\r | |
10fa47e5 | 4 | # Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r |
49ba9447 | 5 | #\r |
b26f0cf9 | 6 | # SPDX-License-Identifier: BSD-2-Clause-Patent\r |
49ba9447 | 7 | #\r |
7b202cb0 | 8 | ##\r |
49ba9447 | 9 | \r |
10 | [Defines]\r | |
46293a42 | 11 | DEC_SPECIFICATION = 0x00010005\r |
49ba9447 | 12 | PACKAGE_NAME = OvmfPkg\r |
13 | PACKAGE_GUID = 2daf5f34-50e5-4b9d-b8e3-5562334d87e5\r | |
14 | PACKAGE_VERSION = 0.1\r | |
15 | \r | |
50944545 | 16 | [Includes]\r |
17 | Include\r | |
18 | \r | |
28b29a70 | 19 | [LibraryClasses]\r |
f6c6c020 | 20 | ## @libraryclass Loads and boots a Linux kernel image\r |
21 | #\r | |
22 | LoadLinuxLib|Include/Library/LoadLinuxLib.h\r | |
23 | \r | |
28b29a70 | 24 | ## @libraryclass Save and restore variables using a file\r |
25 | #\r | |
26 | NvVarsFileLib|Include/Library/NvVarsFileLib.h\r | |
27 | \r | |
392a3146 LE |
28 | ## @libraryclass Provides services to work with PCI capabilities in PCI\r |
29 | # config space.\r | |
30 | PciCapLib|Include/Library/PciCapLib.h\r | |
31 | \r | |
02b9a834 LE |
32 | ## @libraryclass Layered on top of PciCapLib, allows clients to plug an\r |
33 | # EFI_PCI_IO_PROTOCOL backend into PciCapLib, for config\r | |
34 | # space access.\r | |
35 | PciCapPciIoLib|Include/Library/PciCapPciIoLib.h\r | |
36 | \r | |
6a744d40 LE |
37 | ## @libraryclass Layered on top of PciCapLib, allows clients to plug a\r |
38 | # PciSegmentLib backend into PciCapLib, for config space\r | |
39 | # access.\r | |
40 | PciCapPciSegmentLib|Include/Library/PciCapPciSegmentLib.h\r | |
41 | \r | |
77874cee LE |
42 | ## @libraryclass Register a status code handler for printing the Boot\r |
43 | # Manager's LoadImage() and StartImage() preparations, and\r | |
44 | # return codes, to the UEFI console.\r | |
45 | PlatformBmPrintScLib|Include/Library/PlatformBmPrintScLib.h\r | |
46 | \r | |
f1ec65ba | 47 | ## @libraryclass Access QEMU's firmware configuration interface\r |
48 | #\r | |
49 | QemuFwCfgLib|Include/Library/QemuFwCfgLib.h\r | |
50 | \r | |
f70b071e LE |
51 | ## @libraryclass S3 support for QEMU fw_cfg\r |
52 | #\r | |
53 | QemuFwCfgS3Lib|Include/Library/QemuFwCfgS3Lib.h\r | |
54 | \r | |
cca7475b LE |
55 | ## @libraryclass Rewrite the BootOrder NvVar based on QEMU's "bootorder"\r |
56 | # fw_cfg file.\r | |
57 | #\r | |
58 | QemuBootOrderLib|Include/Library/QemuBootOrderLib.h\r | |
59 | \r | |
28b29a70 | 60 | ## @libraryclass Serialize (and deserialize) variables\r |
61 | #\r | |
62 | SerializeVariablesLib|Include/Library/SerializeVariablesLib.h\r | |
63 | \r | |
cd8ff8fd AB |
64 | ## @libraryclass Invoke Xen hypercalls\r |
65 | #\r | |
66 | XenHypercallLib|Include/Library/XenHypercallLib.h\r | |
67 | \r | |
0169352e AB |
68 | ## @libraryclass Manage XenBus device path and I/O handles\r |
69 | #\r | |
70 | XenIoMmioLib|Include/Library/XenIoMmioLib.h\r | |
71 | \r | |
7b202cb0 | 72 | [Guids]\r |
29ebe47c LE |
73 | gUefiOvmfPkgTokenSpaceGuid = {0x93bb96af, 0xb9f2, 0x4eb8, {0x94, 0x62, 0xe0, 0xba, 0x74, 0x56, 0x42, 0x36}}\r |
74 | gEfiXenInfoGuid = {0xd3b46f3b, 0xd441, 0x1244, {0x9a, 0x12, 0x0, 0x12, 0x27, 0x3f, 0xc1, 0x4d}}\r | |
75 | gOvmfPlatformConfigGuid = {0x7235c51c, 0x0c80, 0x4cab, {0x87, 0xac, 0x3b, 0x08, 0x4a, 0x63, 0x04, 0xb1}}\r | |
76 | gVirtioMmioTransportGuid = {0x837dca9e, 0xe874, 0x4d82, {0xb2, 0x9a, 0x23, 0xfe, 0x0e, 0x23, 0xd1, 0xe2}}\r | |
2c123c14 | 77 | gQemuRamfbGuid = {0x557423a1, 0x63ab, 0x406c, {0xbe, 0x7e, 0x91, 0xcd, 0xbc, 0x08, 0xc4, 0x57}}\r |
29ebe47c | 78 | gXenBusRootDeviceGuid = {0xa732241f, 0x383d, 0x4d9c, {0x8a, 0xe1, 0x8e, 0x09, 0x83, 0x75, 0x89, 0xd7}}\r |
9116c9c5 | 79 | gRootBridgesConnectedEventGroupGuid = {0x24a2d66f, 0xeedd, 0x4086, {0x90, 0x42, 0xf2, 0x6e, 0x47, 0x97, 0xee, 0x69}}\r |
49ba9447 | 80 | \r |
b0f51446 | 81 | [Protocols]\r |
29ebe47c | 82 | gVirtioDeviceProtocolGuid = {0xfa920010, 0x6785, 0x4941, {0xb6, 0xec, 0x49, 0x8c, 0x57, 0x9f, 0x16, 0x0a}}\r |
29ebe47c LE |
83 | gXenBusProtocolGuid = {0x3d3ca290, 0xb9a5, 0x11e3, {0xb7, 0x5d, 0xb8, 0xac, 0x6f, 0x7d, 0x65, 0xe6}}\r |
84 | gXenIoProtocolGuid = {0x6efac84f, 0x0ab0, 0x4747, {0x81, 0xbe, 0x85, 0x55, 0x62, 0x59, 0x04, 0x49}}\r | |
c5d736eb | 85 | gIoMmuAbsentProtocolGuid = {0xf8775d50, 0x8abd, 0x4adf, {0x92, 0xac, 0x85, 0x3e, 0x51, 0xf6, 0xc8, 0xdc}}\r |
10fa47e5 | 86 | gEfiLegacy8259ProtocolGuid = {0x38321dba, 0x4fe0, 0x4e17, {0x8a, 0xec, 0x41, 0x30, 0x55, 0xea, 0xed, 0xc1}}\r |
b0f51446 | 87 | \r |
61069836 | 88 | [PcdsFixedAtBuild]\r |
b36f701d JJ |
89 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase|0x0|UINT32|0\r |
90 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSize|0x0|UINT32|1\r | |
91 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase|0x0|UINT32|0x15\r | |
92 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize|0x0|UINT32|0x16\r | |
61069836 | 93 | \r |
b90aefa9 | 94 | ## This flag is used to control the destination port for PlatformDebugLibIoPort\r |
95 | gUefiOvmfPkgTokenSpaceGuid.PcdDebugIoPort|0x402|UINT16|4\r | |
96 | \r | |
37078a63 | 97 | ## When VirtioScsiDxe is instantiated for a HBA, the numbers of targets and\r |
98 | # LUNs are retrieved from the host during virtio-scsi setup.\r | |
99 | # MdeModulePkg/Bus/Scsi/ScsiBusDxe then scans all MaxTarget * MaxLun\r | |
100 | # possible devices. This can take extremely long, for example with\r | |
101 | # MaxTarget=255 and MaxLun=16383. The *inclusive* constants below limit\r | |
102 | # MaxTarget and MaxLun, independently, should the host report higher values,\r | |
103 | # so that scanning the number of devices given by their product is still\r | |
104 | # acceptably fast.\r | |
105 | gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxTargetLimit|31|UINT16|6\r | |
106 | gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxLunLimit|7|UINT32|7\r | |
107 | \r | |
501e08fc JJ |
108 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogBase|0x0|UINT32|0x8\r |
109 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogSize|0x0|UINT32|0x9\r | |
110 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize|0x0|UINT32|0xa\r | |
111 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareBlockSize|0|UINT32|0xb\r | |
112 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase|0x0|UINT32|0xc\r | |
113 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwSpareBase|0x0|UINT32|0xd\r | |
114 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase|0x0|UINT32|0xe\r | |
115 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress|0x0|UINT32|0xf\r | |
b382ede3 JJ |
116 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase|0x0|UINT32|0x11\r |
117 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesSize|0x0|UINT32|0x12\r | |
7cb6b0e0 JJ |
118 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase|0x0|UINT32|0x13\r |
119 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize|0x0|UINT32|0x14\r | |
6a7cba79 LE |
120 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageBase|0x0|UINT32|0x18\r |
121 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageSize|0x0|UINT32|0x19\r | |
ad43bc6b | 122 | gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize|0x0|UINT32|0x1a\r |
9beac0d8 | 123 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd|0x0|UINT32|0x1f\r |
501e08fc | 124 | \r |
460ffed2 HW |
125 | ## Pcd8259LegacyModeMask defines the default mask value for platform. This\r |
126 | # value is determined.\r | |
127 | # 1) If platform only support pure UEFI, value should be set to 0xFFFF or\r | |
128 | # 0xFFFE; Because only clock interrupt is allowed in legacy mode in pure\r | |
129 | # UEFI platform.\r | |
130 | # 2) If platform install CSM and use thunk module:\r | |
131 | # a) If thunk call provided by CSM binary requires some legacy interrupt\r | |
132 | # support, the corresponding bit should be opened as 0.\r | |
133 | # For example, if keyboard interfaces provided CSM binary use legacy\r | |
134 | # keyboard interrupt in 8259 bit 1, then the value should be set to\r | |
135 | # 0xFFFC.\r | |
136 | # b) If all thunk call provied by CSM binary do not require legacy\r | |
137 | # interrupt support, value should be set to 0xFFFF or 0xFFFE.\r | |
138 | #\r | |
139 | # The default value of legacy mode mask could be changed by\r | |
140 | # EFI_LEGACY_8259_PROTOCOL->SetMask(). But it is rarely need change it\r | |
141 | # except some special cases such as when initializing the CSM binary, it\r | |
142 | # should be set to 0xFFFF to mask all legacy interrupt. Please restore the\r | |
143 | # original legacy mask value if changing is made for these special case.\r | |
144 | gUefiOvmfPkgTokenSpaceGuid.Pcd8259LegacyModeMask|0xFFFF|UINT16|0x3\r | |
145 | \r | |
146 | ## Pcd8259LegacyModeEdgeLevel defines the default edge level for legacy\r | |
147 | # mode's interrrupt controller.\r | |
148 | # For the corresponding bits, 0 = Edge triggered and 1 = Level triggered.\r | |
149 | gUefiOvmfPkgTokenSpaceGuid.Pcd8259LegacyModeEdgeLevel|0x0000|UINT16|0x5\r | |
150 | \r | |
70c66df5 | 151 | [PcdsDynamic, PcdsDynamicEx]\r |
85c0b5ee | 152 | gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent|0|UINT64|2\r |
9d35ac26 | 153 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable|FALSE|BOOLEAN|0x10\r |
d55004da | 154 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId|0|UINT16|0x1b\r |
6fbef93e | 155 | gUefiOvmfPkgTokenSpaceGuid.PcdQemuSmbiosValidated|FALSE|BOOLEAN|0x21\r |
49ba9447 | 156 | \r |
c4df7fd0 LE |
157 | ## The IO port aperture shared by all PCI root bridges.\r |
158 | #\r | |
159 | gUefiOvmfPkgTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x22\r | |
160 | gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x23\r | |
161 | \r | |
03845e90 LE |
162 | ## The 32-bit MMIO aperture shared by all PCI root bridges.\r |
163 | #\r | |
164 | gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT64|0x24\r | |
165 | gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT64|0x25\r | |
166 | \r | |
7e5b1b67 LE |
167 | ## The 64-bit MMIO aperture shared by all PCI root bridges.\r |
168 | #\r | |
169 | gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x26\r | |
170 | gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x27\r | |
171 | \r | |
966dbaf4 | 172 | ## The following setting controls how many megabytes we configure as TSEG on\r |
d04b72c6 LE |
173 | # Q35, for SMRAM purposes. Permitted defaults are: 1, 2, 8. Other defaults\r |
174 | # cause undefined behavior. During boot, the PCD is updated by PlatformPei\r | |
175 | # to reflect the extended TSEG size, if one is advertized by QEMU.\r | |
966dbaf4 | 176 | #\r |
d04b72c6 | 177 | # This PCD is only accessed if PcdSmmSmramRequire is TRUE (see below).\r |
966dbaf4 LE |
178 | gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8|UINT16|0x20\r |
179 | \r | |
e05061c5 | 180 | [PcdsFeatureFlag]\r |
2f9c55cc | 181 | gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation|TRUE|BOOLEAN|0x1c\r |
43336916 | 182 | gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation|FALSE|BOOLEAN|0x1d\r |
1f695483 LE |
183 | \r |
184 | ## This feature flag enables SMM/SMRAM support. Note that it also requires\r | |
185 | # such support from the underlying QEMU instance; if that support is not\r | |
186 | # present, the firmware will reject continuing after a certain point.\r | |
187 | #\r | |
188 | # The flag also acts as a general "security switch"; when TRUE, many\r | |
189 | # components will change behavior, with the goal of preventing a malicious\r | |
190 | # runtime OS from tampering with firmware structures (special memory ranges\r | |
191 | # used by OVMF, the varstore pflash chip, LockBox etc).\r | |
192 | gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire|FALSE|BOOLEAN|0x1e\r |